Online proceedings - EDA Publishing Association

7-9 October 2009, Leuven, Belgium
supply voltage of 1.2V in this technology, the frequency
In conventional CMOS processes the overall circuit reduces with increasing temperature, while below this voltage
performance reduces dramatically with increasing the effect is opposite. For the same ring oscillator fabricated
temperatures, because the effect of the mobility reduction in with a standard V T , this ZTC is reduced to 0.95 V.
the transistor current, represented by β□, was traditionally As a result of this varying temperature behaviour, the worstcase
and best-case corners for simulation need to be
much larger than the effect of the reduction of the threshold
voltage V T . This was one of the reasons to keep high-speed reconsidered, since for modern CMOS technologies a higher
processors cool, by using a fan. Also worst-case corner temperature not automatically corresponds to a lower
simulations were usually done at high temperatures. performance! For the 45nm technology node and beyond, the
However, today's CMOS technologies offer several different temperature effect will diminish further, because of an
threshold voltages to support both high-speed and lowleakage
increasing compensation of the β□ and V T contributions to the
applications. For general-purpose and high-speed transistor current [8].
processes, V T is relatively low and a further reduction with ZTC also has consequences for certain failure analysis methods
0.7mV/ 0 C has less influence on this speed than the reduction that use local heating to detect changes in circuit behaviour,
in the β□.
because these changes will become smaller and less visible in
For low-leakage processes, with a relatively large V T , both modern technologies [9].
effects partly compensate each other, because of the From the above it is clear that thermal simulations on ICs in
increasing competition between mobility and threshold advanced CMOS technologies are very important to verify
voltage, so that there is a reduced influence on the speed. At whether the maximum temperature does not exceed the
a certain supply voltage the above two mechanisms fully specified temperature, and that the temperature variations
cancel each others contribution to the transistor current, such across the die remain limited to avoid potential mechanical
that the circuit speed has no longer a relation with the stress in and between the all physical compounds of the
temperature. This is the so-called zero-temperaturecoefficient
package mounted on a board. However, thermal simulations
(ZTC) voltage [5]. This reducing temperature have become less important for the prediction of the
dependence, which is expected to continue with further performance variations across the die, due to the weaker impact
scaling of the supply voltage, has serious consequences for of the temperature on the current behaviour of the individual
the static timing analysis, as it may invalidate the approach transistors.
of defining PVT (process, voltage and temperature) corners,
by independently varying voltage and temperature [6].
Figure 2 shows the frequency response of a high-V T ring
oscillator as a function of the supply voltage, for different
operating temperatures [7].
Fig. 2. Ring oscillator frequency responses as a function of the supply
voltage at different temperatures.
Above the ZTC voltage of 1.1 V, which is close to the nominal
IV. CONCLUSIONS
On-chip temperature variations had a relatively large impact on
the performance of the various cores on a die in conventional
CMOS technologies. In an advanced 45nm CMOS technology,
however, the relation between the temperature and the
performance is much weaker, because the reduction in
mobility, due to a higher temperature, is greatly compensated
by a reduction in the threshold voltage. However, prediction of
the absolute temperature is still important to meet the
specification requirements of the application. Next to that, it is
also important to limit the temperature variations across the
mounted die in order to reduce mechanical stress.
Therefore, extensive thermal simulations have been performed
for a complex video and graphics processing chip made for
digital TV applications. The target was to create an overall
temperature distribution diagram across the die, based on an
accurate compact model that includes all compounds from dieto-package-to-board.
The first floorplan of the chip showed a
temperature distribution in which the temperature variations
were too large for the targeted application area. This has led to
a change in the floorplan of the cores on the die. The final
floorplan resulted in a maximum temperature variation over the
die of 5 0 C, compared to the variation of 23 0 C of the original
floorplan.
©EDA Publishing/THERMINIC 2009 34
ISBN: 978-2-35500-010-2