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7-9 October 2009, Leuven, Belgium sink performances, and load resistances. The TE model was used to determine the maximum power generations and efficiencies associated with the optimized pellet geometries. Optimized pellet height was found to be 10mm. The result suggests that the temperature difference across pellets is a dominant parameter affecting power generations and efficiencies. The parametric study showed that generation efficiencies associated with different load resistances are very similar to each other despite 20 times difference between two load resistances. The study showed that generation efficiency decreases, e.g. 7.4% to 6.4% at a source heat flow of 20W, as the thermal resistance between the TEG cold side and the ambient increases from 0.1K/W to 1K/W. The decrease of the temperature difference across the TEG induced by the increase of the net thermal resistance of the module can explain the degradation of the generation efficiency. ACKNOWLEDGMENT We would like to thank Todd Salamon in Bell Labs, Alcatel- Lucent for the constructive discussion regarding this work. This work was supported by IDA Ireland. REFERENCES [1] G. Fischer, “Next-generation base station radio frequency architecture”, Bell Labs Tech. J., vol. 12, no. 2, pp. 3–18, 2007 [2] K.Ikoma, M.Munekiyo, K.Furuya, M.Kobayashi, T.Izumi, and K.Shinohara, “Thermoelectric module and generator for gasoline engine vehicles”, Proc. 17th Int. Conf. on Thermoelectrics, Nagoya, Japan, May 1998, pp. 464-467 [3] J. G. Haidar, J. I. Ghojel, “Waste heat recovery from the exhaust of lowpower diesel engine using thermoelectric generators”, Proc. 20th Int. Conf. on Thermoelectrics, Beijing, China, June 2001, pp. 413-417 [4] T. Kajikawa, “Status and future prospects on the development of thermoelectric power generation systems utilizing combustion heat from municipal solid waste”, Proc. 16th Int. Conf. on Thermoelectrics, Dresden, Germany, August 1997, pp. 28-36 [5] G. L. Solbrekken, K. Yazawa,A. Bar-Cohen, “Heat driven cooling of portable electronics using thermoelectric technology”, IEEE T. Adv. Packaging, vol. 31, no. 2, pp. 429-437, May 2008 [6] S. Maneewan, J. Khedari, B. Zeghmati, J. Hirunlabh and J. Eakburanawat, “Experimental investigation on generated power of thermoelectric roof solar collector”, Proc. 22nd Int. Conf. on Thermoelectrics, Montpellier, France, August 2003, pp. 574-577 [7] Suski and D. Edward, “Method and apparatus for recovering power from semiconductor circuit using thermoelectric device,” U.S. Patent 5 419 780, May 30, 1995. [8] K. Yazawa, G. L. Solbrekken, and A. Bar-Cohen, “Thermoelectric powered convective cooling of microprocessors,” IEEE T. Adv. Packaging, vol. 28, no. 2, pp. 231–239, May 2005. [9] T. C. Harman, P. J. Taylor, M. P. Walsh, B. E. LaForge, “Quantum dot superlattice thermoelectric materials and devices”, Science, vol. 297, pp. 2229-2232, September 2002 [10] R. Venkatasubramanian, E. Siivola, T. Colpitts, B. O'Quinn, “Thin-film thermoelectric devices with high room-temperature figures of merit”, Nature, vol. 413, pp. 597-602, October 2001 [11] K. F. Hsu, S. Loo, F. Guo, W. Chen, J. S. Dyck, C. Uher, T. Hogan, E. K. Polychroniadis, M. G. Kanatzidis, “Cubic AgPb mSbTe 2+m: Bulk thermoelectric materials with high figure of merit”, Science, vol. 303, pp. 818-821, February 2004 [12] A. I. Hochbaum, R. Chen, R. D. Delgado, W. Liang, E. C. Garnett, M. Najarian, A. Majumdar, P. Yang, “Enhanced thermoelectric performance of rough silicon nanowires”, Nature, vol. 451, pp. 163-167, January 2008 [13] A. I. Boukai, Y. Bunimovich, J. Tahir-Kheli, J.-K. Yu, W. A. Goddard III ,J. R. Heath , “Silicon nanowires as efficient thermoelectric materials”, Nature, vol. 451, pp. 168-171, January 2008 [14] D. M. Rowe, Thermoelectrics Handbook: Micro to Nano, CRC, 2006 ©EDA Publishing/THERMINIC 2009 79 ISBN: 978-2-35500-010-2
7-9 October 2009, Leuven, Belgium Practical Realization of PTAT Sensor for ASIC Overheat Protection M. Szermer, M. Janicki, Z. Kulesza, A. Napieralski Department of Microelectronics and Computer Science, Technical University of Lodz Wolczanska 221/223, 90-924 Lodz, POLAND Tel. +48 42 631 2722 e-mail: szermer@dmcs.pl Abstract-This paper presents simulations and measurements of an integrated PTAT sensor. The sensor is equipped with an overheat protection circuit and was implemented in an ASIC containing matrices of heat sources and junction temperature sensors. The PTAT sensor is used for temperature monitoring and it is responsible for issuing warning signals in a case of chip overheat. Particular attention is paid to the discussion of sensor design and the presentation of simulated circuit operation. I. INTRODUCTION The constant increase of dissipated power density in the state-of-the-art integrated circuits quite often requires realtime chip temperature monitoring. The idea of temperature monitoring system is not new and it was already presented in [1]-[2]. One of the methods to realize such a monitoring system is to place temperature sensors inside circuit layout. Just simple p-n diodes could serve for this purpose. Another possible solution is to use dedicated temperature sensors, such as the Proportional To Absolute Temperature ones (PTATs). The main advantage of this sensor is that it has the linear dependence of output voltage on temperature. This allows high precision temperature measurements. Another advantage is that this sensor usually consists of a small number of transistors; hence the area occupied by the sensor is very small. Moreover, PTAT sensors can be designed using standard transistors available in a particular design technology, so no additional process steps are required. The PTAT sensors can be used as temperature warning elements only after minor modification of a circuit. This is a very desired feature in modern chips. The following section presents in detail the design of our sensor. Then, the simulated characteristics of the sensor are presented and compared with the measured ones. Finally separate section discusses the details of sensor layout design in the particular technology chosen for a practical ASIC realization. II. PTAT SENSOR DESIGN However the idea of PTAT sensor is well known but detailed description of it is written in this section [3]-[5]. First the conception of the PTAT sensor with other blocks is discussed. After this the PTAT sensor is described in more details. The description of it reveals the conception of the overheat protection circuit. The block schematic of designed temperature monitoring system, placed in the ASIC, is shown in Fig. 1. This system consists of a sensor, a comparator, a voltage divider and current mirrors. The mirrors provide the proper bias currents to the other circuits and are not described in the paper. One input of the comparator is connected to the constant voltage from the voltage divider. The second input is connected to the output voltage from the PTAT sensor. This allows triggering the warning signal by the comparator. In case of emergency, this output signal from the comparator is responsible for switching off the transistors delivering current to the bipolar transistor inside the sensor. This action is described in more detail in the following paragraph. The practical realization of this system, its simulations and measurements are discussed in the next two sections. The designed PTAT sensor consists of 9 MOS transistors, 3 bipolar transistors and 1 resistor (see Fig. 2). The MOS transistors create current mirrors which inject the desired current to the sensor. In order to explain properly the principle of sensor operation it is necessary to describe these current mirrors in more detail. This circuit consists of 7 MOS transistors. Transistors M0 and M1 are the circuit inputs to which current is delivered. Transistors M4 and M5 are used as outputs of the mirror. They deliver current to the bipolar transistor used in a sensor. From the operation point of view the pair of transistors M2 and M3 is very important. They constitute an additional output of the mirror. The transistor M6 is used as a switch which is responsible for turning on and off the additional current mirror output. The gate of this transistor is connected to the overheat warning signal. In absence of the warning, the current is flowing through the mirror and the voltage drop at the output is higher than in the case when the current is not flowing through the additional mirror (the warning signal high). Owing to this, the output voltage reaches its critical value at 150 °C and the warning signal is issued. The sensor was designed so that it has a hysteresis in the output characteristics. This means that the warning signal is cancelled when the temperature decreases below 130 °C. This phenomenon is clearly visible in Figs. 3-4. The desired output signal hysteresis size and the low power consumption of the sensor were attained owing to the proper dimensioning of the transistors. ©EDA Publishing/THERMINIC 2009 80 ISBN: 978-2-35500-010-2
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