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impact on the mechanical stress within and in between the
various compounds of the packaged die.
Figure 3 shows the resulting temperature map, with a
maximum temperature of 125 0 C in the right upper corner
and a maximum temperature gradient of 23 0 C
7-9 October 2009, Leuven, Belgium
Figure 5 shows the new temperature map as a result of the
simulation for the new floorplan.
Fig. 5. Temperature map of the die with the new floorplan.
Fig, 3. Temperature map of the die from the FE model temperature
simulations for the die glued in a BGA 40 x 40 mm package, including an
internal copper heat spreader and an external heat sink on top of the
package.
This gradient was considered as too high for the
application, particularly for the introduced mechanical stress.
Therefore the floorplan was changed in such a way that the
most intensive power consuming blocks were more evenly
distributed over the die, with the aim to reduce the gradient
to a level of 10 0 C max, set by the chip architect. The final
floorplan is shown in figure 4.
Although the maximum temperature of 1250C still
remains, the map clearly shows that the maximum
temperature variation over the die is limited to only 5.3
degrees, which is even less than required from the
application.
The following section shows that in a 45nm CMOS
technology, the temperature variation across the die has
much less influence on the performance than in conventional
technologies.
III. FROM TEMPERATURE TO PERFORMANCE
An increase in the operating temperature of a MOS
transistor affects its behaviour in two different ways:
1. The mobility of the majority carriers, e.g., electrons in
an nMOS transistor, in the channel decreases. Consequently,
since the transistor gain factor β□ = μ.C ox , also β□ decreases.
Its temperature dependence can be estimated with [4, 7]:
β□(Temp) = β□(298 K) x (298/Temp) 3/2 (1)
The exponent 3/2 in this expression is more applicable to
the electron mobility. For holes this exponent is closer to 1.
PMOS transistor currents are therefore less temperature
dependent than those of nMOS transistors.
2. The threshold voltage V T of both nMOS and pMOS
transistors decreases slightly. The magnitude of the influence
of temperature change on threshold voltage variation V T
depends on the substrate doping level. A variation of
-0.7mV/ 0 C is quite typical.
Both effects have different consequences for the speed of
an IC. This speed is determined by the delay τ of a logic
gate, which is defined as:
Fig. 4. Final floorplan and power distribution during full operation of all IP.
Cores.
τ = CV/I = 2CV/(β(V gs -V T ) 2 (2)
©EDA Publishing/THERMINIC 2009 33
ISBN: 978-2-35500-010-2