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7-9 October 2009, Leuven, Belgium C. Effect of copper vias In the IMEC approach (figure 8), a 3D-die stack is built by using through-silicon Cu vias (TSVs) and a polymer material to fill the gap between the dies [4, 7, 9]. Interconnections between dies are made using the vias (nails) which have electrical functionality but also a thermal advantage since the copper thermal conductivity is three orders of magnitude higher than the thermal conductivity of the polymer glue. Fig. 8. Right: schematic view of IMEC`s 3D-SIC chip stacking approach with hybrid Cu/dielectric bonding. In this figure and in the study reported, BCB has been assumed as the bonding dielectric. Left: SEM image of a TSV in a IMEC`s 3D stack. Fig. 6. Interaction of two hot spots located on the same level (die 3). (a) The graph reports the temperature measured in the center of hotspot 1, when the ratio (r) between the hotspots separation and their diameter is varied. (b) Temperature as a function of the distance from the hotspot 1 center, for different values of r. The meaning of the interaction distance can be better understood when looking at the flux plots in figure 7. For r = 7 the hot spots spreading angles - visualized through the heat flux lines - almost do not intercept. On the other hand, an interaction between the respective temperature fields start to be visible when the power sources are so closely spaced (r = 3) that their spreading angles overlap. Fig. 7. Heat flux emanating from two hot spots active in die 3, for two significant values of r. The presence of TSVs in the polymer layer alters its thermal properties: a decrease in thermal resistance of the polymer, and thus in the overall temperature, is expected in this case. It has been previously demonstrated [6] that, for the case of a homogeneous power dissipation in stacked dies, the presence of copper bumps in the polymer accounts for the major part of the reduction in the thermal resistance in a stack. This suggests the use of dummy Cu studs in the polymer as a thermal management aid. In order to quantify the impact of dummy copper on the stack temperature a series of FEM simulations have been performed. We have used a 2D axisymmetric model of a 2.5 x 2.5 mm 2 wide structure with 5 μm diameter Cu studs placed in the interface layer - BCB in this case (figure 9 a). A package resistance R1 = 1.3 K/W has been considered for all simulations. At first, a parametric study has been performed in which the polymer thickness has been varied while keeping the Cu studs pitch fixed. Figure 9b reports the results and demonstrates that the presence of Cu studs with a sufficiently small pitch affects significantly the thermal resistance of the polymer layer. The copper provides for an effective heat conduction path (fig. 10), and reduces considerably the overall stack temperature. The maximum temperature in a stack with dummy Cu studs is found to be almost independent on the polymer thicknesses when the studs pitch is small, thus the copper thermal impact is more significant for thicker BCB layers. A similar conclusion can be drawn from figure 9c, where the copper impact as a function of bumps pitch is explored for two different BCB thicknesses. ©EDA Publishing/THERMINIC 2009 59 ISBN: 978-2-35500-010-2
7-9 October 2009, Leuven, Belgium The maximum temperature reached on a given die in the stack and the extent to which the hotspot influences the surrounding plane is also influenced by the die thickness. Figure 11 reports the variation in the peak temperature in die 3 for a hot spot located in the same die. Fig. 11. Peak temperature variation in die 3 as a function of the die thickness. VI. CONCLUSIONS We have presented the thermal analysis of a typical 3-D stack solution for microelectronics circuits with localized heat sources (hot spots). The analysis aimed at quantifying the impact of various parameters on the hot spots thermal footprint on the temperature distribution in the stack. The interaction between hot spots located on the same die level has also been analyzed. The potential thermal impact of the presence of dummy Cu in the dielectric glue has been demonstrated. Fig. 9. (a) Model used to study the thermal impact of Cu studs in BCB. (b) Peak temperature in the top die (die 3) as a function of polymer thickness. P is the studs pitch. (c) Peak temperature in the top die as a function of the studs pitch for two different polymer thicknesses. REFERENCES [1] M. Rencz, “Thermal issues in stacked die packages,” 21 st IEEE SEMI-THERM Symposium, pp. 307-312, March 2005. [2] S. Pinel et al, “Thermal modeling and management in ultrathin chip stack technology,” IEEE Trans. On Components and Packaging Technologies, vol. 25, Issue 2, pp. 244-253, June 2002. [3] S. Im and K. Banerjee, “Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs,” IEDM Tech. Dig., pp. 727-730, December 2000. [4] E. Beyne, “The rise of the 3 rd dimension for system integration,” Proc. IEEE Int. Interconnect Technology Conference, pp. 1-5, 2006. [5] The International Technology Roadmap for Semiconductors (ITRS), ed. 2008. Available for free downloading, url: http://www.itrs.net/Links/2008ITRS/Home2008.htm. [6] Msc. MARC, commercially available software, url: http://www.mscsoftware.com. [7] L. C. Chen, B. Vandevelde, B. Swinnen, E. Beyne, “Enabling SPICE-Type modeling of the thermal properties of 3D-stacked ICs,” Electronics Packaging Technology Conference, pp. 492-499, December 2006. [8] V. Palankovski, S. Selberherr, “Thermal models for semiconductor device simulation,” High Temperature Electronics, pp. 25-28, July 1999. [9] B. Swinnen et al, “3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias,” Int. Electron Devices Meeting, pp. 1-4, December 2006. Fig. 10. Structure with Cu studs built in a 3 μm thick BCB with a pitch of 15 μm. Top: Model of the structure. Bottom: temperature distribution. ©EDA Publishing/THERMINIC 2009 60 ISBN: 978-2-35500-010-2
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