Online proceedings - EDA Publishing Association

7-9 October 2009, Leuven, Belgium
Electro-Thermal Modeling of Nano-Scale Devices
D. Vasileska 1 , K. Raleva 2 and S. M. Goodnick 1
1 Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287-5706, USA
2 Faculty of Electrical Engineering and Information Technology, University Sts. Cyril and Methodius, Skopje, Republic of
Macedonia
Abstract-In this paper we present simulation results obtained with
our electro-thermal device simulator when modeling different
technology generations of FD-SOI devices. In particular, we stress
out the importance of the temperature boundary conditions for
digital and analog circuits and the use of the full model which
takes into account both temperature and thickness dependence
(which is particularly important for thin silicon films) of the
thermal conductivity.
Key-words: electro-thermal modeling, FDSOI devices,
particle-based device simulations
I. INTRODUCTION
The scaling of semiconductor devices into the nanometer
regime and the problems associated with further
miniaturization of device technologies has resulted into
investigation of devices with alternative materials and
alternative device designs such as fully-depleted (FD), dualgate
(DG), tri-gate silicon-on-insulator (SOI) and other device
designs. The problem with SOI devices is that they exhibit selfheating
effects. These self-heating effects arise from the fact
that the underlying SiO 2 layer has about 100 times smaller
thermal conductivity than bulk Si (1.4 W/m/K). Also, the
thickness of the silicon film in nanoscale devices is much
smaller than the phonon mean free path which is on the order
of 300 nm in bulk silicon. Therefore, boundary scattering
becomes dominant scattering mechanism, thus reducing the
thermal conductivity value to a fraction of its bulk value. For
example, the bulk thermal conductivity in silicon is 148
W/m/K and the thermal conductivity of a silicon film of
thickness of 10 nm is 13 W/m/K (a factor of 10 smaller than
the bulk value). Also, in thin silicon films the thermal
conductivity has smaller temperature dependence because
boundary scattering is temperature independent scattering
process.
II. THE ROLE OF THE TEMPERATURE BOUNDARY
CONDITIONS
In analog devices neighboring devices are typically on and if
the gate contacts are also biased then there is no heat flow
through the gate contact and the side boundaries. In these cases
it is appropriate to use Neumann boundary conditions on the
side (artificial) boundaries and Neumann boundary conditions
on the gate electrode. Simulation results for the current
degradation for different technology of FD SOI devices,
summarized in Table 1, are presented in Figure 1.
In the case of digital circuits, the devices are rarely on and
the use of Dirichlet boundary conditions at the gate and the side
boundaries are the appropriate boundary conditions. This
corresponds to the best-case scenario of heat removal from the
device active region. Simulation results for the current
degradation for different technology devices when Dirichlet
boundary conditions are applied to the gate and the side
boundaries, are shown in Figure 2.
Table 1. Parameters for various simulated device technology nodes (constant
field scaling) [1].
L
(nm)
tox
(nm)
t Si
(nm)
t box
(nm)
N ch
(cm -3 )
V GS=V DS
(V)
I D
(mA/um)
25 2 10 50 1×10 18 1.2 1.82
45 2 18 60 1×10 18 1.2 1.41
60 2 24 80 1×10 18 1.2 1.14
80 2 32 100 1×10 17 1.5 1.78
90 2 36 120 1×10 17 1.5 1.67
100 2 40 140 1×10 17 1.5 1.57
120 3 48 160 1×10 17 1.8 1.37
140 3 56 180 1×10 17 1.8 1.23
180 3 72 200 1×10 17 1.8 1.03
L- Gate Length; tox- Gate Oxide Thickness;
t Si- Active Si Layer Thickness;
t box- BOX Thickness;
N ch- Channel Doping Concentration;
I D- Isothermal current value (300K).
Degradation (%)
100
75
50
25
300K
400K
600K
Neumann
0
50 100 150
Gate Length (nm)
Figure 1. Current degradation vs. technology generation ranging from 25 nm to
180 nm channel length FD SOI devices (Table 1). Isothermal boundary
condition of 300K is set on the bottom of the BOX. Parameter is the
temperature on the gate electrode. Neumann boundary conditions are applied at
the vertical sides.
Degradation (%)
100
80
60
40
20
300K
Neumann
0
50 100 150
Gate Length (nm)
Figure 2. Current degradation for the case of Dirichlet boundary conditions at
the artificial boundaries. In one case Dirichlet boundary conditions are applied
at the gate electrode with T Gate=300 K and in the second case Neumann
boundary conditions are applied at the gate electrode.
©EDA Publishing/THERMINIC 2009 195
ISBN: 978-2-35500-010-2