Online proceedings - EDA Publishing Association
Online proceedings - EDA Publishing Association
Online proceedings - EDA Publishing Association
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
7-9 October 2009, Leuven, Belgium<br />
Devices fabricated on wafers with TSV interconnecting<br />
elements are exposed to additional mechanical stress related to<br />
the IC layout and wafer shape (Fig. 1). This paper discusses<br />
various cases of stress distribution based on simulation results<br />
performed by Coventor [5] and TCAD [6] packages.<br />
A<br />
Fig. 3. Mechanical design drawing (3D model), without and with<br />
encapsulation [7].<br />
Even if all standalone (non 3D) modules have been correctly<br />
designed, simulated and would perfectly operate if assembled<br />
as standalone devices, if the device profits from 3D integration<br />
technique its functionality may be affected by various side<br />
effects not taken into consideration during design. Such a<br />
device not optimized for 3D integration during design process<br />
– may fail. 3D integrated device comprises various modules.<br />
Fig. 2. a) V T(P) - Threshold Voltage (V T) on Stress Tensor (P) sensitivity for<br />
various Stress Tensor-Channel Angle (α). NMOS; L=130[nm]; Shallow S/D;<br />
UDS=0.05[V] b) Threshold voltage variation for 350nm technology for<br />
various mechanical stress levels and various angles between mechanical<br />
force and source-drain direction<br />
It is especially important for analogue blocks and low noise<br />
amplifiers. Electrical simulations performed in TCAD show<br />
that digital blocks are more resistant to the mechanical stress<br />
then analogue ones. Sample simulations performed in TCAD<br />
for MNOS and PMOS transistors show that mechanical stress<br />
relative sensitivity of complementary MOS devices is<br />
complementary as presented on Fig. 2b. Selected results of<br />
TCAD simulations performed for simple digital blocks like<br />
inverters and NAND digital gates also have been performed.<br />
Simulated gates have been modeled for AMS 350nm<br />
technology. Simulation results confirm that for moderate levels<br />
of mechanical stress (mechanical stress level should not exceed<br />
the level of 500MPa) parasitic stress does not significantly<br />
affect transfer function of digital circuits.<br />
Modeling and simulation results of the integrated, intelligent<br />
health monitoring system 3D model [7] have been presented.<br />
Such a system is the e-Cubes project demonstrator sample.<br />
General idea is shown on the Fig. 3. Significant speedup and<br />
improvements of product development stages will be the profit<br />
of the project. From the reliability point of view thermomechanical<br />
behavior of the whole system is the most important<br />
parameter to be taken into consideration.<br />
B<br />
Fig. 4. 3D model of the e-Cubes demonstrator for health monitoring<br />
designed in CoventorWare with the mesh ready for multidomain modeling<br />
and simulation by FE methods.<br />
Each of them affects neighboring modules in thermal,<br />
mechanical, electrical, electromagnetic way. Probability that a<br />
single module affects another in its neighborhood (e.g. by high<br />
temperature transfer) is quite high. Therefore the module<br />
arrangement and its complex multidomain simulation are so<br />
important on each design stage.<br />
For this simulation 3D model designed in CoventorWare have<br />
been used (Fig. 4). 3D integration technique has been<br />
simulated along with applied, real thermo-mechanical<br />
boundary conditions like power dissipation present in different<br />
modules. Also selected mechanical issues regarding the<br />
encapsulation methodology have been done. Thermal<br />
simulations results show that under assumed boundary<br />
conditions temperature does not increase too much across the<br />
whole demonstrator device structure Sample results of the<br />
thermal investigation are shown on the Fig. 5.<br />
The aim of this part of the simulation was verification of the<br />
temperature distribution under high and low power operating<br />
modes. 300 K ambient temperature has been assumed as one of<br />
boundary conditions applied for this simulation as well as<br />
convection and radiation on the bottom and upper surfaces. For<br />
applied boundary conditions in the worst case temperature<br />
increases to 325 K for high power mode and 310 K for low<br />
power mode.<br />
Apart from the thermal phenomena mechanical properties of<br />
the device and used materials are important from reliability<br />
point of view, especially under higher range device<br />
temperatures. The main goal of performed simulation was to<br />
©<strong>EDA</strong> <strong>Publishing</strong>/THERMINIC 2009 85<br />
ISBN: 978-2-35500-010-2