Online proceedings - EDA Publishing Association

7-9 October 2009, Leuven, Belgium
using a compact model of the total physical structure of a
packaged die, including heat spreader.
II. FROM POWER DISTRIBUTION TO TEMPERATURE
DISTRIBUTION
Even when the power distribution across an SoC is
accurately known, the temperature distribution can still be
very different, depending on the thermal behaviour of the
package and the thermal design of the application. This
requires a reasonably accurate model that includes the
thermal properties of the chip, the bonds, the package and
the system. One way to achieve this is to use Compact
Thermal Models (CTM), simple board simulation tools like
COMIC and a Finite Elements (FE) program [1]. CTM’s are
widely used for predicting the maximum junction
temperatures. However, temperature gradients do not belong
to its predicting capability. In order to get to know the
temperature gradient across the die, first a CTM must be
derived. Next the CTM will be used in combination with
COMIC to predict the thermal behaviour of the product in a
simplified application. One of the calculation results is the
effective Heat Transfer Coefficient (HTC) which is working
on the ‘thermal’ contacts of the package with the application
PCB. Next, these HTC’s will be used as thermal boundary
conditions in the FE program. Since the FE model of the
package contains a detailed description of the floorplan of
the IC an accurate prediction of the temperature can be
achieved.
The chip used for case study
Many thermal simulations on integrated circuits are
performed on complex and high-speed processors,
consuming between 50W to a 100W [2, 3]. In [2], the total
temperature variation across the chip at a maximum power
consumption of P total =32.3W is: ΔT=31.3 0 C, with a
minimum temperature of T min =106.1 0 C and a maximum of
T max =137.4 0 C. This minimum and maximum temperature
values, as well as the chip locations where these occur, are
very much dependent on the floorplan of the chip and of the
applied package.
For our research, we use an advanced video and graphics
processor chip used in very advanced digital TV sets. Figure
1 shows the power distribution, based on the physical
position of the processor, controller, memory and interface
cores, when all cores are operating at maximum
performance.
low-performance interfaces
low-performance interfaces
U3
0.8W
U4
0.515W
U2
0.294W 2.94W
U8
0.83W
DDR interface
U1
1.11W
U5
0.21W U6
0.26W
low-performance interfaces
U7
2.02W
Fig. 1. Original floorplan and power distribution during full operation of all
IP cores.
The die would be mounted into a HBGA 40 x 40 mm
package, including a copper drop-in heat spreader. Figure 2
shows a cross section of the total physical structure that has
been included in the model for simulations.
Fig. 2. Physical structure that has been included in the model for
simulations.
DDR interface
Low-Performance
interfaces
Next, the above floorplan, together with the power
numbers were also fed into the finite elements model and
simulated. The goal of the simulations is twofold. First it is
important to predict the overall temperature distribution
across the die and check whether, at some local spot, it
would exceed the maximum specified temperature of 125 0 C.
Second, a large temperature variation may have severe
©EDA Publishing/THERMINIC 2009 32
ISBN: 978-2-35500-010-2