Online proceedings - EDA Publishing Association
Online proceedings - EDA Publishing Association
Online proceedings - EDA Publishing Association
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VI. NOMENCLATURE<br />
A nm unit cell area [m 2 ]<br />
c p specific heat capacity [J/(kg*K)]<br />
g coefficient [L/min/cm 2 ]<br />
h eff effective heat transfer coeff. [W/(m 2 *K)]<br />
h nm unit cell heat transfer coefficient [W/(m 2 *K)]<br />
HT heat transfer<br />
k coefficient [-]<br />
k v coefficient of flow [L/min]<br />
n number of cold plates [-]<br />
P cp cold plate pumping power [W]<br />
P system total system pumping power [W]<br />
total electrical processor power [W]<br />
P el<br />
Δp loop<br />
Δp cp<br />
Δp system<br />
dp/dx<br />
Q <br />
rack cooling loop pressure drop [bar]<br />
cold plate pressure drop [bar]<br />
system pressure drop = Δploop + Δpcp [bar]<br />
pressure gradient [Pa/m]<br />
heat flow [W]<br />
q<br />
nm<br />
unit cell heat flux [W/cm 2 ]<br />
R fluid fluid resistance [kg/(s*m 4 )]<br />
R conv convective thermal resistance [K*mm 2 /W]<br />
R TIM thermal interface resistance [K*mm 2 /W]<br />
T jmax maximal junction temperature [°C]<br />
T fout fluid outlet temperature [K]<br />
fluid inlet temperature [K]<br />
T fin<br />
ΔT fout-in<br />
ΔT j<br />
t nm<br />
t Si<br />
t TIM<br />
V <br />
fluid temp. difference from outlet to inlet [K]<br />
T jmax - T jmin [K]<br />
unit cell cavity height [mm]<br />
silicon die thickness [mm]<br />
bond-line thickness [mm]<br />
cold plate volumetric flow rate [L/min]<br />
V nm<br />
unit cell volumetric flow rate [L/min]<br />
V system<br />
rack cooling loop vol. flow rate [L/min]<br />
7-9 October 2009, Leuven, Belgium<br />
Greek letters<br />
ρ density of water [kg/m 3 ]<br />
constants<br />
h 0<br />
p 0<br />
reference heat transfer coefficient = 1 W/(m 2 *K)<br />
reference pressure = 1bar<br />
subscript/superscript<br />
cp cold plate<br />
el electrical<br />
eff effective<br />
j junction<br />
fout-in fluid outlet minus inlet<br />
fin fluid inlet<br />
fout fluid outlet<br />
loop server rack cooling loop<br />
max maximal<br />
m cell number in y-direction<br />
n cell number in x-direction<br />
ACKNOWLEDGMENT<br />
We acknowledge Reto Wälchli, Urs Kloter, and Martin<br />
Witzig for their technical contributions and John Magerlein<br />
and Walter Riess for their continuous support.<br />
REFERENCES<br />
[1] J. Koomey, “Estimating Total Power Consumption by<br />
Servers in the U.S. and the World”, A report by the Lawrence<br />
Berkeley National Laboratory, February 2007, see http://<br />
enterprise.amd.com/Downloads/svrpwrusecompletefinal.pdf.<br />
[2] E. Colgan et al., “A Practical Implementation of Silicon<br />
Microchannel Coolers for High Power Chips”, IEEE<br />
Transactions on Components and Packaging Technologies, Vol.<br />
30 No. 2., June 2007, pp. 218-225.<br />
[3] T. Brunschwiler et al., “Towards Zero Emission Datacenters”,<br />
IBM J. RES. & DEV., vol. 53 NO. 3 PAPER 11, 2009, see<br />
http://www.research.ibm.com/journal/rd/533/brunschwiler.pdf<br />
[4] H. Hamann et al., “Spatially-Resolved Imaging of<br />
Microprocessor Power (SIMP): Hotspots in Microprocessors”,<br />
Proc. 10th Intersociety Conf. on Thermal and Thermomechanical<br />
Phenomena in Electronics Systems ITHERM 06, 30<br />
May – 2 June, 2006, pp. 121-125.<br />
©<strong>EDA</strong> <strong>Publishing</strong>/THERMINIC 2009 155<br />
ISBN: 978-2-35500-010-2