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3.9 (Deductive Fault Simulation) The controlling value of a NOR gate is one, and the inversion value is also one. Let S be the set of inputs that hold the controlling value, and I be the set of all inputs, i.e., I = {A, B, C}. When all inputs hold the non-controlling value (ABC = 000), we have L D = ⎛ ⎜ ⎞ ∪ L ⎝ j ⎟ ∪ D/ c ⊕ i j ∈I ⎠ { ( )} = ( L A ∪ L B ∪ L C )∪{ D/0} When at least one input holds the controlling value, we have ⎛ ⎛ L D = ⎜ ⎞ ⎛ ⎞ ⎞ ⎜ ∩ L ⎝ j ⎟ −⎜ ∪ L j ∈S ⎠ j ⎟ ⎟ ∪ ⎝ ⎝ j ∈( I −S { D/1} ) ⎠ ⎠ For example, if ABC = 110, L D will be L D = ( L A ∩ L B )− L C )∪{ D/1} VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 12/15
3.10 (Deductive Fault Simulation) For the purpose of demonstration, we do not perform fault collapsing here. The noncollapsed fault list is {a/0, a/1, b/0, b/1, D/0, D/1, H/0, H/1, E/0, E/1, F/0, F/1, c/0, c/1}. VLSI Test Principles and Architectures Ch. 3 – Logic & Fault Simulation – P. 13/15
Page 1 and 2: Chapter 3 Exercise Solutions 3.1 (P
Page 3 and 4: (c) Tri-state buffer Let A be the i
Page 5 and 6: (c) Min-Max Delays VLSI Test Princi
Page 7 and 8: 3.4 (Event-Driven Simulation) Time
Page 9 and 10: 3.6 (Hazard Detection) Use 8-valued
Page 11: 3.8 (Parallel Fault Simulation) PFS
Page 15: 3.12 (Critical Path Tracing) VLSI T

34~chapter 03 lfsim.pdf

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