PIC18F97J60 Family Device Data Sheet - CNMAT
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PIC18F97J60 Family Device Data Sheet - CNMAT

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<strong>PIC18F97J60</strong> FAMILY<br />

TABLE 1-6:<br />

Pin Name<br />

RD0/AD0/PSP0<br />

RD0<br />

AD0<br />

PSP0<br />

RD1/AD1/PSP1<br />

RD1<br />

AD1<br />

PSP1<br />

RD2/AD2/PSP2<br />

RD2<br />

AD2<br />

PSP2<br />

RD3/AD3/PSP3<br />

RD3<br />

AD3<br />

PSP3<br />

RD4/AD4/PSP4/SDO2<br />

RD4<br />

AD4<br />

PSP4<br />

SDO2<br />

RD5/AD5/PSP5/<br />

SDI2/SDA2<br />

RD5<br />

AD5<br />

PSP5<br />

SDI2<br />

SDA2<br />

RD6/AD6/PSP6/<br />

SCK2/SCL2<br />

RD6<br />

AD6<br />

PSP6<br />

SCK2<br />

SCL2<br />

RD7/AD7/PSP7/SS2<br />

RD7<br />

AD7<br />

PSP7<br />

SS2<br />

PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)<br />

Pin Number<br />

TQFP<br />

92<br />

91<br />

90<br />

89<br />

88<br />

87<br />

84<br />

83<br />

Pin<br />

Type<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

O<br />

I/O<br />

I/O<br />

I/O<br />

I<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I/O<br />

I<br />

Buffer<br />

Type<br />

ST<br />

TTL<br />

TTL<br />

ST<br />

TTL<br />

TTL<br />

ST<br />

TTL<br />

TTL<br />

ST<br />

TTL<br />

TTL<br />

ST<br />

TTL<br />

TTL<br />

—<br />

ST<br />

TTL<br />

TTL<br />

ST<br />

ST<br />

ST<br />

TTL<br />

TTL<br />

ST<br />

ST<br />

ST<br />

TTL<br />

TTL<br />

TTL<br />

Description<br />

PORTD is a bidirectional I/O port.<br />

Digital I/O.<br />

External memory address/data 0.<br />

Parallel Slave Port data.<br />

Digital I/O.<br />

External memory address/data 1.<br />

Parallel Slave Port data.<br />

Digital I/O.<br />

External memory address/data 2.<br />

Parallel Slave Port data.<br />

Digital I/O.<br />

External memory address/data 3.<br />

Parallel Slave Port data.<br />

Digital I/O.<br />

External memory address/data 4.<br />

Parallel Slave Port data.<br />

SPI data out.<br />

Digital I/O.<br />

External memory address/data 5.<br />

Parallel Slave Port data.<br />

SPI data in.<br />

I 2 C data I/O.<br />

Digital I/O.<br />

External memory address/data 6.<br />

Parallel Slave Port data.<br />

Synchronous serial clock input/output for SPI mode.<br />

Synchronous serial clock input/output for I 2 C mode.<br />

Digital I/O.<br />

External memory address/data 7.<br />

Parallel Slave Port data.<br />

SPI slave select input.<br />

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output<br />

ST = Schmitt Trigger input with CMOS levels Analog = Analog input<br />

I = Input O = Output<br />

P = Power OD = Open-Drain (no P diode to VDD)<br />

Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).<br />

2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).<br />

3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).<br />

4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).<br />

5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).<br />

DS39762D-page 34 Preliminary © 2008 Microchip Technology Inc.

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