PIC18F97J60 Family Device Data Sheet - CNMAT
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PIC18F97J60 Family Device Data Sheet - CNMAT

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<strong>PIC18F97J60</strong> FAMILY<br />

Pin Diagrams (Continued)<br />

80-Pin TQFP<br />

RH1<br />

RH0<br />

RE2/P2B<br />

RE3/P3C (2)<br />

RE4/P3B (2)<br />

RE5/P1C (2)<br />

RE6/P1B (2)<br />

RE7/ECCP2 (1) /P2A (1)<br />

RD0<br />

VDD<br />

VSS<br />

RD1<br />

RD2<br />

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61<br />

RH2<br />

RH3<br />

RE1/P2C<br />

RE0/P2D<br />

RB0/INT0/FLT0<br />

RB1/INT1<br />

RB2/INT2<br />

RB3/INT3<br />

MCLR<br />

RG4/CCP5/P1D<br />

VSS<br />

VDDCORE/VCAP<br />

RF7/SS1<br />

RF6/AN11<br />

RF5/AN10/CVREF<br />

RF4/AN9<br />

RF3/AN8<br />

RF2/AN7/C1OUT<br />

RH7/AN15/P1B (2)<br />

RH6/AN14/P1C (2)<br />

1<br />

2<br />

3<br />

4<br />

5<br />

6<br />

7<br />

8<br />

9<br />

10<br />

11<br />

12<br />

13<br />

14<br />

15<br />

16<br />

17<br />

18<br />

19<br />

20<br />

PIC18F86J60<br />

PIC18F86J65<br />

PIC18F87J60<br />

60<br />

59<br />

58<br />

57<br />

56<br />

55<br />

54<br />

53<br />

52<br />

51<br />

50<br />

49<br />

48<br />

47<br />

46<br />

45<br />

44<br />

43<br />

42<br />

41<br />

VDDRX<br />

TPIN+<br />

TPIN-<br />

VSSRX<br />

RG0/ECCP3/P3A<br />

RG1/TX2/CK2<br />

RB4/KBI0<br />

RB5/KBI1<br />

RB6/KBI2/PGC<br />

VSS<br />

OSC2/CLKO<br />

OSC1/CLKI<br />

VDD<br />

RB7/KBI3/PGD<br />

RC5/SDO1<br />

RC4/SDI1/SDA1<br />

RC3/SCK1/SCL1<br />

RC2/ECCP1/P1A<br />

RG2/RX2/DT2<br />

RG3/CCP4/P3D<br />

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40<br />

RH5/AN13/P3B (2)<br />

RH4/AN12/P3C (2)<br />

RF1/AN6/C2OUT<br />

ENVREG<br />

AVDD<br />

AVSS<br />

RA3/AN3/VREF+<br />

RA2/AN2/VREF-<br />

RA1/LEDB/AN1<br />

RA0/LEDA/AN0<br />

VSS<br />

VDD<br />

RA5/AN4<br />

RA4/T0CKI<br />

RC1/T1OSI/ECCP2 (1) /P2A (1)<br />

RC0/T1OSO/T13CKI<br />

RC6/TX1/CK1<br />

RC7/RX1/DT1<br />

RJ4<br />

RJ5<br />

VSSPLL<br />

VDDPLL<br />

RBIAS<br />

VSSTX<br />

TPOUT+<br />

TPOUT-<br />

VDDTX<br />

Note 1: The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting.<br />

2: P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting.<br />

DS39762D-page 4 Preliminary © 2008 Microchip Technology Inc.

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