PIC18F97J60 Family Device Data Sheet - CNMAT

PIC18F97J60 FAMILY
TABLE 1-6:
Pin Name
PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
NC 9 — — No connect.
VSS 15, 36, 40, P — Ground reference for logic and I/O pins.
60, 65, 85
VDD 17, 37, 59, P — Positive supply for peripheral digital logic and I/O pins.
62, 86
AVSS 31 P — Ground reference for analog modules.
AVDD 30 P — Positive supply for analog modules.
ENVREG 29 I ST Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
16
P
P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
VSSPLL 82 P — Ground reference for Ethernet PHY PLL.
VDDPLL 81 P — Positive 3.3V supply for Ethernet PHY PLL.
VSSTX 79 P — Ground reference for Ethernet PHY transmit subsystem.
VDDTX 76 P — Positive 3.3V supply for Ethernet PHY transmit subsystem.
VSSRX 72 P — Ground reference for Ethernet PHY receive subsystem.
VDDRX 75 P — Positive 3.3V supply for Ethernet PHY receive subsystem.
RBIAS 80 I Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor;
see Section 18.0 “Ethernet Module” for specification.
TPOUT+ 78 O — Ethernet differential signal output.
TPOUT- 77 O — Ethernet differential signal output.
TPIN+ 74 I Analog Ethernet differential signal input.
TPIN- 73 I Analog Ethernet differential signal input.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
DS39762D-page 40 Preliminary © 2008 Microchip Technology Inc.