Boolean Satisfiability (SAT) Algorithms

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Intel’s Reaction This report stirred up a huge controversy. Intel at first denied that the problem existed. Later, Intel claimed that it was not serious and would not affect most users. • However, people who could prove that they were affected would get their processor replaced by Intel However, although most independent estimates found the bug to be of little importance and have negligible effect on most users, it has caused a great public outcry. • Companies like IBM (whose "586" microprocessor competed at that time with the Intel Pentium line) joined the condemnation. Finally, Intel was forced to offer to replace all flawed Pentium processors, at huge potential cost to the company • However, it turned out that only a small fraction of Pentium owners actually bothered to get their chips replaced • Intel's stock price actually rose the day they finally acknowledged http://en.wikipedia.org/wiki/Pentium_FDIV_bug Boolean SAT Algorithms / FLOLAC 2009 Prof. Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw 14
Aftermath... Intel hired 1000+ PhDs for strategic CAD research, especially in the design verification area However, there were still several bugs found in later Pentium chips • e.g. CMPXCHG8B instruction, Dan-0411, Pentium FO bugs, etc Where’s the problem Why is it so difficult Let’s first review a little bit about the typical design process… Boolean SAT Algorithms / FLOLAC 2009 Prof. Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw 15
Page 1 and 2: Boolean Satisfiability (SAT) Algori
Page 3 and 4: What is Verification What’s the p
Page 5 and 6: #Transistors in Intel’s CPUs Year
Page 7 and 8: What is Verification What’s the p
Page 9 and 10: And of course, don’t forget the i
Page 11 and 12: Improvement on Floating-Point Execu
Page 13: A 3-D plot of the ratio 4195835/314
Page 17 and 18: How do you verify your design Bool
Page 19 and 20: Simulation-Based Verification Testb
Page 21 and 22: Like Finding a Bug in an Ocean… B
Page 23 and 24: Then why is simulation still the ma
Page 25 and 26: And of course, simulation approach
Page 27 and 28: Using hardware to speed up simulati
Page 29 and 30: Verification vs. Testing Objective
Page 31 and 32: Observability Problem --- Solved In
Page 33 and 34: The Fact More than 90% of properti
Page 35 and 36: ABV Example --- OVL module assert_n
Page 37 and 38: Any Problem Whose Problem “My big
Page 39 and 40: Think --- If you simulate your desi
Page 41 and 42: Simulation and Assertion-Based Veri
Page 43 and 44: Formal Verification Technologies De
Page 45 and 46: Proving “assert_always(p)” In
Page 47 and 48: Set of Reachable States t0 t1 t2 t3
Page 49 and 50: Combinational Invariance It is wor
Page 51 and 52: In this topic, we will use SAT engi
Page 53 and 54: Boolean Satisfiability (SAT) Fundam
Page 55 and 56: Complexity of SAT solver We have le
Page 57 and 58: Something like --- A Decision Tree
Page 59 and 60: Boolean Satisfiability Checking for
Page 61 and 62: A Typical Combinational SAT Algorit
Page 63 and 64: A Typical Combinational SAT Algorit
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a b c d combSat (g7, 0) 1 g1 g2 g3
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a b c d combSat (d, 1) 1 1 g1 g2 g3
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a b c d combSat (d, 1) 1 1 g1 g2 g3
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How many decisions did we make Ther
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Logic Implications Also called “
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How to schedule and evaluate these
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Trying to avoid fruitless implicati
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What’s the improvement Worse case
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Sounds good for all-1’s forward i
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2-Watched-Literal Algorithm H. Zhan
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2-Watched-Literal Algorithm Example
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Caching Effect: Reducing from O(n)
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Difference between circuit and CNF
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Any problem Remember there is only
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A Closer Look 0 1 1 0 0 0 11 1 11 1
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Direct Implication 1. Single source
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Direct vs. Indirect Implications 0
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Watch Scheme for XOR Gate n-input
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Applications of Logic Implication W
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Redundancy in a Combinational Circu
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Mandatory Assignment Example (1) Fa
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1. How do we know a wire in a combi
Page 109 and 110:
How to add an extra wire to make th
Page 111 and 112:
RAMBO: Redundancy Addition and remo
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Is (g5 g9) redundant c 0 b 0 g1 1
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Filtering Out Impossible Candidate
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How do we add “something” to a
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A Two-Way Redundancy Addition and R
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RAR Example (w t : g6 g7) c g4 0 0
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2-Way RAR Algorithm 1. Given a targ
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Creating a Redundant Gate (2) g s1
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A closer look at the previous examp
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Single Wire Replacement Theorem in
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A closer look... MA(w t ) a MA(g d
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SRAR-Wire vs. Original RAMBO (FYI)
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Single Gate Replacement in SatRAR *
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Alternative Sub-circuit by SatRAR M
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CNF-Based SAT Algorithm 1. Davis, P
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Davis Putnam Algorithm M .Davis, H.
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Basic DLL Procedure - DFS (a’ + b
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Page 147 and 148:
Page 149 and 150:
Page 151 and 152:
Potentially exponential complexity!
Page 153 and 154:
Conflict-Driven Learning (a’ + b
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Non-Chronological Backtracking (a
Page 157 and 158:
Deduced Implication from Learned Cl
Page 159 and 160:
Deduced Implication from Learned Cl
Page 161 and 162:
A Closer Look at the Implication Gr
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Conflict Analysis 2 a = 1 a = 1 a1
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Which constraint is the best to add
Page 167 and 168:
Conflict-Driven Learning Decision l
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A closer look at binary decision tr
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Conflict-Driven Non-Chronological B
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What we have learned on SAT... 1. E
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Static Decision Ordering Decision
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zChaff’s Variable State Independe
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More decision heuristics... Variabl
Page 181 and 182:
Remember when we talked about confl
Page 183 and 184:
Various Learning Techniques Other
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Learned by Signal Correlations A p
Page 187 and 188:
Conflict vs. Success-Driven Learnin
Page 189 and 190:
Success-Driven Learning Ref: Shuo,
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What can we do to make the learning
Page 193 and 194:
Recalled, the SAT algorithms we hav
Page 195 and 196:
SAT-Based Verification We know tha
Page 197 and 198:
However, in the above approach, we
Page 199 and 200:
Bounded Model Checking (BMC) Algori
Page 201 and 202:
Application of BMC If the property
Page 203 and 204:
K-induction Induction: SSS2000 •
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Induction SAT for (k = 0 to infinit
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Does “Induction SAT” guarantee
Page 209 and 210:
Induction over simple paths Let sim
Page 211 and 212:
Is the recurrence diameter the same
Page 213 and 214:
Outline Overview of Hardware Verif
Page 215 and 216:
Symbolic model checking without BDD
Page 217 and 218:
Limitation of Formal Engine Still
Page 219 and 220:
Localization abstraction Property:
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Image and over-approximated image
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Remember: Resolution a ∨ b ∨ ¬
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Generating refutations Refutation
Page 227 and 228:
Extraction of Unsatisfiability Core
Page 229 and 230:
Some Definitions for Unsatisfiabili
Page 231 and 232:
Interpolants from Proofs Deriving
Page 233 and 234:
SAT to compute set of reachable sta
Page 235 and 236:
Overapproximation An overapproxima
Page 237 and 238:
Adequate image Img(P,C) P Img’(P,
Page 239 and 240:
Huh A A' B P C C C C C C C F A ⇒
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Reachability algorithm let k = 0 re
Page 243 and 244:
Interpolation-based MC Fully SAT-ba
Page 245 and 246:
Conclusion on Boolean SAT Algorithm
Page 247 and 248:
Some popular SAT engines SATO •
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Boolean Satisfiability (SAT) Algorithms

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