Boolean Satisfiability (SAT) Algorithms

More documents

Recommendations

Info

Conflict-Driven Non-Chronological Backtracking --- Algorithm 1. When conflict occurs, check if the conflict level == 0 (implication level for the SAT target) a) If yes, return unsatisfiability (Why) b) Else, continue to 2 2. Find the 1st-UIP cut as the conflict causes 3. Backtrack to the max decision level of the nodes other than UIP in the cut 4. The UIP gate will be implied with the opposite value 5. Perform the new implication 6. If conflict, go to 1, else continue for the next decision Boolean SAT Algorithms / FLOLAC 2009 Prof. Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw 168
A closer look at binary decision tree In general, is non-chronological backtracking safe • May lead to SAT solution ealier • But some portion of the decision tree may not be covered • Not a complete search anymore • May also miss some bugs Difficult to record which branches haven’t been searched 1 d c 0 0 0 1 X 1 b a 1 d 1 0 Boolean SAT Algorithms / FLOLAC 2009 Prof. Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw 169
Page 1 and 2:
Boolean Satisfiability (SAT) Algori
Page 3 and 4:
What is Verification What’s the p
Page 5 and 6:
#Transistors in Intel’s CPUs Year
Page 7 and 8:
What is Verification What’s the p
Page 9 and 10:
And of course, don’t forget the i
Page 11 and 12:
Improvement on Floating-Point Execu
Page 13 and 14:
A 3-D plot of the ratio 4195835/314
Page 15 and 16:
Aftermath... Intel hired 1000+ PhD
Page 17 and 18:
How do you verify your design Bool
Page 19 and 20:
Simulation-Based Verification Testb
Page 21 and 22:
Like Finding a Bug in an Ocean… B
Page 23 and 24:
Then why is simulation still the ma
Page 25 and 26:
And of course, simulation approach
Page 27 and 28:
Using hardware to speed up simulati
Page 29 and 30:
Verification vs. Testing Objective
Page 31 and 32:
Observability Problem --- Solved In
Page 33 and 34:
The Fact More than 90% of properti
Page 35 and 36:
ABV Example --- OVL module assert_n
Page 37 and 38:
Any Problem Whose Problem “My big
Page 39 and 40:
Think --- If you simulate your desi
Page 41 and 42:
Simulation and Assertion-Based Veri
Page 43 and 44:
Formal Verification Technologies De
Page 45 and 46:
Proving “assert_always(p)” In
Page 47 and 48:
Set of Reachable States t0 t1 t2 t3
Page 49 and 50:
Combinational Invariance It is wor
Page 51 and 52:
In this topic, we will use SAT engi
Page 53 and 54:
Boolean Satisfiability (SAT) Fundam
Page 55 and 56:
Complexity of SAT solver We have le
Page 57 and 58:
Something like --- A Decision Tree
Page 59 and 60:
Boolean Satisfiability Checking for
Page 61 and 62:
A Typical Combinational SAT Algorit
Page 63 and 64:
A Typical Combinational SAT Algorit
Page 65 and 66:
a b c d combSat (g7, 0) 1 g1 g2 g3
Page 67 and 68:
a b c d combSat (d, 1) 1 1 g1 g2 g3
Page 69 and 70:
a b c d combSat (d, 1) 1 1 g1 g2 g3
Page 71 and 72:
How many decisions did we make Ther
Page 73 and 74:
Logic Implications Also called “
Page 75 and 76:
How to schedule and evaluate these
Page 77 and 78:
Trying to avoid fruitless implicati
Page 79 and 80:
What’s the improvement Worse case
Page 81 and 82:
Sounds good for all-1’s forward i
Page 83 and 84:
2-Watched-Literal Algorithm H. Zhan
Page 85 and 86:
2-Watched-Literal Algorithm Example
Page 87 and 88:
Caching Effect: Reducing from O(n)
Page 89 and 90:
Difference between circuit and CNF
Page 91 and 92:
Any problem Remember there is only
Page 93 and 94:
A Closer Look 0 1 1 0 0 0 11 1 11 1
Page 95 and 96:
Direct Implication 1. Single source
Page 97 and 98:
Direct vs. Indirect Implications 0
Page 99 and 100:
Watch Scheme for XOR Gate n-input
Page 101 and 102:
Applications of Logic Implication W
Page 103 and 104:
Redundancy in a Combinational Circu
Page 105 and 106:
Mandatory Assignment Example (1) Fa
Page 107 and 108:
1. How do we know a wire in a combi
Page 109 and 110:
How to add an extra wire to make th
Page 111 and 112:
RAMBO: Redundancy Addition and remo
Page 113 and 114:
Is (g5 g9) redundant c 0 b 0 g1 1
Page 115 and 116:
Filtering Out Impossible Candidate
Page 117 and 118: How do we add “something” to a
Page 119 and 120: A Two-Way Redundancy Addition and R
Page 121 and 122: RAR Example (w t : g6 g7) c g4 0 0
Page 123 and 124: 2-Way RAR Algorithm 1. Given a targ
Page 125 and 126: Creating a Redundant Gate (2) g s1
Page 127 and 128: A closer look at the previous examp
Page 129 and 130: Single Wire Replacement Theorem in
Page 131 and 132: A closer look... MA(w t ) a MA(g d
Page 133 and 134: SRAR-Wire vs. Original RAMBO (FYI)
Page 135 and 136: Single Gate Replacement in SatRAR *
Page 137 and 138: Alternative Sub-circuit by SatRAR M
Page 139 and 140: CNF-Based SAT Algorithm 1. Davis, P
Page 141 and 142: Davis Putnam Algorithm M .Davis, H.
Page 143 and 144: Basic DLL Procedure - DFS (a’ + b
Page 151 and 152: Potentially exponential complexity!
Page 153 and 154: Conflict-Driven Learning (a’ + b
Page 155 and 156: Non-Chronological Backtracking (a
Page 157 and 158: Deduced Implication from Learned Cl
Page 159 and 160: Deduced Implication from Learned Cl
Page 161 and 162: A Closer Look at the Implication Gr
Page 163 and 164: Conflict Analysis 2 a = 1 a = 1 a1
Page 165 and 166: Which constraint is the best to add
Page 167: Conflict-Driven Learning Decision l
Page 171 and 172: Conflict-Driven Non-Chronological B
Page 173 and 174: What we have learned on SAT... 1. E
Page 175 and 176: Static Decision Ordering Decision
Page 177 and 178: zChaff’s Variable State Independe
Page 179 and 180: More decision heuristics... Variabl
Page 181 and 182: Remember when we talked about confl
Page 183 and 184: Various Learning Techniques Other
Page 185 and 186: Learned by Signal Correlations A p
Page 187 and 188: Conflict vs. Success-Driven Learnin
Page 189 and 190: Success-Driven Learning Ref: Shuo,
Page 191 and 192: What can we do to make the learning
Page 193 and 194: Recalled, the SAT algorithms we hav
Page 195 and 196: SAT-Based Verification We know tha
Page 197 and 198: However, in the above approach, we
Page 199 and 200: Bounded Model Checking (BMC) Algori
Page 201 and 202: Application of BMC If the property
Page 203 and 204: K-induction Induction: SSS2000 •
Page 205 and 206: Induction SAT for (k = 0 to infinit
Page 207 and 208: Does “Induction SAT” guarantee
Page 209 and 210: Induction over simple paths Let sim
Page 211 and 212: Is the recurrence diameter the same
Page 213 and 214: Outline Overview of Hardware Verif
Page 215 and 216: Symbolic model checking without BDD
Page 217 and 218: Limitation of Formal Engine Still
Page 219 and 220:
Localization abstraction Property:
Page 221 and 222:
Image and over-approximated image
Page 223 and 224:
Remember: Resolution a ∨ b ∨ ¬
Page 225 and 226:
Generating refutations Refutation
Page 227 and 228:
Extraction of Unsatisfiability Core
Page 229 and 230:
Some Definitions for Unsatisfiabili
Page 231 and 232:
Interpolants from Proofs Deriving
Page 233 and 234:
SAT to compute set of reachable sta
Page 235 and 236:
Overapproximation An overapproxima
Page 237 and 238:
Adequate image Img(P,C) P Img’(P,
Page 239 and 240:
Huh A A' B P C C C C C C C F A ⇒
Page 241 and 242:
Reachability algorithm let k = 0 re
Page 243 and 244:
Interpolation-based MC Fully SAT-ba
Page 245 and 246:
Conclusion on Boolean SAT Algorithm
Page 247 and 248:
Some popular SAT engines SATO •
show all

Boolean Satisfiability (SAT) Algorithms

Create successful ePaper yourself

Delete template?

Save as template?