Boolean Satisfiability (SAT) Algorithms

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Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) 0 b 0 a (a + c’ + d) (a + c’ + d’) c ⇐ Backtrack 0 1 ⇐ Forced Decision (b’ + c’ + d) (a’ + b + c’) (a’ + b’ + c) Modified from: Prof. Sharad Malik, “The Quest for Efficient Boolean Satisfiability Solvers” 144 Boolean SAT Algorithms / FLOLAC 2009 Prof. Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw
Basic DLL Procedure - DFS (a’ + b + c) (a + c + d) (a + c + d’) 0 b 0 a ⇐ Backtrack (a + c’ + d) c (a + c’ + d’) 0 1 (b’ + c’ + d) (a’ + b + c’) (a’ + b’ + c) a=0 c=1 Implication Graph (a + c’ + d) (a + c’ + d’) d=1 d=0 Conflict! Modified from: Prof. Sharad Malik, “The Quest for Efficient Boolean Satisfiability Solvers” 145 Boolean SAT Algorithms / FLOLAC 2009 Prof. Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw
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Boolean Satisfiability (SAT) Algori
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What is Verification What’s the p
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#Transistors in Intel’s CPUs Year
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What is Verification What’s the p
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And of course, don’t forget the i
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Improvement on Floating-Point Execu
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A 3-D plot of the ratio 4195835/314
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Aftermath... Intel hired 1000+ PhD
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How do you verify your design Bool
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Simulation-Based Verification Testb
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Like Finding a Bug in an Ocean… B
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Then why is simulation still the ma
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And of course, simulation approach
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Using hardware to speed up simulati
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Verification vs. Testing Objective
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Observability Problem --- Solved In
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The Fact More than 90% of properti
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ABV Example --- OVL module assert_n
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Any Problem Whose Problem “My big
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Think --- If you simulate your desi
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Simulation and Assertion-Based Veri
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Formal Verification Technologies De
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Proving “assert_always(p)” In
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Set of Reachable States t0 t1 t2 t3
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Combinational Invariance It is wor
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In this topic, we will use SAT engi
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Boolean Satisfiability (SAT) Fundam
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Complexity of SAT solver We have le
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Something like --- A Decision Tree
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Boolean Satisfiability Checking for
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A Typical Combinational SAT Algorit
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A Typical Combinational SAT Algorit
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a b c d combSat (g7, 0) 1 g1 g2 g3
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a b c d combSat (d, 1) 1 1 g1 g2 g3
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a b c d combSat (d, 1) 1 1 g1 g2 g3
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How many decisions did we make Ther
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Logic Implications Also called “
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How to schedule and evaluate these
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Trying to avoid fruitless implicati
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What’s the improvement Worse case
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Sounds good for all-1’s forward i
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2-Watched-Literal Algorithm H. Zhan
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2-Watched-Literal Algorithm Example
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Caching Effect: Reducing from O(n)
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Difference between circuit and CNF
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Any problem Remember there is only
Page 93 and 94: A Closer Look 0 1 1 0 0 0 11 1 11 1
Page 95 and 96: Direct Implication 1. Single source
Page 97 and 98: Direct vs. Indirect Implications 0
Page 99 and 100: Watch Scheme for XOR Gate n-input
Page 101 and 102: Applications of Logic Implication W
Page 103 and 104: Redundancy in a Combinational Circu
Page 105 and 106: Mandatory Assignment Example (1) Fa
Page 107 and 108: 1. How do we know a wire in a combi
Page 109 and 110: How to add an extra wire to make th
Page 111 and 112: RAMBO: Redundancy Addition and remo
Page 113 and 114: Is (g5 g9) redundant c 0 b 0 g1 1
Page 115 and 116: Filtering Out Impossible Candidate
Page 117 and 118: How do we add “something” to a
Page 119 and 120: A Two-Way Redundancy Addition and R
Page 121 and 122: RAR Example (w t : g6 g7) c g4 0 0
Page 123 and 124: 2-Way RAR Algorithm 1. Given a targ
Page 125 and 126: Creating a Redundant Gate (2) g s1
Page 127 and 128: A closer look at the previous examp
Page 129 and 130: Single Wire Replacement Theorem in
Page 131 and 132: A closer look... MA(w t ) a MA(g d
Page 133 and 134: SRAR-Wire vs. Original RAMBO (FYI)
Page 135 and 136: Single Gate Replacement in SatRAR *
Page 137 and 138: Alternative Sub-circuit by SatRAR M
Page 139 and 140: CNF-Based SAT Algorithm 1. Davis, P
Page 141 and 142: Davis Putnam Algorithm M .Davis, H.
Page 143: Basic DLL Procedure - DFS (a’ + b
Page 147 and 148: Basic DLL Procedure - DFS (a’ + b
Page 149 and 150: Basic DLL Procedure - DFS (a’ + b
Page 151 and 152: Potentially exponential complexity!
Page 153 and 154: Conflict-Driven Learning (a’ + b
Page 155 and 156: Non-Chronological Backtracking (a
Page 157 and 158: Deduced Implication from Learned Cl
Page 159 and 160: Deduced Implication from Learned Cl
Page 161 and 162: A Closer Look at the Implication Gr
Page 163 and 164: Conflict Analysis 2 a = 1 a = 1 a1
Page 165 and 166: Which constraint is the best to add
Page 167 and 168: Conflict-Driven Learning Decision l
Page 169 and 170: A closer look at binary decision tr
Page 171 and 172: Conflict-Driven Non-Chronological B
Page 173 and 174: What we have learned on SAT... 1. E
Page 175 and 176: Static Decision Ordering Decision
Page 177 and 178: zChaff’s Variable State Independe
Page 179 and 180: More decision heuristics... Variabl
Page 181 and 182: Remember when we talked about confl
Page 183 and 184: Various Learning Techniques Other
Page 185 and 186: Learned by Signal Correlations A p
Page 187 and 188: Conflict vs. Success-Driven Learnin
Page 189 and 190: Success-Driven Learning Ref: Shuo,
Page 191 and 192: What can we do to make the learning
Page 193 and 194: Recalled, the SAT algorithms we hav
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SAT-Based Verification We know tha
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However, in the above approach, we
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Bounded Model Checking (BMC) Algori
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Application of BMC If the property
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K-induction Induction: SSS2000 •
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Induction SAT for (k = 0 to infinit
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Does “Induction SAT” guarantee
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Induction over simple paths Let sim
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Is the recurrence diameter the same
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Outline Overview of Hardware Verif
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Symbolic model checking without BDD
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Limitation of Formal Engine Still
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Localization abstraction Property:
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Image and over-approximated image
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Remember: Resolution a ∨ b ∨ ¬
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Generating refutations Refutation
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Extraction of Unsatisfiability Core
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Some Definitions for Unsatisfiabili
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Interpolants from Proofs Deriving
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SAT to compute set of reachable sta
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Overapproximation An overapproxima
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Adequate image Img(P,C) P Img’(P,
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Huh A A' B P C C C C C C C F A ⇒
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Reachability algorithm let k = 0 re
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Interpolation-based MC Fully SAT-ba
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Conclusion on Boolean SAT Algorithm
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Some popular SAT engines SATO •
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Boolean Satisfiability (SAT) Algorithms

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