Boolean Satisfiability (SAT) Algorithms

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What about circuit properties Finding input assignment inputs circuit cone p = 0 What are the “decisions” • “Assigning input value one at a time” Enumeration method: exponential complexity... • “Assigning values to internal signals” Still exponential complexity... Boolean SAT Algorithms / FLOLAC 2009 Prof. Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw 58
Boolean Satisfiability Checking for Properties on Circuit Finding input assignment inputs Input Boolean space p = 0 b circuit cone a 1 p = 0 0 b a a = 1 a = 0 b = 1 b = 0 A solver to solve this kind of problem is called a Boolean Satisfiability (SAT) Solver Boolean SAT Algorithms / FLOLAC 2009 Prof. Chung-Yang (Ric) Huang http://dvlab.ee.ntu.edu.tw 59
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Boolean Satisfiability (SAT) Algori
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What is Verification What’s the p
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#Transistors in Intel’s CPUs Year
Page 7 and 8: What is Verification What’s the p
Page 9 and 10: And of course, don’t forget the i
Page 11 and 12: Improvement on Floating-Point Execu
Page 13 and 14: A 3-D plot of the ratio 4195835/314
Page 15 and 16: Aftermath... Intel hired 1000+ PhD
Page 17 and 18: How do you verify your design Bool
Page 19 and 20: Simulation-Based Verification Testb
Page 21 and 22: Like Finding a Bug in an Ocean… B
Page 23 and 24: Then why is simulation still the ma
Page 25 and 26: And of course, simulation approach
Page 27 and 28: Using hardware to speed up simulati
Page 29 and 30: Verification vs. Testing Objective
Page 31 and 32: Observability Problem --- Solved In
Page 33 and 34: The Fact More than 90% of properti
Page 35 and 36: ABV Example --- OVL module assert_n
Page 37 and 38: Any Problem Whose Problem “My big
Page 39 and 40: Think --- If you simulate your desi
Page 41 and 42: Simulation and Assertion-Based Veri
Page 43 and 44: Formal Verification Technologies De
Page 45 and 46: Proving “assert_always(p)” In
Page 47 and 48: Set of Reachable States t0 t1 t2 t3
Page 49 and 50: Combinational Invariance It is wor
Page 51 and 52: In this topic, we will use SAT engi
Page 53 and 54: Boolean Satisfiability (SAT) Fundam
Page 55 and 56: Complexity of SAT solver We have le
Page 57: Something like --- A Decision Tree
Page 61 and 62: A Typical Combinational SAT Algorit
Page 63 and 64: A Typical Combinational SAT Algorit
Page 65 and 66: a b c d combSat (g7, 0) 1 g1 g2 g3
Page 67 and 68: a b c d combSat (d, 1) 1 1 g1 g2 g3
Page 69 and 70: a b c d combSat (d, 1) 1 1 g1 g2 g3
Page 71 and 72: How many decisions did we make Ther
Page 73 and 74: Logic Implications Also called “
Page 75 and 76: How to schedule and evaluate these
Page 77 and 78: Trying to avoid fruitless implicati
Page 79 and 80: What’s the improvement Worse case
Page 81 and 82: Sounds good for all-1’s forward i
Page 83 and 84: 2-Watched-Literal Algorithm H. Zhan
Page 85 and 86: 2-Watched-Literal Algorithm Example
Page 87 and 88: Caching Effect: Reducing from O(n)
Page 89 and 90: Difference between circuit and CNF
Page 91 and 92: Any problem Remember there is only
Page 93 and 94: A Closer Look 0 1 1 0 0 0 11 1 11 1
Page 95 and 96: Direct Implication 1. Single source
Page 97 and 98: Direct vs. Indirect Implications 0
Page 99 and 100: Watch Scheme for XOR Gate n-input
Page 101 and 102: Applications of Logic Implication W
Page 103 and 104: Redundancy in a Combinational Circu
Page 105 and 106: Mandatory Assignment Example (1) Fa
Page 107 and 108: 1. How do we know a wire in a combi
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How to add an extra wire to make th
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RAMBO: Redundancy Addition and remo
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Is (g5 g9) redundant c 0 b 0 g1 1
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Filtering Out Impossible Candidate
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How do we add “something” to a
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A Two-Way Redundancy Addition and R
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RAR Example (w t : g6 g7) c g4 0 0
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2-Way RAR Algorithm 1. Given a targ
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Creating a Redundant Gate (2) g s1
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A closer look at the previous examp
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Single Wire Replacement Theorem in
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A closer look... MA(w t ) a MA(g d
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SRAR-Wire vs. Original RAMBO (FYI)
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Single Gate Replacement in SatRAR *
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Alternative Sub-circuit by SatRAR M
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CNF-Based SAT Algorithm 1. Davis, P
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Davis Putnam Algorithm M .Davis, H.
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Basic DLL Procedure - DFS (a’ + b
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Potentially exponential complexity!
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Conflict-Driven Learning (a’ + b
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Non-Chronological Backtracking (a
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Deduced Implication from Learned Cl
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Deduced Implication from Learned Cl
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A Closer Look at the Implication Gr
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Conflict Analysis 2 a = 1 a = 1 a1
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Which constraint is the best to add
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Conflict-Driven Learning Decision l
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A closer look at binary decision tr
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Conflict-Driven Non-Chronological B
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What we have learned on SAT... 1. E
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Static Decision Ordering Decision
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zChaff’s Variable State Independe
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More decision heuristics... Variabl
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Remember when we talked about confl
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Various Learning Techniques Other
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Learned by Signal Correlations A p
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Conflict vs. Success-Driven Learnin
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Success-Driven Learning Ref: Shuo,
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What can we do to make the learning
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Recalled, the SAT algorithms we hav
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SAT-Based Verification We know tha
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However, in the above approach, we
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Bounded Model Checking (BMC) Algori
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Application of BMC If the property
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K-induction Induction: SSS2000 •
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Induction SAT for (k = 0 to infinit
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Does “Induction SAT” guarantee
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Induction over simple paths Let sim
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Is the recurrence diameter the same
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Outline Overview of Hardware Verif
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Symbolic model checking without BDD
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Limitation of Formal Engine Still
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Localization abstraction Property:
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Image and over-approximated image
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Remember: Resolution a ∨ b ∨ ¬
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Generating refutations Refutation
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Extraction of Unsatisfiability Core
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Some Definitions for Unsatisfiabili
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Interpolants from Proofs Deriving
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SAT to compute set of reachable sta
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Overapproximation An overapproxima
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Adequate image Img(P,C) P Img’(P,
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Huh A A' B P C C C C C C C F A ⇒
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Reachability algorithm let k = 0 re
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Interpolation-based MC Fully SAT-ba
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Conclusion on Boolean SAT Algorithm
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Some popular SAT engines SATO •
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Boolean Satisfiability (SAT) Algorithms

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