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Bulk Dielectric Constant (k) Lowering Interconnect Power Consumption Industry Challenge Interconnect power is ~⅓ of total chip power consumption * Technology Enabler Lowering the dielectric constant, k, improves insulation & lowers device power use 3.6 3.2 2.8 2.4 2 4 USG FSG k ~ 3.6 Black Diamond k ~ 3.0 Black Diamond Black II k ~ 2.5 Diamond 3 Lowering interconnect k ~2.2 power by ~10%** per gen. 130nm 90/65nm 45/32nm 22/15nm Logic Technology Node (nm) *Source: Chandra, G.; Kapur, P.; Saraswat, K.C.; "Scaling trends for the on chip power dissipation” **Source: Tada, M.; Inoue, N.; Hayashi, Y.; , "Performance Modeling of Low- /Cu Interconnects for 32-nm-Node and Beyond 14 APPLIED MATERIALS- EXTERNAL USE
DRAM - Approaches to Lowering Power Industry Challenge Technology Enabler Tungsten Gate Lower resistance, lower RC coupling, Endura ® Versa XLR W PVD Transistor Contact Lower resistance enables higher drive current at lower voltage Endura ® HAR Cobalt PVD Oxynitride Gate Increased capacitance enables higher speed and scaling Centura ® DPN HD Gate Stack 15 APPLIED MATERIALS- EXTERNAL USE
Page 1 and 2: Energy Efficiency in Electronics Ge
Page 3 and 4: At A Glance Fiscal 2011 Revenue: $1
Page 5 and 6: Applied Materials Green Initiatives
Page 7 and 8: Setting Aggressive Goals CORPORATE
Page 9 and 10: Trillion Billion Million LOW COST T
Page 11 and 12: Tool Efficiency = GHG/Energy Opport
Page 13: Applied Materials Strategies to Red
Page 17 and 18: Engineering Efficiency into product
Page 19: Summary • Improving the energy ef

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