NAND Flash Architecture and Specification Trends - Micron

NAND Flash Architecture and 

Specification Trends 

Michael Abraham 

Applications Engineering Manager 

Micron Technology, Inc. 

(mabraham@micron.com) 

Santa Clara, CA USA 

August 2009 1

Abstract 

� As NAND Flash continues to shrink, page sizes, block 

sizes, and ECC requirements are increasing while data 

retention, endurance, and performance are decreasing 

� These changes impact systems like random write 

performance and more 

� Learn how to prepare for these changes and counteract 

some of them through improved block management 

techniques and system design 

� This presentation also discusses some of the tradeoff 

myths – for example, the myth that you can directly trade 

ECC for endurance 


August 2009 2

Resolution (nm) 

200 

100 

80 

60 

40 

NAND Flash: 

Shrinking Faster Than Moore’s Law 

Logic 

DRAM 

NAND 

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 

Semiconductor International, 1/1/2007 

Micron 32Gb NAND 

(34nm) 


August 2009 3

Memory Organization Trends 

Over time, NAND block size is increasing 

� Larger page sizes increase sequential throughput 

� More pages per block reduce die size 

4,194,304 

1,048,576 

262,144 

65,536 

16,384 

4,096 

1,024 

256 

64 

16 

Block size (B) Data Bytes per Page Pages per Block 


August 2009 4

Consumer-Grade NAND Flash: 

Endurance and ECC Trends 

� Process shrinks lead to less electrons per floating gate 

� ECC used to improve data retention and endurance 

� To adjust for increasing RBERs, ECC is increasing exponentially to achieve 

equivalent UBERs 

� For consumer applications, endurance becomes less important as density 

increases 

Endurance (Cycles) 

100,000 

10,000 

1,000 

2005 Future 

SLC Endurance MLC-2 Endurance 

MLC-2 ECC SLC ECC 


August 2009 5 

30 

25 

20 

15 

10 

5 

0 

ECC (bits)

Myth: More ECC Extends Block 

Endurance 

� Block endurance is how long a block is usable before program 

or erase status failures occur 

� Applying more ECC than required does not automatically extend 

the block endurance 

� NAND devices are configured to trigger program and erase 

status failures for a specific, fixed ECC value predetermined at 

the factory to meet qualification requirements 

� Applying extra ECC does not change these predetermined 

thresholds, which means that program and erase status failures 

begin to occur at the same cycling intervals regardless of the 

amount of ECC applied 


August 2009 6

80 

60 

40 

20 

0 

Larger Page Sizes Improve 

Sequential Write Performance 

� For a fixed page size, write throughput decreases as 

NAND process shrinks 

� NAND vendors increase the page size to compensate 

for slowing array performance 

� Write throughput decreases with more bits per cell 

SLC MLC-2 MLC-3 

512 2048 4096 8192 2048 4096 8192 4096 8192 

Data Bytes per Page 

Sequential Programming Throughput (MB/s) 


August 2009 7

More Pages Per Block Affect 

Random Write Performance 

� The block copy time is the largest limiting factor for random write 

performance 

� As block copy time increases, random performance decreases 

• Number of pages per block is the dominant factor 

• Increase of t PROG is the next largest factor 

• Increase in I/O transfer time due to increasing page size (effect not shown below) 

is also a factor 

� Some card interfaces have write timeout specs at 250ms, which means 

that block management algorithms manage partial blocks 

500 

400 

300 

200 

100 

0 

32 / 

300 

SLC MLC MLC-2 MLC MLC-3 

64 / 

250 

64 / 

300 

128 / 

250 


August 2009 8 

128 / 

600 

128 / 

900 

256 / 

900 

Pages per Block & t PROG (typ) 

Block Copy Time (ms) 

256 / 

1200 

192 / 

2000+

NAND Interface 

� The NAND interface is increasing in 

throughput 

• Enables better utilization of I/O channels – higher 

bandwidth 

• Immediately useful for single die read 

performance 

• Modest improvement for write performance with 

multiple die 

� Important for SSDs, enterprise applications 

• Reduces I/O channels 


August 2009 9

NAND Interface Trends 

Interface Standard (x8) 

Max Throughput 

(MB/s) 

No standard 40 

ONFI 1.0 Async (12/06) 50 

ONFI 2.0 Sync (2/08) 133 

ONFI 2.1-2.2 Sync (1/09, 9/09) 200 

Toggle Mode (not published) 133 

ONFI 3.0 Sync 400

MB/s 

900 

800 

700 

600 

500 

400 

300 

200 

100 

0 

40 

80 

Async 

167 

333 

The ONFI Advantage 

Single Channel Package Dual Channel Package 

200 

400 

Synchronous 

Target 

800 

Target 

400 

ONFi 1.0 ONFi 2.0 ONFi 2.1 ONFi 3.0 

� Supports simultaneous read, 

program, and erase operations on 

multiple die on the same chip 

enable since ONFI 1.0 

� Only industry-standard NAND 

interface capable of 200 MB/s data 

rate from a single die 

� Two independent channels in a 

single package (doubles the 

bandwidth) 

� In volume production today 

� Headroom for 400 MB/s and beyond 

� Work has already begun on ONFI 

3.0 


August 2009 11

A-Data Afa Technologies Alcor Micro 

Aleph One Anobit Tech. Apacer 

Arasan Chip Systems ASMedia Technology ATI 

Avid Electronics BitMicro Biwin Technology 

Chipsbank Cypress DataFab Systems 

Data I/O Datalight Denali Software 

ENE Technology Entorian FCI 

FormFactor Foxconn Fresco Logic 

Fusion Media Tech Genesys Logic Hagiwara Sys-Com 

HiperSem Hitachi GST Hyperstone 

InCOMM Indilinx Inphi 

Intelliprop ITE Tech Jinvani Systech 

Kingston Technology Lauron Technologies Lotes 

LSI Macronix Marvell 

Mentor Graphics Metaram Moai Electronics 

Molex NVidia Orient Semiconductor 

P.A. Semi Powerchip Semi. Power Quotient International 

Prolific Technology Qimonda Sandforce 

Seagate Shenzhen Netcom Sigmatel 

Silicon Integrated Systems Silicon Motion Silicon Storage Tech 

Silicon Systems STEC Skymedi 

Smart Modular Tech. Solid State System Super Talent Electronics 

Synopsys Tandon Tanisys 

Telechips Teradyne, Inc. Testmetrix 

Transcend Information Tyco UCA Technology 

Santa Clara, CA USA University of York Virident Systems WinBond 

August 2009 12 

Members

Improving System Performance 

� System performance is increased by adding more channels or 

more die per channel 

� Ignoring effects of ECC and block management algorithms, total 

throughput is either array or I/O throughput limited 

Controller 


Flash 
































August 2009 13

Performance (MB/s) 

800 

700 

600 

500 

400 

300 

200 

100 

0 

SLC 4KB Two-Plane Throughput 

Example: Async vs. Sync Interface 

136 160160160 

68 80 80 80 

34 40 40 40 

480 

240 

120 

800 800 800 

400 400 400 

200 200 200 

1 


2 4 8 

19 

1 2 4 8 

1 2 4 8 

1 2 4 8 

1 

4 


38 40 40 

28 56 

# of NAND Die per Channel 

# of Channels 

76 

152 160 160 

38 76 80 80 

448 

224 

224 

400 

112 

200 

112 

56 112 

800

Performance (MB/s) 

800 

700 

600 

500 

400 

300 

200 

100 

0 

MLC 4KB Two-plane Throughput 

Example: Async vs. Sync Interface 

120 160160160 

60 80 80 80 

30 40 40 40 

704 

800 800 

352 

400 400 

352 

176 

176 200 200 

88 

28 56 

160 

112 

14 28 

56 80 

32 64 

128 

16 32 64 

128 

1 


2 4 8 

1 7 

2 4 8 

1 

14 

2 

28 

4 

40 

8 

8 

1 

16 

2 

32 

4 8 

1 

4 


64 

# of NAND Die per Channel 

# of Channels 

256

Conclusions 

� Larger block sizes to become more difficult to manage 

� Page size doubles, increasing sequential performance while reducing 

random performance to compensate for overall slower array throughput 

� ECC increases to compensate for data retention and endurance; still, 

endurance is decreasing for consumer NAND memory 

� 2 bpc MLC has a lower manufacturing cost per bit as long as it is on a 

smaller process node than 3 bpc MLC memory – and it fits more 

customer applications! 

� Pages per block increasing to reduce die size 

� Interface performance increasing to open up a whole new market – 

enterprise solutions – while helping improve SSD performance 

� ONFI provides a proactive, scalable interface for the future with broad 

industry support 


August 2009 16

Questions? 


August 2009 17

About Michael Abraham 

� Manager of Micron’s NAND Flash 

Applications Engineering group 

� B.S. in Computer Engineering from 

Brigham Young University 

� Technical representative for Micron 

in ONFI and JEDEC for NAND Flash 

� Key role in defining and standardizing the highspeed, 

synchronous DDR NAND interface within 

Micron and at ONFI 

©2007-2009 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products 

and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. 

Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 


August 2009 18

NAND Flash Architecture and Specification Trends - Micron

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