Stability Analysis of an All-Electric Ship MVDC Power Distribution ...

Figure 7: Cascade of a PICM-FB controlled buck converter and a PICM-FFFB-controlled VSI. Another buck converter is used to perturb the bus and
extract bus impedance. A high bandwidth CPL added to the bus has the effect of destabilizing the bus.
Viewed from the bus port, the entire system can be lumped
into a 1-port network, as previously described in Section II.
The digital network analyzer technique [23] is the tool used to
measure the bus impedance and address system level stability
issues in a MVDC power distribution system. This technique
uses a switching converter as a perturbation source, and its
controller as a signal analyzer to measure small-signal transfer
functions and impedances of interest. Referring to Fig. 9, a
pseudo-random binary sequence (PRBS) test signal is added to
the duty cycle signal from the feedback controller. Applying
the cross-correlation technique to the appropriate measured
quantities allows online monitoring of the bus impedance
Z bus (s)=V bus (s)/I inj (s).
A. Cascade of Buck Converter and VSI
For this case, the system with only FB control is
marginally stable, while the same system with FFFB control is
highly stabilized. Fig. 10 shows the Bode plot of the bus
impedance, which is the parallel combination of the output
Figure 8: Control of the VSI. PICM-FB loop in the middle and FF loop at the top.
Figure 9: Conceptual block diagram showing injection of a test
signal for system bus impedance measurements.
impedance of the buck converter and the input impedance of
the VSI (Eq. (20). The analytical transfer functions, given in
(20), are compared with the nonparametric results given by the
digital network analyzer in simulation.
Z
⎛ 1 1 ⎞
_
= ⎜
+ ⎟
(20)
bus CL
⎝ Zout
_ CL(
Buck )
Zin
_ CL(
VSI ) ⎠
where CL denotes either FB or FFFB.
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