Micron ® PISMO ™ Module Data Sheet

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PISMO2-00001: Micron Mobile DDR SDRAM + NAND Module 

Introduction 

Micron ® PISMO Module Data Sheet 

PISMO2-00001: Mobile DDR SDRAM + NAND Flash 

Introduction 

Features 

The PISMO (Platform Independent Storage MOdule) specification provides a standard 

external interface to ease memory performance evaluation. This document 

describes the mechanical and functional features, configuration options, and design 

specifications of a Micron ® PISMO2-compliant module. This small, stackable module 

features a combination of Mobile DDR SDRAM and NAND Flash memory, as described 

in Table 1. The board includes: 

Three memory chip footprints (only two are in use at once) 

Bottom connector to the host system (J2) 

Top connector (J1, for stacking multiple boards) 

64Kb serial EEPROM for configuration and presence detection 

PISMO2-00001 options and part markings are described in Figure 12 on page 21. Reference 

documents and data sheets are listed in Table 9 on page 21. 

Physical Module Mechanics 

Stackable memory module (up to four active modules) 

Plain rectangular PCB (60mm x 50mm) 

Stacking height: 7mm (other stacking heights will become available later) 

Supports additional debugging tools (for example, a logic analyzer adapter) 

Supports spacers with or without screw option 

Supported Memory Interfaces 

Dynamic memory: 128Mb, 256Mb, 512Mb, and 1Gb; x32; 1.8V Micron Mobile DDR 

SDRAM MT46HxxM32LF 

NAND memory: 1Gb; x8 or x16; 1.8V NAND Flash memory MT29F1G08BB or 

MT29F1G16AB 

Serial EEPROM for presence detection: 64Kb 

PDF: 09005aef827fda9b/Source: 09005aef827fda71 Micron Technology, Inc., reserves the right to change products or specifications without notice. 

PISMO2_00001_datasheet.fm - Rev. B 11/07 EN 1 ©2007 Micron Technology, Inc. All rights reserved. 

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by 

Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.

Table 1: PISMO2-00001 Module Memory Technologies 

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Features 

Technology Density Voltage Data Bus Package 

Mobile DDR SDRAM 128Mb to 1Gb 1.8V 32-bit 90-ball VFBGA 

NAND Flash 1Gb 1.8V 8- or 16-bit, 

multiplexed 

63-ball FBGA 

Figure 1: Micron Mobile DDR SDRAM and NAND PISMO2 Module (PISMO2-00001) 

Top side 

(Lock) 

J5 

Micron Part-Specific Features 

C14 

C3 

C4 C34 

C15 

J1 

Mobile 

DDR 

U3 

Bottom side 

NAND 

(x16) 

U10 (x16) 

NAND 

(x8) 

U11 (x8) 

For part-specific features, refer to the data sheets listed on any of the following Micron 

product pages: 

Mobile DDR SDRAM—www.micron.com/products/mobiledram/ddrsdram 

NAND Flash—www.micron.com/products/nand 



J2 

C35 

(CS) 

(PWR) 

R12 

R11 

U9 

C36 

C6 

C29 

C13 

R20 1.8 

R19 3.3 

RN8 

RN7 

R14 

RN6 

RN5 

RN4 

RN3 

R8 

RN2 

RN1 

R7 

C18 

C2 

R6 R3 

C31 

C33 

C30 C21 C5 

C20 

C32 

C19 C26 

C24 

C27 C28 

C1 

C25 

C17 

C16 

C48 

R23 

(1V8) 

R21 

C22 

C47 

C46 

R9 

R10 

R15 

(CS) 

R18 

R16 

R17 

C41 C40 

C43 

R22 

C42 

C39 C38 C37 

C44 C45 

C23

Pin Assignments and Descriptions 

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Table 3 on page 4 and Table 4 on page 5 illustrate the signal locations within the bottom 

and top PISMO2-00001 connectors, respectively. The meanings of the signal name 

prefixes are explained in Table 2. 

Table 2: Naming Conventions for PISMO2 Specification Signals 

Signal Prefix Definition 

SM The “SM_” prefix identifies PISMO2 static memory interface signals. This 

interface supports NOR Flash, DiskOnChip, SRAM and PSRAM memory, and 

memory-mapped I/O devices. 

DM The “DM_” prefix identifies PISMO2 dynamic memory interface signals. This 

interface supports single data rate (SDR) or double data rate (DDR) SDRAM 

memory. 

NA The “NA_” prefix identifies PISMO2 NAND memory interface signals. This 

interface supports NAND Flash memory. 

FS The “FS_” prefix identifies PISMO2 serial memory interface signals. This 

interface supports serial Flash memory or I/O devices with a serial bus 

interface. 

AUX The “AUX_” prefix identifies PISMO2 module management interface 

signals. This interface supports hardware production and testing, module 

control functions, and plug-and-play enumeration. 


PISMO2_00001_datasheet.fm - Rev. B 11/07 EN 3 ©2007 Micron Technology, Inc. All rights reserved.

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Table 3: PISMO2-00001 Bottom Connector (J2) Pin Assignments 

Col. Row A Row B Row C Row D Row E Row F Row G Row H 

1 DM_DQS3_DH DM_DQS3_DL DNU11 DM_CS1_N VSS46 FS_SCK FS_SO FS_RESET_N 

2 DM_D26 DM_D24 DM_BA2 DM_A15 DM_A4 VSS45 FS_SI FS_HOLD_N 

3 DM_D27 DM_D25 DM_RESET_N DM_A7 DM_A6 FS_V33_0 DNU9 FS_CS3_N 

4 DM_D29 DM_D28 DM_ODT1 DM_A11 DM_A9 VSS44 FS_VIO_1 FS_CS2_N 

5 DM_D30 DM_D31 DM_ODT0 DM_CKE1 DM_CKE0 VSS43 FS_VIO_0 FS_CS1_N 

6 DM_DQS1_DH DM_DQS1_DL DM_VREF DM_A14 DM_DQM3 VSS42 FS_V18_0 FS_CS0_N 

7 DM_D8 DM_D9 DM_VIO_9 DM_A8 DM_A12 VSS41 FS_WP_N AUX_SA2 

8 DM_D10 DM_D11 DM_VIO_3 DM_DQM1 DM_A5 VSS40 AUX_SCL AUX_SA1 

9 DM_D12 DM_D13 DM_VIO_6 VSS37 VSS38 VSS39 AUX_SDA AUX_SA0 

10 DM_D15 DM_D14 DM_VIO_5 DM_CLK1_DH DM_CLK1_DL VSS36 AUX_TDI AUX_TDO 

11 DM_D1 DM_D0 DM_VIO_8 VSS34 VSS35 AUX_V33_1 AUX_TCK AUX_TMS 

12 DM_D3 DM_D2 DM_VIO_4 DM_CLK0_DH DM_CLK0_DL VSS33 DNU13 AUX_PRESENT_N 

13 DM_D5 DM_D4 DM_VCC_3 VSS31 VSS32 AUX_V33_0 AUX_POR_N AUX_HMR_N 

14 DM_D6 DM_D7 DM_VIO_2 DM_A10 DM_A2 VSS30 AUX_V33_2 AUX_STANDBY_N 

15 DM_DQS0_DH DM_DQS0_DL DM_VIO_7 DM_WE_N DM_CS0_N VSS29 NA_RY_3 NA_LCK 

16 DM_D16 DM_D17 DM_VCC_2 DM_DQM0 DM_A13 NA_VIO_2 NA_IO15 NA_IO7 

17 DM_D19 DM_D18 DM_VCC_1 DM_RAS_N DM_CAS_N VSS28 NA_IO14 NA_IO6 

18 DM_D22 DM_D20 DM_VIO_1 DM_BA1 DM_BA0 VSS27 NA_IO13 NA_IO5 

19 DM_D23 DM_D21 DM_VIO_0 DM_A1 DM_A0 VSS26 NA_IO12 NA_IO4 

20 DM_DQS2_DH DM_DQS2_DL DM_VCC_0 DM_DQM2 DM_A3 VSS25 NA_IO11 NA_IO3 

21 VSS20 VSS21 VSS22 VSS23 VSS24 NA_VIO_1 NA_IO10 NA_IO2 

22 SM_D23 SM_D31 SM_V33_2 SM_A30 SM_A31 VSS19 NA_IO9 NA_IO1 


24 SM_D21 SM_D29 SM_V33_0 SM_A26 SM_A27 VSS17 DNU12 NA_PRE 

25 SM_D20 SM_D28 SM_VIO_8 SM_A24 SM_A25 VSS16 NA_RY_0 NA_RE_N 

26 SM_D19 SM_D27 SM_VIO_7 SM_A22 SM_A23 NA_VIO_0 NA_CS2_N NA_CS3_N 

27 SM_D18 SM_D26 SM_VIO_6 SM_A20 SM_A21 NA_V33_0 NA_CS1_N NA_CS0_N 

28 SM_D17 SM_D25 SM_VIO_5 SM_A18 SM_A19 NA_V18_0 NA_CLE NA_ALE 

29 SM_D16 SM_D24 SM_CLK3 SM_A16 SM_A17 VSS15 NA_WE_N NA_WP_N 

30 DNU16 VSS12 SM_CLK2 VSS13 SM_BE2 VSS14 NA_RY_1 NA_RY_2 

31 DNU17 VSS9 SM_CLK1 VSS10 SM_BE3 SM_OE_N VSS11 DNU4 

32 SM_D7 SM_D15 SM_CLK0 SM_A14 SM_A15 SM_WE_N VSS8 DNU3 

33 SM_D6 SM_D14 SM_VIO_4 SM_A12 SM_A13 SM_LBA_N VSS7 SM_WP_N 

34 SM_D5 SM_D13 SM_VIO_3 SM_A10 SM_A11 SM_BUSY_N_0 VSS6 SM_RESET_N 

35 SM_D4 SM_D12 SM_VIO_2 SM_A8 SM_A9 SM_BWAIT_N VSS5 SM_PD 

36 SM_D3 SM_D11 SM_VIO_1 SM_A6 SM_A7 VSS4 SM_BUSY_N_2 SM_BUSY_N_3 

37 SM_D2 SM_D10 SM_VIO_0 SM_A4 SM_A5 VSS3 SM_IRQ_N SM_CS3_N 

38 SM_D1 SM_D9 SM_V18_2 SM_A2 SM_A3 VSS2 SM_CRE SM_CS2_N 

39 SM_D0 SM_D8 SM_V18_1 SM_A0 SM_A1 VSS1 SM_DMARQ_N SM_CS1_N 

40 DNU14 DNU15 SM_V18_0 SM_BE0 SM_BE1 VSS0 SM_BUSY_N_1 SM_CS0_N 



Table 4: PISMO2-00001 Top Connector (J1) Pin Assignments 

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Col. Row A Row B Row C Row D Row E Row F Row G Row H 

1 DM_DQS3_DH DM_DQS3_DL DNU11 DM_VIO VSS46 FS_SCK FS_SO FS_RESET_N 

2 DM_D26 DM_D24 DM_BA2 DM_A15 DM_A4 VSS45 FS_SI FS_HOLD_N 

3 DM_D27 DM_D25 DM_RESET_N DM_A7 DM_A6 FS_V33_0 DNU9 FS_CS3_N 

4 DM_D29 DM_D28 DM_ODT1 DM_A11 DM_A9 VSS44 FS_VIO_1 FS_CS2_N 

5 DM_D30 DM_D31 DM_ODT0 DM_CKE1 DM_CKE0 VSS43 FS_VIO_0 FS_CS1_N 

6 DM_DQS1_DH DM_DQS1_DL DM_VREF DM_A14 DM_DQM3 VSS42 FS_V18_0 FS_CS0_N 

7 DM_D8 DM_D9 DM_VIO_9 DM_A8 DM_A12 VSS41 FS_WP_N AUX_SA1 

8 DM_D10 DM_D11 DM_VIO_3 DM_DQM1 DM_A5 VSS40 AUX_SCL AUX_SA0 

9 DM_D12 DM_D13 DM_VIO_6 VSS37 VSS38 VSS39 AUX_SDA AUX_V33 

10 DM_D15 DM_D14 DM_VIO_5 DM_CLK1_DH DM_CLK1_DL VSS36 AUX_TDI AUX_TDO 

11 DM_D1 DM_D0 DM_VIO_8 VSS34 VSS35 AUX_V33_1 AUX_TCK AUX_TMS 

12 DM_D3 DM_D2 DM_VIO_4 DM_CLK0_DH DM_CLK0_DL VSS33 DNU13 AUX_PRESENT_N 

13 DM_D5 DM_D4 DM_VCC_3 VSS31 VSS32 AUX_V33_0 AUX_POR_N AUX_HMR_N 

14 DM_D6 DM_D7 DM_VIO_2 DM_A10 DM_A2 VSS30 AUX_V33_2 AUX_STANDBY_N 

15 DM_DQS0_DH DM_DQS0_DL DM_VIO_7 DM_WE_N DM_CS1_N VSS29 NA_RY_3 NA_LCK 

16 DM_D16 DM_D17 DM_VCC_2 DM_DQM0 DM_A13 NA_VIO_2 NA_IO15 NA_IO7 

17 DM_D19 DM_D18 DM_VCC_1 DM_RAS_N DM_CAS_N VSS28 NA_IO14 NA_IO6 

18 DM_D22 DM_D20 DM_VIO_1 DM_BA1 DM_BA0 VSS27 NA_IO13 NA_IO5 

19 DM_D23 DM_D21 DM_VIO_0 DM_A1 DM_A0 VSS26 NA_IO12 NA_IO4 

20 DM_DQS2_DH DM_DQS2_DL DM_VCC_0 DM_DQM2 DM_A3 VSS25 NA_IO11 NA_IO3 

21 VSS20 VSS21 VSS22 VSS23 VSS24 NA_VIO_1 NA_IO10 NA_IO2 



24 SM_D21 SM_D29 SM_V33_0 SM_A26 SM_A27 VSS17 DNU12 NA_PRE 

25 SM_D20 SM_D28 SM_VIO_8 SM_A24 SM_A25 VSS16 NA_RY_0 NA_RE_N 

26 SM_D19 SM_D27 SM_VIO_7 SM_A22 SM_A23 NA_VIO_0 NA_CS3_N NA_VIO 

27 SM_D18 SM_D26 SM_VIO_6 SM_A20 SM_A21 NA_V33_0 NA_CS2_N NA_CS1_N 

28 SM_D17 SM_D25 SM_VIO_5 SM_A18 SM_A19 NA_V18_0 NA_CLE NA_ALE 

29 SM_D16 SM_D24 SM_CLK3 SM_A16 SM_A17 VSS15 NA_WE_N NA_WP_N 

30 DNU16 VSS12 SM_CLK2 VSS13 SM_BE2 VSS14 NA_RY_1 NA_RY_2 

31 DNU17 VSS9 SM_CLK1 VSS10 SM_BE3 SM_OE_N VSS11 DNU4 

32 SM_D7 SM_D15 SM_CLK0 SM_A14 SM_A15 SM_WE_N VSS8 DNU3 

33 SM_D6 SM_D14 SM_VIO_4 SM_A12 SM_A13 SM_LBA_N VSS7 SM_WP_N 

34 SM_D5 SM_D13 SM_VIO_3 SM_A10 SM_A11 SM_BUSY_N_0 VSS6 SM_RESET_N 

35 SM_D4 SM_D12 SM_VIO_2 SM_A8 SM_A9 SM_BWAIT_N VSS5 SM_PD 

36 SM_D3 SM_D11 SM_VIO_1 SM_A6 SM_A7 VSS4 SM_BUSY_N_2 SM_BUSY_N_3 

37 SM_D2 SM_D10 SM_VIO_0 SM_A4 SM_A5 VSS3 SM_IRQ_N SM_CS3_N 

38 SM_D1 SM_D9 SM_V18_2 SM_A2 SM_A3 VSS2 SM_CRE SM_CS2_N 

39 SM_D0 SM_D8 SM_V18_1 SM_A0 SM_A1 VSS1 SM_DMARQ_N SM_CS1_N 

40 DNU14 DNU15 SM_V18_0 SM_BE0 SM_BE1 VSS0 SM_BUSY_N_1 SM_CS0_N 

Table 5 on page 6 lists and briefly describes all (and only) the signals that are routed to 

and from the memory devices installed on the PISMO2-00001 with reference to the 

corresponding bottom connector ball. 



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Table 5: PISMO2-00001 Ball Descriptions (Referenced to the Bottom Connector) 

Ball No. (Bottom) Symbol Type Description 

DRAM Section 

D12, E12 DM_CLK0_DH Input System clock: DM_CLK_DH and DM_CLK_DL are differential 

DM_CLK0_DL 

clock inputs. All address and control input signals are sampled 

on the positive edge of DM_CLK_DH and the negative edge of 

DM_CLK_DL. Output (read) data is referenced to both edges of 

DM_CLK. Internal clock signals are derived from DM_CLK_DH/ 

DM_CLK_DL. SDRAM and Mobile SDRAM only use 

DM_CLK_DH. Both DM_CLK_DH and DM_CLK_DL apply to 

DDR, Mobile DDR, and DDR2 SDRAM. 

E5 DM_CKE0 Input Clock enable: DM_CKE HIGH activates, and DM_CKE LOW 

deactivates, internal clock signals and device input buffers and 

output drivers. Taking DM_CKE LOW provides PRECHARGE, 

POWER-DOWN, and SELF REFRESH operation (all banks idle) or 

active power-down (row active in any bank). DM_CKE is 

synchronous for power-down entry and exit and for self 

refresh entry. DM_CKE is asynchronous for self refresh exit. 

E15 DM_CS0_N Input Chip select: DM_CS_N enables (registered LOW) and disables 

(registered HIGH) the command decoder. All commands are 

masked when DM_CS_N is registered HIGH. DM_CS_N provides 

external bank selection on multibank systems. DM_CS_N is 

considered part of the command code. 

D17 DM_RAS_N Input Row address strobe: Latches row addresses on the positive 

edge of the DM_CLK with DM_RAS_N LOW. Enables row access 

and precharge. 

E17 DM_CAS_N Input Column address strobe: Latches column addresses on the 

positive edge of the DM_CLK with DM_CAS_N LOW. Enables 

column access. 

D15 DM_WE_N Input Write enable: Enables WRITE operation and row precharge. 

Latches data in starting from DM_CAS_N, DM_WE_N active. 

D16, D8, D20, E6 DM_DQM0 to 

DM_DQM3 

E18, D18 DM_BA0, 

DM_BA1 

E19, D19, E14, E20, E2, E8, 

E3, D3, D7, E4, D14, D4, E7 

B11, A11, B12, A12, B13, 

A13, A14, B14, A7, B7, A8, 

B8, A9, B9, B10, A10, A16, 

B16, B17, A17, B18, B19, 

A18, A19, B2, B3, A2, A3, 

B4, A4, A5, B5 

DM_A0 to 

DM_A12 

DM_D0 to 

DM_D31 

A15, A6, A20, A1 DM_DQS0_DH 

to 

DM_DQS3_DH 

C19, C18, C14, C8, C12, 

C10, C9, C15, C11, C7 

DM_VIO_0 to 

DM_VIO_9 

Input Data input/output mask: Makes data output High-Z, t SHZ after 

the clock and masks the output. Blocks data input when 

DM_DQM active. 

Input Bank select address: DM_BA0 and DM_BA1 define to which 

bank an ACTIVE, READ, WRITE, or PRECHARGE command is 

applied. Bank address also determines whether the mode 

register or extended mode register is to be accessed during an 

MRS or EMRS cycle. 

Input Address: Row/column addresses are multiplexed on the same 

pins. 

I/O Data input/output: Data inputs/outputs are multiplexed on the 

same pins. 

I/O Data strobes: Output with read data, input with write data. 

Edge-aligned with read data, center-aligned with write data. 

Only applicable to DDR and DDR2 SDRAM. 

Supply Data output power: Isolates the output buffer power supply to 

provide improved noise immunity. 



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Table 5: PISMO2-00001 Ball Descriptions (Referenced to the Bottom Connector) (continued) 


C20, C17, C16, C13 DM_VCC_0 to 

DM_VCC_3 

Supply Power supply: Power for the core logic. 

E16 DM_A13 Input Upgrade address input for future devices (selected via R5). 

NAND Section 

H28 NA_ALE Input Address latch enable: Controls the address registers. When 

active (HIGH), an address is latched from NA_IO0–NA_IO7 into 

the address registers with the rising edge of the write enable 

signal. When addresses are not being loaded, NA_ALE is driven 

LOW. 

H27 NA_CS0_N Input Chip enable (active-LOW signal): These device select control 

signals are active (LOW) and are ignored during any of the 

busy states. The NAND devices go into a low-power standby 

mode when driven HIGH during ready states. The host should 

implement as many chip-select signals as supported by the 

host CPU, starting at NA_CS0_N and pull up all remaining 

NA_CSN_N signals to NA_VIO. 

G28 NA_CLE Input Command latch enable: Controls the command register. When 

active (HIGH), commands are latched from NA_IO0–NA_IO7 

into the register with the rising edge of the write enable 

signal. When a command is not being loaded, this signal is 

driven LOW. 

H25 NA_RE_N Input Read enable (active-LOW signal): Initiates the transfer of 

information from the device to the host and increments the 

internal column counter by one. Information is valid when it is 

active (LOW) and is driven HIGH when information is not being 

transferred. 

G29 NA_WE_N Input Write enable (active-LOW signal): Initiates the transfer of 

information from the host to the device. Command, address, 

and data are latched with the rising edge, and WE is driven 

HIGH when information is not being transferred. 

H29 NA_WP_N Input Write protect (active-LOW signal): Provides a hardware 

method for protecting NAND memory contents. LOW means 

write-protected. 

H23, H22, H21, H20, H19, 

H18, H17, H16, G23, G22, 

G21, G20, G19, G18, G17, 

G16 

NA_IO0 to 

NA_IO15 

I/O Data inputs and outputs: These bidirectional signals are used 

to input command and address. They can input data during 

WRITE operation and output data during READ operation. All 

signals are inputs during non-READ operations. 

H15 NA_LCK Input When NA_LCK is HIGH during power-up, the BLOCK LOCK 

function is enabled. To disable the BLOCK LOCK, connect 

NA_LCK to VSS during power-up, or leave it unconnected 

(internal pull-down). 

G25 NA_RY Output Ready/Busy: Indicates the operating condition of the device. It 

is busy, active (LOW) during PROGRAM, ERASE, and READ 

operation and returns to ready, active (HIGH) after completing 

the operation. This signal is an open-drain output buffer on 

memory modules. The host must implement a pull-up resistor 

to NA_VIO. The value of this pull-up resistor determines the 

rise time of the NA_RY signal and should be calculated as 

specified in the NAND Flash memory data sheets. 



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Table 5: PISMO2-00001 Ball Descriptions (Referenced to the Bottom Connector) (continued) 


F28 

EEPROM Section 

NA_V18_0 Supply 1.8V power supply: The host implementation supplies 1.8V DC 

on this pin, independent of the I/O voltage. This power supply 

is used as memory core voltage. 

H9, H8, H7 AUX_SA0 to 

AUX_SA2 

Input Used by the EEPROM for multiple device operation. The levels 

on these inputs are compared with the corresponding bits in 

the slave address. The chip is selected if the comparison is true. 

Up to eight devices may be connected to the same bus by 

using different chip-select bit combinations. 

G8 AUX_SCL Input Synchronizes data transfer to and from the device. 

G9 AUX_SDA I/O This bidirectional pin transfers addresses and data into and 

data out of the device. It is an open-drain terminal; therefore, 

the SDA bus requires a pull-up resistor to VCC (typical 10kΩ for 

100 kHz, 2kΩ for 400 kHz). For normal data transfer, SDA is 

allowed to change only during SCL LOW. Changes during SCL 

HIGH are reserved for indicating start and stop conditions. 

F13, F11, G14 AUX_V33_0 to 

AUX_V33_2 

Supply +1.8V to 5.5V power supply. 

Ground Pins 

F40, F39, F38, F37, F36, 

G35, G34, G33, G32, B31, 

D31, G31, B30, D30, F30, 

F29, F25, F24, F23, F22, 

A21, B21, C21, D21, E21, 

F20, F19, F18, F17, F15, 

F14, D13, E13, F12, D11, 

E11, F10, D9, E9, F9, F8, F7, 

F6, F5, F4, F2, E1 

VSS0 to VSS46 Supply Ground. 



Functional Block Diagram 

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Functional Block Diagram 

Figure 2 illustrates the connections among the host system, the PISMO2-00001 DRAM 

and NAND interface, and the Micron DRAM and NAND devices. All NAND and DRAM 

interface signals are also connected straight through from bottom to top on the PISMO2 

connector except NA_CS[3:0] and DM_CS[1:0], which are connected as shown in“Chip- 

Select Routing” on page 10. The STATIC and FAST SERIAL interface signals are only 

“routed through” (no devices are connected). 

For clarity, in Figure 2, the NAND and DRAM interface signal connections between the 

top and bottom connectors have been omitted. 

Figure 2: PISMO2-00001 Functional Block Diagram 

CPU PISMO2-00001 

DRAM Controller 

DRAM 

Interface 

NAND Controller 

NAND 

Interface 

Auxiliary Signals 

Controller 

Auxiliary 

Interface 

DRAM 

Interface 

DM_ BUS 

NAND 

Interface 

NA_ BUS 

Auxiliary 

Signals 

Interface 

AUX_ BUS 

Mobile DDR 

SDRAM 

MT46H16M32LF 

1.8V NAND Flash 

MT29F1G16AB 

Microchip 

24AA64-I/ST I2C 

Serial EEPROM 



Chip-Select Routing 

Design for Testability 

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The PISMO2 specification enables the DRAM interface to support up to two memory 

banks, adopting the same signaling, whereas up to four memory banks can be 

connected to the NAND interface. The Micron PISMO2-00001 memory module uses one 

DRAM and one NAND bank. Table 6 clarifies the chip-select routing scheme adopted for 

this implementation. This method automatically maps host controller chip-select 

signals to the NAND memory banks installed within a PISMO2 memory module stack. 

If the number of stacked memory banks exceeds host controller support, only the first 

two DRAM and the first four NAND banks (starting at the bottommost module) are used. 

All remaining banks are forced inactive. 

Table 6: PISMO2-00001 DRAM and NAND Interface Chip-Select Routing 

Memory Interface 

DRAM interface: 

– 1 device installed 

– 1 CS_N used 

NAND interface: 

– 1 device installed 

– 1 CS_N used 

Chip-Select Connections 

Bottom Side Top Side 

DM_CS0_N 

DM_CS1_N 

DM_VIO 

NA_CS0_N 

NA_CS1_N 

NA_CS2_N 

NA_CS3_N 

NA_VIO 

To Mobile DDR 

DM_CS0_N 

DM_CS1_N 

To NAND 

NA_CS0_N 

NA_CS1_N 

NA_CS2_N 

NA_CS3_N 

To the 

NAND 

device 

Top connector 

To the 

DRAM 

device 


DM_CS0_N 

DM_CS0_N 

Bottom connector 

Top connector 

DM_CS1_N 

DM_CS1_N 

DM_VIO 

NA_CS0# NA_CS1# NA_CS2# NA_CS3# 

NA_CS0# NA_CS1# NA_CS2# NA_CS3# 

Bottom connector 

NA_VIO 

Although the PISMO2 specification prohibits routing used chip selects back to the top 

connector, the PISMO2-00001 board features a configuration option that enables the 

user to scope CS# with the Micron PISMO2-P6960 logic state analyzer adapter (LSA) tile. 

Every chip-select signal that is connected to an installed memory chip can be routed 

back to the higher CS# position available for the bank on the top connector, just by 

moving a configuration resistor. (For example, the NA_CS0_N ball of the bottom 

connector is routed back to NA_CS3_N position of the top connector by R10.) Configuration 

options are listed in Table 7 on page 11. See the PISMO2-P6960 data sheet for more 

information. 



Table 7: PISMO2-00001 CS# Feedback Configurations 

Serial Presence-Detect 

Advance 


Serial Presence-Detect 

Configuration 

Resistor Signal 

Top Connector 

Position Notes 

R11 DM_VIO D1 If R11 is installed, the board is compliant 

with the PISMO2 specification. 

R12 DM_CS0_N D1 If R12 is installed, the CS is routed back 

to the top connector. 

R9 NA_POWER H26 If R9 is installed, the board is compliant 

with the PISMO2 specification. 

R10 NA_CS0_N H26 If R10 is installed, the CS is routed back 

to the top connector. 

The Micron PISMO2-00001 module features serial presence-detect (SPD). The SPD 

function is implemented using a 64Kb serial EEPROM compliant with the PISMO2 specification. 

This nonvolatile storage device contains 8KB. System READ/WRITE operations 

between the master (host system) and the slave EEPROM device occur via a standard I 2 C 

bus using the PISMO2-00001 AUX_SCL (clock) and AUX_SDA (data) signals, together 

with AUX_SA[2:0], which provide eight unique PISMO2/EEPROM addresses. The 

memory write protect pin (WP#) is tied to ground on the module, permanently disabling 

hardware write protect. All these signals are in the AUX_V33 I/O voltage domain, which 

is fixed at 3.3V. 

The configuration EEPROM contains information about the memory module itself, such 

as vendor, complete part number, and serial number. It also contains information about 

the memory devices installed on the module. The operating system or the application 

running on the host system processor can use the data from the configuration EEPROM 

to perform the following tasks: 

Initialize the memory space 

Identify the PISMO2 memory card vendors, model, and revision 

Validate system configurations 

Query product names of installed memory devices in terms of speed grade, data bus 

width, density of memory chip, and addressing scheme 

Query key memory device parameters, such as timing and voltage options 

Optimize host controller settings according to detected memory parameters 

Select optimized programming algorithms 

Select software drivers based on identified memory modules 

Obtain additional vendor-specific information 

The Micron PISMO2-00001 board complies with the PISMO 2.0 specification, which 

defines a scheme for automatically assigning two-wire addresses to two-wire devices on 

the memory module. As shown in Figure 3 on page 12, the PISMO2-00001 module automatically 

assigns two-wire device addresses by module location in the stack. No additional 

logic is required for this function. 



Advance 


Serial EEPROM Data Structure 

Figure 3: PISMO2-00001 Two-Wire Address Generation Scheme 

Table 8: EEPROM Addresses 

Serial EEPROM Data Structure 

Host Memory Module A Memory Module B 

The connections shown in Figure 3 result in the two-wire device address assignments 

shown in Table 8. 

Memory Module Stack Location EEPROM Address (Hexadecimal) 

1 st memory module (bottommost) 0xA0 (WRITE), 0xA1 (READ) 

2nd memory module 0xA2 (WRITE), 0xA3 (READ) 

3rd memory module 0xA6 (WRITE), 0xA7 (READ) 

4 th memory module (topmost) 0xAE (WRITE), 0xAF (READ) 

TBD 

AUX_V33 AUX_V33 

AUX_SCL 

AUX_SDA 

AUX_SA0 

AUX_SA1 

AUX_SA2 

Bottom Top Bottom 

AUX_SCL 

AUX_SDA 

AUX_SA0 

AUX_SA1 

AUX_SA2 

Two-wire address(es): 

AUX_SCL 

AUX_SDA 

AUX_SA0 

AUX_SA1 

AUX_SA2 

On-board 

two-wire device(s) 



SCL 

SDA 

A0 

A1 

A2 

A6 A5 A4 A3 0 0 0 R/W 

AUX_SCL 

AUX_SDA 

AUX_SA0 

AUX_SA1 

AUX_SA2 

AUX_V33 

Two-wire address(es): 

2 nd module: xxxx001x 

3 rd module: xxxx011x 

4 th module: xxxx111x

Mechanical Specifications 

Connector Description 

Figure 4: PISMO2 Connectors 

For clarity, some contacts are not shown 

Advance 



The PISMO2-00001 board/host system connection is provided by a Samtec SE (singleended) 

array connector system designed for high-speed/high-density applications 

where high pin-count flexibility, space savings, and routability are critical. The Edge 

Rate blade and beam interface was designed to provide maximum signal integrity at 

50Ω on a popular 0.050in x 0.050in grid. The SE array connector has been tested up to 

4 GHz (single-ended) and 9 GHz (differentially) at the 7mm mated height. 

Connector Specifications 

Male P/N: SEAM-40-02.0-SM-8-2-A-K 

Female P/N: SEAF-40-05.0-SM-8-2-A-K 

Black liquid crystal polymer 

320 positions (8 x 40 grid) 

1.27mm (0.050in) pitch 

7mm mated height 

30 microinch Au duplex contact plating 

Copper alloy contact material 

–55°C to +125°C operating temperature range 

Pb-free solder 

Memory Module 

SEAF (female) connector SEAM (male) connector 

Figure 5 on page 14 illustrates the mechanical construction of the PISMO2-00001 

memory module. The A1 mark denotes the location of the A1 pin on both connectors. 



Figure 5: PISMO2-00001 Memory Module Dimensions 

Advance 



Top view Bottom view 

Side views 

11.2 

1.5 

26.0 

60.0 

30.0 

26.0 

A1 

The bottom side is used as the primary assembly side. The top side carries module documentation, 

such as the label. 



39.0 

7.0 

50.0 

SEAF (female/top) 

SEAM (male/bottom) 

A1

Vertical Space 

Advance 



The connectors chosen for PISMO2 use a 7mm stacked height. This means that a 7mm 

vertical space exists between the host system and the first memory module PCBs and 

also between the PCBs of the two neighboring memory modules. The PISMO2 specification 

defines requirements for vertical space assignments on PISMO2 memory modules 

and host controllers. Because Micron’s PISMO2-00001 complies with this requirement, it 

can be plugged into any PISMO2 host controller or on top of any other memory module. 

Figure 6 illustrates the PISMO2 vertical space requirements. 

Figure 6: PISMO2-00001 Vertical Space Requirements 

SEAF 

SEAM 

Top side 

Maximum component height: 2mm 

Label 

Ø8.0 Ø8.0 

Bottom (assembly side) 

Maximum component height: 4mm 

No components in keep-out areas 

around mounting holes 

Ø8.0 Ø8.0 



Label 

Assembly side



Schematics 

Figure 7: Bottom Connector Schematic 

5 

5 

4 

4 

3 

SM_A[0..31] J2B 

SM_D[0..31] 

SM_A[0..31] SEAM-40-02.0-S-08-2-A-K SM_D[0..31] 

D 

C 

B 

DM_DQM[0..3] 

DM_DQM[0..3] 

DM_D[0..31] 

DM_D[0..31] 

DM_A[0..15] 

DM_A[0..15] 

DM_A0 

DM_D0 

DM_A1 

DM_D1 

DM_A2 

DM_D2 

DM_A3 

DM_D3 

DM_A4 

DM_D4 

DM_A5 

DM_D5 

DM_A6 

DM_D6 

DM_A7 

DM_D7 

DM_A8 

DM_D8 

DM_A9 

DM_D9 

DM_A10 

DM_D10 

DM_A11 

DM_D11 

DM_A12 

DM_D12 

DM_A13 

DM_D13 

DM_A14 

DM_D14 

DM_A15 

DM_D15 

DM_D16 

DM_BA0 

DM_D17 

DM_BA0 

DM_BA1 

DM_D18 

DM_BA1 

DM_BA2 

DM_D19 

DM_BA2 

DM_D20 

DM_DQM0 

DM_D21 

DM_DQM1 

DM_D22 

DM_DQM2 

DM_D23 

DM_DQM3 

DM_D24 

DM_D25 

DM_CLK0_DL 

DM_D26 

DM_CLK0_DL 

DM_CLK0_DH 

DM_D27 

DM_CLK0_DH 

DM_CKE0 

DM_D28 

DM_CKE0 

DM_D29 

DM_CLK1_DL 

DM_D30 

DM_CLK1_DL 

DM_CLK1_DH 

DM_D31 

DM_CLK1_DH 

DM_CKE1 

DM_CKE1 

DM_DQS0_DL 

DM_RAS_N 

DM_DQS0_DH 

DM_RAS_N 

DM_CAS_N 

DM_CAS_N 

DM_WE_N 

DM_DQS1_DL 

DM_WE_N 

DM_DQS1_DH 

DM_CS0_N 

DM_CS0_N 

DM_CS1_N_BOT 

DM_DQS2_DL 

DM_CS1_N_BOT 

DM_DQS2_DH 

DM_RESET_N 

DM_RESET_N 

DM_DQS3_DL 

DM_ODT0 

DM_DQS3_DH 

DM_ODT0 

DM_ODT1 

DM_ODT1 

NA_IO[0..15] 

NA_IO[0..15] 

AUX_3V3 

SM_VIO 

SM_3V3 

SM_1V8 

DM_POWER 

DM_DQS0_DL 

DM_DQS0_DH 

DM_DQS1_DL 

DM_DQS1_DH 

FS_VIO 

DM_DQS2_DL 

DM_DQS2_DHVref 

FS_3V3 

DM_DQS3_DL FS_1V8 

DM_DQS3_DH 

NA_1V8 

NA_3V3 

STATIC MEMORY INTERFACE 

SM_A0 

D39 

SM_A1 

SM_A0 

SM_D0 

E39 

SM_A2 

SM_A1 

D38 

SM_A3 

SM_A2 

E38 

SM_A4 

SM_A3 

D37 

SM_A5 

SM_A4 

E37 

SM_A6 

SM_A5 

D36 

SM_A7 

SM_A6 

E36 

SM_A8 

SM_A7 

D35 

SM_A9 

SM_A8 

E35 

SM_A10 

SM_A9 

D34 

SM_A11 

SM_A10 

E34 

SM_A12 

SM_A11 

D33 

SM_A13 

SM_A12 

E33 

SM_A14 

SM_A13 

D32 

SM_A15 

SM_A14 

E32 

SM_A16 

SM_A15 

D29 

SM_A17 

SM_A16 

E29 

SM_A18 

SM_A17 

D28 

SM_A19 

SM_A18 

E28 

SM_A20 

SM_A19 

D27 

SM_A21 

SM_A20 

E27 

SM_A22 

SM_A21 

D26 

SM_A23 

SM_A22 

E26 

SM_A24 

SM_A23 

D25 

SM_A25 

SM_A24 

E25 

SM_A26 

SM_A25 

D24 

SM_A27 

SM_A26 

E24 

SM_A28 

SM_A27 

D23 

SM_A29 

SM_A28 

E23 

SM_A30 

SM_A29 

D22 

SM_A31 

SM_A30 

E22 

SM_A31 

SM_BE0 

SM_BE0 

SM_BE1 

SM_BE1 

SM_BE2 

SM_BE2 

SM_BE3 

SM_BE3 

SM_CLK0 

SM_CLK0 

SM_CLK1 

SM_CLK1 

SM_CLK2 

SM_CLK2 

SM_CLK3 

SM_CLK3 

SM_CS0_N 

SM_CS0_N 

SM_CS1_N 

SM_CS1_N 

SM_CS2_N 

SM_CS2_N 

SM_CS3_N 

SM_CS3_N 

SM_WE_N 

SM_WE_N 

SM_OE_N 

SM_OE_N 

SM_LBA_N 

SM_LBA_N 

SM_WP_N 

SM_WP_N 

SM_RESET_N 

SM_RESET_N 

SM_CRE_N 

SM_CRE_N 

SM_PD_N 

SM_PD_N 

FS_SI 

FS_SI 

FS_SCK 

FS_SCK 

FS_WP_N 

FS_WP_N 

FS_RESET 

FS_RESET 

FS_CS0_N 

FS_CS0_N 

FS_CS1_N 

FS_CS1_N 

FS_CS2_N 

FS_CS2_N 

FS_CS3_N 

FS_CS3_N 

SM_D0 

SM_D1 

SM_D2 

SM_D3 

SM_D4 

SM_D5 

SM_D6 

SM_D7 

SM_D8 

SM_D9 

SM_D10 

SM_D11 

SM_D12 

SM_D13 

SM_D14 

SM_D15 

SM_D16 

SM_D17 

SM_D18 

SM_D19 

SM_D20 

SM_D21 

SM_D22 

SM_D23 

SM_D24 

SM_D25 

SM_D26 

SM_D27 

SM_D28 

SM_D29 

SM_D30 

SM_D31 

SM_BUSY_N_0 

SM_BUSY_N_1 SM_BUSY_N_0 



SM_BUSY_N_3 

SM_IRQ_N 

SM_IRQ_N 

SM_BWAIT_N 

SM_BWAIT_N 

SM_DMARQ_N 

SM_DMARQ_N 

FS_SO 

FS_HOLD_N FS_SO 

FS_HOLD_N 

D 

C 

B 

A 

NA_CLE 

NA_ALE 

NA_RE_N 

NA_WE_N 

NA_PRE 

NA_WP_N 

NA_CS0_N 

NA_CS1_N_BOT 

NA_CS2_N_BOT 

NA_CS3_N_BOT 

NA_CLE 

NA_ALE 

NA_RE_N 

NA_WE_N 

NA_PRE 

NA_WP_N 

NA_CS0_N 

NA_CS1_N_BOT 

NA_CS2_N_BOT 

NA_CS3_N_BOT 

NA_IO0 

NA_IO1 

NA_IO2 

NA_IO3 

NA_IO4 

NA_IO5 

NA_IO6 

NA_IO7 

NA_IO8 

NA_IO9 

NA_IO10 

NA_IO11 

NA_IO12 

NA_IO13 

NA_IO14 

NA_IO15 

AUX_SDA 

AUX_SCL 

AUX_SA0_BOT 

AUX_SA1_BOT 

AUX_SA2_BOT 

AUX_TDI 

AUX_TCK 

AUX_TMS 

AUX_STANDBY_N 

AUX_POR_N 

AUX_HMR_N 

AUX_SDA 

AUX_SCL 

AUX_SA0_BOT 

AUX_SA1_BOT 

AUX_SA2_BOT 

AUX_TDI 

AUX_TCK 

AUX_TMS 

AUX_STANDBY_N 

AUX_POR_N 

AUX_HMR_N 

AUX_TDO 

AUX_TDO 

Title 

BOTTOM CONNECTOR 

D o c u m e n t N u m b e r 

Micron Technology 

Systems Engineering 

via A. Pacinotti, 7 

67051, Avezzano 

ITALY 

R e v i s i o n 

Size 

A 

NA_LCK 

NA_LCK 

NA_RY0 

NA_RY1 

NA_RY2 

NA_RY3 

NA_RY0 

NA_RY1 

NA_RY2 

NA_RY3 

M I C R O N - P I S M O 2 - 0 0 0 0 1 

4 . 0 

CONFIDENTIAL AND PROPRIETARY INFORMATION 

The information contained herein is proprietary of Micron Technology. Any reproduction, in whole or in part, 

disclosure, or use of this drawing is expressly prohibited except as specified in writing by Micron Technology. 

A-3 

A39 

SM_D1 A38 

SM_D2 A37 

SM_D3 A36 

SM_D4 A35 

SM_D5 A34 

SM_D6 A33 

SM_D7 A32 

SM_D8 B39 

SM_D9 B38 

SM_D10 B37 

SM_D11 B36 

SM_D12 B35 

SM_D13 B34 

SM_D14 B33 

SM_D15 B32 

SM_D16 A29 

SM_D17 A28 

SM_D18 A27 

SM_D19 A26 

SM_D20 A25 

SM_D21 A24 

SM_D22 A23 

SM_D23 A22 

SM_D24 B29 

SM_D25 B28 

SM_D26 B27 

SM_D27 B26 

SM_D28 B25 

SM_D29 B24 

SM_D30 B23 

SM_D31 B22 

D40 

SM_BE0 

E40 

SM_BE1 

E30 

SM_BE2 

E31 

SM_BE3 

C32 

SM_CLK0 

C31 

SM_CLK1 

C30 

SM_CLK2 

C29 

SM_CLK3 

H40 

SM_CS0_N 

H39 

SM_CS1_N 

H38 

SM_CS2_N 

H37 

SM_CS3_N 

F32 

SM_WE_N 

F31 

SM_OE_N 

SM_IRQ_N 

F33 

SM_LBA_N 

H33 

SM_WP_N 

H34 

SM_RESET_N 

G38 

SM_CRE_N 

H35 

SM_PD_N 

G37 

SM_BWAIT_N F35 

SM_BUSY_N_0 

SM_DMARQ_N 

F34 

G39 

SM_BUSY_N_1 G40 


SM_BUSY_N_3 H36 

J2C 

SEAM-40-02.0-S-08-2-A-K 

FAST SERIAL 

MEMORY 

INTERFACE 

FS_SO G1 

FS_HOLD_N H2 

J2F 

SEAM-40-02.0-S-08-2-A-K 

POWER 

F13 

AUX_V33_0 

F11 

AUX 

AUX_V33_1 

G14 

AUX_V33_2 

C37 

SM_VIO_0 

C36 

SM_VIO_1 

C35 

STATIC MEMORY 

SM_VIO_2 

VSS1 

C34 

SM_VIO_3 

VSS2 

C33 

SM_VIO_4 

VSS3 

C28 

SM_VIO_5 

VSS4 

C27 

SM_VIO_6 

VSS5 

C26 

SM_VIO_7 

C25 

SM_VIO_8 

C24 

SM_V33_0 

C23 

SM_V33_1 

C22 

SM_V33_2 

C40 

SM_V18_0 

C39 

SM_V18_1 

C38 

SM_V18_2 

C19 

DM_VIO_0 

C18 

DM_VIO_1 

C14 

DM_VIO_2 

C8 

DM_VIO_3 

C12 

DM_VIO_4 

C10 

DM_VIO_5 

C9 

DYNAMIC 

DM_VIO_6 

C15 

MEMORY 

DM_VIO_7 

C11 

DM_VIO_8 

C7 

DM_VIO_9 

C20 

DM_VCC_0 

C17 

DM_VCC_1 

C16 

DM_VCC_2 

C13 

DM_VCC_3 

G5 

FS_VIO_0 

G4 

FAST SERIAL 

FS_VIO_1 

F3 

MEMORY 

FS_V33_0 

G6 

FS_V18_0 

F26 

NA_VIO_0 

F21 

NAND 

NA_VIO_1 

F16 

MEMORY 

NA_VIO_2 

F27 

NA_V33_0 

F28 

NA_V18_0 

F39 

F38 

F37 

F36 

G2 

FS_SI 

F1 

FS_SCK 

G7 

FS_WP_N 

H1 

FS_RESET_N 

H6 

FS_CS0_N 

H5 

FS_CS1_N 

H4 

FS_CS2_N 

H3 

FS_CS3_N 

G35 

VSS6 G34 

VSS7 G33 

VSS8 G32 

VSS9 B31 

VSS10 D31 

VSS11 G31 

VSS12 B30 

VSS13 D30 

VSS14 

VSS15 

VSS16 

VSS17 

VSS18 

VSS19 

VSS20 

F30 

F29 

F25 

F24 

F23 

F22 

A21 

VSS21 B21 

VSS22 C21 

VSS23 D21 

VSS24 E21 

VSS25 

VSS26 

VSS27 

VSS28 

VSS29 

VSS30 

VSS31 

F20 

F19 

F18 

F17 

F15 

F14 

D13 

VSS32 E13 

VSS33 

VSS34 

F12 

D11 

VSS35 E11 

VSS36 

VSS37 

F10 

D9 

VSS38 E9 

VSS0 

VSS39 

VSS40 

VSS41 

VSS42 

VSS43 

VSS44 

VSS45 

VSS46 

F40 

F9 

F8 

F7 

F6 

F5 

F4 

F2 

E1 

J2D 

SEAM-40-02.0-S-08-2-A-K 

NAND MEMORY 

INTERFACE 

NA_IO0 H23 

G28 

NA_CLE NA_IO1 H22 

NA_IO2 H21 

NA_IO3 H20 

NA_IO4 H19 

NA_IO5 H18 

NA_IO6 H17 

NA_IO7 H16 

NA_IO8 G23 

NA_IO9 G22 

NA_IO10 G21 

NA_IO11 G20 

NA_IO12 G19 

NA_IO13 G18 

NA_IO14 G17 

NA_IO15 G16 

NA_RY0 G25 

H28 

H25 

G29 

H24 

H29 

H27 

G27 

G26 

H26 

NA_ALE 

NA_RE_N 

NA_WE_N 

NA_PRE 

NA_WP_N 

NA_CS0_N 

NA_CS1_N 

NA_CS2_N 

NA_CS3_N 

NA_RY1 G30 

NA_RY2 H30 

NA_RY3 G15 

J2E 

SEAM-40-02.0-S-08-2-A-K 

AUX 

2-wire CONFIG 

JTAG 

AUX_TDO 

H15 

NA_LCK 

H10 

AUX_PRESENT H12 

J2G 

SEAM-40-02.0-S-08-2-A-K 

DNU 

DNU2 

G9 

G8 

H9 

H8 

H7 

G10 

G11 

H11 

H14 

G13 

H13 

AUX_SDA 

AUX_SCL 

AUX_SA0 

AUX_SA1 

AUX_SA2 

AUX_TDI 

AUX_TCK 

AUX_TMS 

AUX_STANDBY_N 

AUX_POR_N 

AUX_HMR_N 

H32 

DNU4 H31 

DNU8 G3 

DNU9 C1 

DNU0 A40 

DNU1 B40 

DNU5 A30 

DNU3 A31 

DNU6 G24 

DNU7 G12 

J2A 

SEAM-40-02.0-S-08-2-A-K 

DYNAMIC MEMORY INTERFACE 

DM_D0 B11 

DM_D1 A11 

DM_D2 B12 

DM_D3 A12 

DM_D4 B13 

DM_D5 A13 

DM_D6 A14 

DM_D7 B14 

DM_D8 A7 

DM_D9 B7 

DM_D10 A8 

DM_D11 B8 

DM_D12 A9 

DM_D13 B9 

DM_D14 B10 

DM_D15 A10 

DM_D16 A16 

DM_D17 B16 

DM_D18 B17 

DM_D19 A17 

DM_D20 B18 

DM_D21 B19 

DM_D22 A18 

DM_D23 A19 

DM_D24 B2 

DM_D25 B3 

DM_D26 A2 

DM_D27 A3 

DM_D28 B4 

DM_D29 A4 

DM_D30 A5 

DM_D31 B5 

DM_DQS0_DL B15 

DM_DQS0_DH A15 

DM_DQS1_DL B6 

DM_DQS1_DH A6 



DM_DQS3_DL B1 

DM_DQS3_DH A1 

E19 

DM_A0 

D19 

DM_A1 

E14 

DM_A2 

E20 

DM_A3 

E2 

DM_A4 

E8 

DM_A5 

E3 

DM_A6 

D3 

DM_A7 

D7 

DM_A8 

E4 

DM_A9 

D14 

DM_A10 

D4 

DM_A11 

E7 

DM_A12 

E16 

DM_A13 

D6 

DM_A14 

D2 

DM_A15 

E18 

DM_BA0 

D18 

DM_BA1 

D16 

DM_DQM0 

D8 

DM_DQM1 

D20 

DM_DQM2 

E6 

DM_DQM3 

E12 

DM_CLK0_DL 

D12 

DM_CLK0_DH 

E5 

DM_CKE0 

E10 

DM_CLK1_DL 

D10 

DM_CLK1_DH 

D5 

DM_CKE1 

D17 

DM_RAS_N 

E17 

DM_CAS_N 

D15 

DM_WE_N 

E15 

DM_CS0_N 

D1 

DM_CS1_N 

C3 

DM_RESET_N 

C5 

DM_ODT0 

C4 

DM_ODT1 

DM_VREF C6 

C2 

DM_BA2 

3 

2 

2 

Date: Tuesday, April 03, 2007 

Sheet 2 of 6 

1 

1 



Advance



Figure 8: Top Connector Schematic 

5 

5 

4 

4 

3 

SM_A[0..31] 

SM_D[0..31] 

D 

C 

DM_DQM[0..3] 

DM_DQM[0..3] 

DM_D[0..31] 

DM_D[0..31] 

DM_A[0..15] 

DM_A[0..15] 

DM_A0 

DM_D0 

DM_A1 

DM_D1 

DM_A2 

DM_D2 

DM_A3 

DM_D3 

DM_A4 

DM_D4 

DM_A5 

DM_D5 

DM_A6 

DM_D6 

DM_A7 

DM_D7 

DM_A8 

DM_D8 

DM_A9 

DM_D9 

DM_A10 

DM_D10 

DM_A11 

DM_D11 

DM_A12 

DM_D12 

DM_A13 

DM_D13 

DM_A14 

DM_D14 

DM_A15 

DM_D15 

DM_D16 

DM_BA0 

DM_D17 

DM_BA0 

DM_BA1 

DM_D18 

DM_BA1 

DM_BA2 

DM_D19 

DM_BA2 

DM_D20 

DM_DQM0 

DM_D21 

DM_DQM1 

DM_D22 

DM_DQM2 

DM_D23 

DM_DQM3 

DM_D24 

DM_D25 

DM_CLK0_DL 

DM_D26 

DM_CLK0_DL 

DM_CLK0_DH 

DM_D27 

DM_CLK0_DH 

DM_CKE0 

DM_D28 

DM_CKE0 

DM_D29 

DM_CLK1_DL 

DM_D30 

DM_CLK1_DL 

DM_CLK1_DH 

DM_D31 

DM_CLK1_DH 

DM_CKE1 

DM_CKE1 

DM_DQS0_DL 

DM_RAS_N 

DM_DQS0_DH 

DM_RAS_N 

DM_CAS_N 

DM_CAS_N 

DM_WE_N 

DM_DQS1_DL 

DM_WE_N 

DM_DQS1_DH 

DM_CS1_N_BOT 

DM_CS1_N_BOT 

DM_CS_FDBK 

DM_DQS2_DL 

DM_DQS2_DH 

DM_RESET_N 

DM_RESET_N 

DM_DQS3_DL 

DM_ODT0 

DM_DQS3_DH 

DM_ODT0 

DM_ODT1 

DM_ODT1 

J1G 

DM_POWER 

SEAF-40-05.0-S-08-2-A-K 

AUX_3V3 

SM_VIO 

SM_3V3 

SM_1V8 

DM_POWER 

DM_DQS0_DL 

DM_DQS0_DH 

FS_VIO 

DM_DQS1_DL 

DM_DQS1_DH 

FS_3V3 

DM_DQS2_DL FS_1V8 

DM_DQS2_DH 

Vref 

DM_DQS3_DL 

DM_DQS3_DH 

NA_1V8 

NA_3V3 

SM_A[0..31] 

SM_A0 

SM_A1 

SM_A2 

SM_A3 

SM_A4 

SM_A5 

SM_A6 

SM_A7 

SM_A8 

SM_A9 

SM_A10 

SM_A11 

SM_A12 

SM_A13 

SM_A14 

SM_A15 

SM_A16 

SM_A17 

SM_A18 

SM_A19 

SM_A20 

SM_A21 

SM_A22 

SM_A23 

SM_A24 

SM_A25 

SM_A26 

SM_A27 

SM_A28 

SM_A29 

SM_A30 

SM_A31 

SM_BE0 

SM_BE0 

SM_BE1 

SM_BE1 

SM_BE2 

SM_BE2 

SM_BE3 

SM_BE3 

SM_CLK0 

SM_CLK0 

SM_CLK1 

SM_CLK1 

SM_CLK2 

SM_CLK2 

SM_CLK3 

SM_CLK3 

SM_CS0_N 

SM_CS0_N 

SM_CS1_N 

SM_CS1_N 

SM_CS2_N 

SM_CS2_N 

SM_CS3_N 

SM_CS3_N 

SM_WE_N 

SM_WE_N 

SM_OE_N 

SM_OE_N 

SM_LBA_N 

SM_LBA_N 

SM_WP_N 

SM_WP_N 

SM_RESET_N 

SM_RESET_N 

SM_CRE_N 

SM_CRE_N 

SM_PD_N 

SM_PD_N 

SM_D[0..31] 

SM_D0 

SM_D1 

SM_D2 

SM_D3 

D 

SM_D4 

SM_D5 

SM_D6 

SM_D7 

SM_D8 

SM_D9 

SM_D10 

SM_D11 

SM_D12 

SM_D13 

SM_D14 

SM_D15 

SM_D16 

SM_D17 

SM_D18 

SM_D19 

SM_D20 

SM_D21 

SM_D22 

SM_D23 

SM_D24 

SM_D25 

SM_D26 

SM_D27 

SM_D28 

SM_D29 

SM_D30 

SM_D31 

C 

SM_BUSY_N_0 




SM_BUSY_N_3 

SM_IRQ_N 

SM_IRQ_N 

SM_BWAIT_N 

SM_BWAIT_N 

SM_DMARQ_N 

SM_DMARQ_N 

B DNU 

DNI 

DM_CS_FDBK 

B 

A 

NA_1V8 

DNI 

NA_CS0_N 

DNU0 

NA_CLE 

NA_ALE 

NA_RE_N 

NA_WE_N 

NA_PRE 

NA_WP_N 

NA_CS1_N_BOT 

NA_CS2_N_BOT 

NA_CS3_N_BOT 

NA_LCK 

DM_CS0_N 

NA_IO[0..15] 

NA_CLE 

NA_ALE 

NA_RE_N 

NA_WE_N 

NA_PRE 

NA_WP_N 

NA_LCK 

NA_IO[0..15] 

NA_IO0 

NA_IO1 

NA_IO2 

NA_IO3 

NA_IO4 

NA_IO5 

NA_IO6 

NA_IO7 

NA_IO8 

NA_IO9 

NA_IO10 

NA_IO11 

NA_IO12 

NA_IO13 

NA_IO14 

NA_IO15 

NA_RY0 

NA_RY1 

NA_RY2 

NA_RY3 

NA_RY0 

NA_RY1 

NA_RY2 

NA_RY3 

AUX_3V3 

AUX_SDA 

AUX_SCL 

AUX_SA0_BOT 

AUX_SA1_BOT 

AUX_TDI 

AUX_TCK 

AUX_TMS 

AUX_STANDBY_N 

AUX_POR_N 

AUX_HMR_N 

AUX_SDA 

AUX_SCL 

AUX_TDI 

AUX_TCK 

AUX_TMS 

AUX_STANDBY_N 

AUX_POR_N 

AUX_HMR_N 

FS_SI 

FS_SCK 

FS_WP_N 

FS_RESET 

FS_CS0_N 

FS_CS1_N 

FS_CS2_N 

FS_CS3_N 

AUX_TDO 

FS_SI 

FS_SCK 

FS_WP_N 

FS_RESET 

FS_CS0_N 

FS_CS1_N 

FS_CS2_N 

FS_CS3_N 

AUX_TDO 

FS_SO 

FS_HOLD_N FS_SO 

FS_HOLD_N 





ITALY 

A 

Title 

TOP CONNECTOR 



Size 

M I C R O N - P I S M O 2 - 0 0 0 0 1 

4 . 0 

A-3 




A40 

DNU1 B40 

DNU2 H32 

DNU3 A31 

DNU4 H31 

DNU5 A30 

DNU6 G24 

DNU7 G12 

DNU8 G3 

DNU9 C1 

J1E 

SEAF-40-05.0-S-08-2-A-K 

AUX 

2-wire CONFIG 

JTAG 

AUX_TDO H10 

AUX_PRESENT H12 

J1A 

SEAF-40-05.0-S-08-2-A-K 

DYNAMIC MEMORY INTERFACE 

DM_DQS0_DL 

DM_POWER 

TP4 

G9 

AUX_SDA 

G8 

AUX_SCL 

H9 

AUX_SA0 

H8 

AUX_SA1 

H7 

AUX_SA2 

G10 

AUX_TDI 

G11 

AUX_TCK 

H11 

AUX_TMS 

H14 

AUX_STANDBY_N 

G13 

AUX_POR_N 

H13 

AUX_HMR_N 

B15 


DM_DQS1_DL B6 

DM_DQS1_DH A6 



DM_DQS3_DL B1 

DM_DQS3_DH A1 

E15 

DM_CS0_N 

D1 

DM_CS1_N 

C3 

DM_RESET_N 

C5 

DM_ODT0 

C4 

DM_ODT1 

DM_VREF C6 

DM_D0 B11 

DM_D1 A11 

DM_D2 B12 

DM_D3 A12 

DM_D4 B13 

DM_D5 A13 

DM_D6 A14 

DM_D7 B14 

DM_D8 A7 

DM_D9 B7 

DM_D10 A8 

DM_D11 B8 

DM_D12 A9 

DM_D13 B9 

DM_D14 B10 

DM_D15 A10 

DM_D16 A16 

DM_D17 B16 

DM_D18 B17 

DM_D19 A17 

DM_D20 B18 

DM_D21 B19 

DM_D22 A18 

DM_D23 A19 

DM_D24 B2 

DM_D25 B3 

DM_D26 A2 

DM_D27 A3 

DM_D28 B4 

DM_D29 A4 

DM_D30 A5 

DM_D31 B5 

J1F 

SEAF-40-05.0-S-08-2-A-K 

E19 

DM_A0 

D19 

DM_A1 

E14 

DM_A2 

E20 

DM_A3 

E2 

DM_A4 

E8 

DM_A5 

E3 

DM_A6 

D3 

DM_A7 

D7 

DM_A8 

E4 

DM_A9 

D14 

DM_A10 

D4 

DM_A11 

E7 

DM_A12 

E16 

DM_A13 

D6 

DM_A14 

D2 

DM_A15 

E18 

DM_BA0 

D18 

DM_BA1 

C2 

DM_BA2 

D16 

DM_DQM0 

D8 

DM_DQM1 

D20 

DM_DQM2 

E6 

DM_DQM3 

E12 

DM_CLK0_DL 

D12 

DM_CLK0_DH 

E5 

DM_CKE0 

E10 

DM_CLK1_DL 

D10 

DM_CLK1_DH 

D5 

DM_CKE1 

D17 

DM_RAS_N 

E17 

DM_CAS_N 

D15 

DM_WE_N 

C24 + 

10U 

POWER 

AUX 

STATIC MEMORY 

VSS1 

VSS2 

VSS3 

VSS4 

VSS5 

DYNAMIC 

MEMORY 

FAST SERIAL 

MEMORY 

NAND 

MEMORY 

F39 

F38 

F37 

F36 

R11 0 

R12 0 

G35 

VSS6 G34 

VSS7 G33 

VSS8 G32 

VSS9 B31 

VSS10 D31 

VSS11 G31 

VSS12 B30 

VSS13 D30 

VSS14 

VSS15 

VSS16 

VSS17 

VSS18 

VSS19 

VSS20 

F30 

F29 

F25 

F24 

F23 

F22 

A21 

VSS21 B21 

VSS22 C21 

VSS23 D21 

VSS24 E21 

VSS25 

VSS26 

VSS27 

VSS28 

VSS29 

VSS30 

VSS31 

F20 

F19 

F18 

F17 

F15 

F14 

D13 

VSS32 E13 

VSS33 

VSS34 

F12 

D11 

VSS35 E11 

VSS36 

VSS37 

F10 

D9 

VSS38 E9 

VSS39 

VSS40 

VSS41 

VSS42 

VSS43 

VSS44 

VSS45 

VSS46 

F9 

F8 

F7 

F6 

F5 

F4 

F2 

E1 

C22 + 

10u 

NA_1V8 

TP1 

F13 

F11 

G14 

C37 

C36 

C35 

C34 

C33 

C28 

C27 

C26 

C25 

C24 

C23 

C22 

C40 

C39 

C38 

C19 

C18 

C14 

C8 

C12 

C10 

C9 

C15 

C11 

C7 

C20 

C17 

C16 

C13 

G5 

G4 

F3 

G6 

F26 

F21 

F16 

F27 

F28 

AUX_V33_0 

AUX_V33_1 

AUX_V33_2 

SM_VIO_0 

SM_VIO_1 

SM_VIO_2 

SM_VIO_3 

SM_VIO_4 

SM_VIO_5 

SM_VIO_6 

SM_VIO_7 

SM_VIO_8 

SM_V33_0 

SM_V33_1 

SM_V33_2 

SM_V18_0 

SM_V18_1 

SM_V18_2 

DM_VIO_0 

DM_VIO_1 

DM_VIO_2 

DM_VIO_3 

DM_VIO_4 

DM_VIO_5 

DM_VIO_6 

DM_VIO_7 

DM_VIO_8 

DM_VIO_9 

DM_VCC_0 

DM_VCC_1 

DM_VCC_2 

DM_VCC_3 

FS_VIO_0 

FS_VIO_1 

FS_V33_0 

FS_V18_0 

NA_VIO_0 

NA_VIO_1 

NA_VIO_2 

NA_V33_0 

NA_V18_0 

VSS0 

F40 

GND 

J1D 

SEAF-40-05.0-S-08-2-A-K 

NAND MEMORY 

INTERFACE 

NA_RY0 

TP7 

G25 

NA_IO0 H23 

NA_IO1 H22 

NA_IO2 H21 

NA_IO3 H20 

NA_IO4 H19 

NA_IO5 H18 

NA_IO6 H17 

NA_IO7 H16 

NA_IO8 G23 

NA_IO9 G22 

NA_IO10 G21 

NA_IO11 G20 

NA_IO12 G19 

NA_IO13 G18 

NA_IO14 G17 

NA_IO15 G16 

G28 

NA_CLE 

H28 

NA_ALE 

H25 

NA_RE_N 

G29 

NA_WE_N 

H24 

NA_PRE 

H29 

NA_WP_N 

H27 

NA_CS0_N 

G27 

NA_CS1_N 

G26 

NA_CS2_N 

H26 

NA_CS3_N 

NA_RY1 G30 

NA_RY2 H30 

NA_RY3 G15 

J1C 

H15 

NA_LCK 

SEAF-40-05.0-S-08-2-A-K 

FAST SERIAL 

MEMORY 

INTERFACE 

G2 

FS_SI 

F1 

FS_SCK FS_HOLD_N 

G7 

FS_WP_N 

H1 

FS_RESET_N 

H6 

FS_CS0_N 

H5 

FS_CS1_N 

H4 

FS_CS2_N 

H3 

FS_CS3_N 

H2 

FS_SO G1 

J1B 

SEAF-40-05.0-S-08-2-A-K 

STATIC MEMORY INTERFACE 

D40 

SM_BE0 

E40 

SM_BE1 

E30 

SM_BE2 

E31 

SM_BE3 

C32 

SM_CLK0 

C31 

SM_CLK1 

C30 

SM_CLK2 

C29 

SM_CLK3 

H40 

SM_CS0_N 

H39 

SM_CS1_N 

H38 

SM_CS2_N 

H37 

SM_CS3_N 

F32 

SM_WE_N 

F31 

SM_OE_N 

SM_IRQ_N 

F33 

SM_LBA_N 

H33 

SM_WP_N 

H34 

SM_RESET_N 

G38 

SM_CRE_N 

H35 

SM_PD_N 

R9 0 

R10 0 

G37 

SM_BWAIT_N F35 

SM_DMARQ_N G39 

D39 

SM_A0 

SM_D0 

E39 

SM_A1 

D38 

SM_A2 

E38 

SM_A3 

D37 

SM_A4 

E37 

SM_A5 

D36 

SM_A6 

E36 

SM_A7 

D35 

SM_A8 

E35 

SM_A9 

D34 

SM_A10 

E34 

SM_A11 

D33 

SM_A12 

E33 

SM_A13 

D32 

SM_A14 

E32 

SM_A15 

D29 

SM_A16 

E29 

SM_A17 

D28 

SM_A18 

E28 

SM_A19 

D27 

SM_A20 

E27 

SM_A21 

D26 

SM_A22 

E26 

SM_A23 

D25 

SM_A24 

E25 

SM_A25 

D24 

SM_A26 

E24 

SM_A27 

D23 

SM_A28 

E23 

SM_A29 

D22 

SM_A30 

E22 

SM_A31 

A39 

SM_D1 A38 

SM_D2 A37 

SM_D3 A36 

SM_D4 A35 

SM_D5 A34 

SM_D6 A33 

SM_D7 A32 

SM_D8 B39 

SM_D9 B38 

SM_D10 B37 

SM_D11 B36 

SM_D12 B35 

SM_D13 B34 

SM_D14 B33 

SM_D15 B32 

SM_D16 A29 

SM_D17 A28 

SM_D18 A27 

SM_D19 A26 

SM_D20 A25 

SM_D21 A24 

SM_D22 A23 

SM_D23 A22 

SM_D24 B29 

SM_D25 B28 

SM_D26 B27 

SM_D27 B26 

SM_D28 B25 

SM_D29 B24 

SM_D30 B23 

SM_D31 B22 

SM_BUSY_N_0 

SM_BUSY_N_1 

F34 

G40 


SM_BUSY_N_3 H36 

+ C23 

10u 

3 

2 

2 



1 

1 



Advance



Figure 9: Mobile DDR DRAM Interface Schematic 

DM_D[0..31] 

5 

5 

4 

4 

3 

DM_A[0..15] 

DM_A[0..15] 

D D 

TERM_DM_DQS2_DH R21 33 DM_DQS2_DH 

DM_DQS2_DH 

U3 

C 

TERM_DM_D23 

TERM_DM_D21 

TERM_DM_D22 

TERM_DM_D20 

TERM_DM_D19 

TERM_DM_D18 

TERM_DM_D16 

TERM_DM_D17 

TERM_DM_DQS0_DH 

TERM_DM_D7 

TERM_DM_D6 

TERM_DM_D5 

TERM_DM_D4 

TERM_DM_D3 

TERM_DM_D2 

TERM_DM_D1 

TERM_DM_D0 

RN7 

8 1 

7 2 

6 3 

5 4 

33 

R14 33 

RN5 

8 1 

7 2 

6 3 

5 4 

DM_D23 

DM_D21 

DM_D22 

DM_D20 

DM_D19 

DM_D18 

DM_D16 

DM_D17 

DM_DQS0_DH 

DM_DQS0_DH 

DM_D7 

DM_D6 

DM_D5 

DM_D4 

DM_D3 

DM_D2 

DM_D1 

DM_D0 

DM_DQM[0..3] 

DM_DQM[0..3] 

DM_A0 

DM_A1 

DM_A2 

DM_A3 

DM_A4 

DM_A5 

DM_A6 

DM_A7 

DM_A8 

DM_A9 

DM_A10 

DM_A11 

DM_A12 

DM_A13 

DM_BA0 

DM_BA1 

DM_DQM0 

DM_DQM1 

DM_DQM2 

DM_DQM3 





DM_CAS_N 

DM_RAS_N 

DM_WE_N 

DM_CS0_N 

DM_CKE0 

DM_CLK0_DH 

C29 

0402 

J8 

J9 

K7 

K9 

K1 

K3 

J1 

J2 

J3 

H1 

J7 

H2 

H3 

H8 

H9 

K2 

G8 

A0 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10/AP 

A11 

NC/A12 

BA0 

BA1 

DM1 

CAS 

MT46HXXM32LF 

TERM_DM_D0 

TERM_DM_D1 

TERM_DM_D2 

TERM_DM_D3 

TERM_DM_D4 

TERM_DM_D5 

TERM_DM_D6 

TERM_DM_D7 

TERM_DM_D8 

TERM_DM_D9 

TERM_DM_D10 

TERM_DM_D11 

TERM_DM_D12 

TERM_DM_D13 

TERM_DM_D14 

TERM_DM_D15 

TERM_DM_D16 

TERM_DM_D17 

TERM_DM_D18 

TERM_DM_D19 

TERM_DM_D20 

TERM_DM_D21 

TERM_DM_D22 

TERM_DM_D23 

TERM_DM_D24 

TERM_DM_D25 

TERM_DM_D26 

TERM_DM_D27 

TERM_DM_D28 

TERM_DM_D29 

TERM_DM_D30 

TERM_DM_D31 

C 

33 

1n 0402 

0402 

TERM_DM_D15 

TERM_DM_D14 

TERM_DM_D12 

TERM_DM_D13 

DM_D15 

DM_D14 

DM_D12 

DM_D13 

DM_CLK0_DL 

DM0 

K8 

G7 

WE 

DQ0 R8 

DQ1 P7 

DQ2 P8 

DQ3 N7 

DQ4 N8 

DQ5 M7 

DQ6 M8 

DQ7 

DQ8 

DQ9 

L7 

L3 

M2 

DQ10 M3 

DQ11 N2 

DQ12 N3 

DQ13 P2 

DQ14 P3 

DQ15 R2 

F7 

G9 

H7 

G1 

G2 

G3 

NC/A13 

RAS 

CS 

CKE 

CLK 

CLK 

DQ29 B2 

DQ16 A8 

DQ17 B7 

DQ18 B8 

DQ19 C7 

DQ20 C8 

DQ21 D7 

DQ22 D8 

DQ23 E7 

DQ24 E3 

DQ25 D2 

DQ26 D3 

DQ27 C2 

DQ28 C3 

DQ30 B3 

DQ31 A2 

F8 

F2 

E2 

DM2 

DM3 

DQS3 

DQS2 

E8 DQS1 

L2 DQS0 

RN8 

8 1 

7 2 

6 3 

5 4 

33 

RN6 

8 1 

7 2 

6 3 

5 4 

33 

R3 

49.9 

L8 

R6 

49.9 

RN4 

8 

7 

6 

5 

1 

2 

3 

4 

B TERM_DM_D11 

TERM_DM_D10 

TERM_DM_D9 

TERM_DM_D8 

RN3 

8 1 

7 2 

6 3 

5 4 

33 

DM_D11 

DM_D10 

DM_D9 

DM_D8 

DM_CS0_N 

DM_WE_N 

DM_CAS_N 

DM_CS0_N 

DM_WE_N 

DM_CAS_N 

B 

DM_RAS_N 

DM_RAS_N 


TERM_DM_D30 

TERM_DM_D31 

TERM_DM_D29 

TERM_DM_D28 

TERM_DM_D27 

TERM_DM_D25 

TERM_DM_D26 

TERM_DM_D24 

33 

R8 33 

RN2 

8 

7 

6 

33 

RN1 

8 

7 

6 

1 

2 

3 

5 4 

1 

2 

3 

5 4 

DM_DQS1_DH 

DM_D30 

DM_D31 

DM_D29 

DM_D28 

DM_D27 

DM_D25 

DM_D26 

DM_D24 

DM_DQS1_DH 

DM_POWER 

C31 

100n 

DM_POWER 

C30 

100n 

C32 

100n 

C33 

100n 

A 

33 

Title 

A 

C25 C21 C26 C27 C19 C20 C18 C2 C17 C28 C15 C16 

100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 

MOBILE DDR 

TERM_DM_DQS3_DH R7 33 DM_DQS3_DH 

DM_DQS3_DH 


M I C R O N - P I S M O 2 - 0 0 0 0 1 


4 . 0 

Size 

A-3 

3 

C5 

100n 

Package 0306 

C6 

100n 

C4 

100n 

C1 

100n 

C3 

100n 

DM_POWER 

C34 

100n 

VddQ_c C9 

VddQ_d D1 

VddQ_b B1 

VddQ_a A7 

VddQ_e E9 

VddQ_f 

L9 

VddQ_g M1 

VddQ_h N9 

VddQ_m P1 

VddQ_n R7 

128/512 Mb Mobile DDR 

4/16Mx32- VFBGA 

VssQ_a 

VssQ_b 

VssQ_c 

VssQ_d 

VssQ_e 

VssQ_f 

VssQ_g 

VssQ_h 

VssQ_m 

VssQ_n 

A3 

B9 

C1 

D9 

E1 

L1 

M9 

N1 

P9 

R3 

C13 

100n 

2 

C14 

100n 

2 

Vdd_a A9 

Vdd_b 

F1 

Vdd_c R9 

Vss_a 

Vss_b 

Vss_c 

A1 

F9 

R1 

NC 

F3 

DM_CKE0 

DM_CLK0_DL 

DM_CLK0_DH 

DM_BA0 

DM_BA1 


1 

DM_CKE0 

DM_CLK0_DL 

DM_CLK0_DH 

DM_BA0 

DM_BA1 





ITALY 





1 



Advance



Figure 10: NAND Flash Interface Schematic 

5 

5 

NA_1V8 

4 

4 

3 

100n 100n 100n 

100n 100n 100n 

100n 100n 100n 100n 100n 100n 

D D 

U10 

NA_IO[0..15] 

NA_IO[0..15] 

C 

NA_CS0_N 

NAND_WP 

NA_RY0 

NA_CLE 

NA_ALE 

NA_RE_N 

NA_WE_N 

LCK 

NA_IO0 

NA_IO1 

NA_IO2 

NA_IO3 

NA_IO4 

NA_IO5 

NA_IO6 

NA_IO7 

NA_IO[0..15] 

NA_IO[0..15] 

NA_CS0_N 

NAND_WP 

NA_RY0 

NA_CLE 

NA_ALE 

NA_RE_N 

NA_WE_N 

LCK 

C6 

C3 

C8 

D5 

C4 

D4 

C7 

G5 

CE 

WP 

R/B 

CLE 

ALE 

RE 

WE 

LOCK 

NA_IO0 

NA_IO1 

NA_IO2 

NA_IO3 

NA_IO4 

NA_IO5 

NA_IO6 

NA_IO7 

NA_IO8 

NA_IO9 

NA_IO10 

NA_IO11 

NA_IO12 

NA_IO13 

NA_IO14 

NA_IO15 

C 

A1 

B9 

B10 

D3 

D6 

E3 

E4 

E5 

NC_0 

NC_5 

NC_6 

NC_7 

NC_8 

NC_11 

NC_12 

NC_13 

NC_24 

NA_1V8 

MT29F1G16AB 

B B 

G4 

NC_23 G3 

B1 

NC_4 

NC_21 

NC_22 

F7 

F8 

NC_3 

A10 NC_2 

A9 NC_1 

I/O7 

A2 

G7 

I/O5 

I/O6 

J7 

G6 

I/O4 K6 

E8 

NC_16 

NC_15 

I/O2 

I/O3 

J5 

D7 

D8 

E6 

E7 

NC_9 

NC_10 

NC_14 

K4 

I/O1 H4 

I/O0 

I/O8 

J3 

NC_17 

NC_18 

NC_19 

NC_20 

F3 

F4 

F5 

F6 

H3 

I/O9 

I/O10 

J4 

H5 

I/O11 K5 

I/O12 H6 

I/O13 K7 

I/O14 H7 

I/O15 

J8 

NC_26 G8 

NC_27 

NC_28 

NC_29 

NC_30 

NC_31 

L1 

L2 

L9 

L10 

M1 

NC_32 M2 

NC_33 M9 

NC_34 M10 

U11 

I/O0 

MT29F1G08AB 

R23 

1k 

H4 

I/O1 

I/O2 

J4 

K4 

I/O3 K5 

I/O4 K6 

I/O5 

I/O6 

J7 

K7 

I/O7 

J8 

NC_27 G8 

NC_28 H3 

NC_29 H5 

NC_30 H6 

NC_31 H7 

F4 

F5 

F6 

NC_18 

NC_19 

NC_20 

NC_21 

NC_22 

NC_23 

NC_32 

NC_33 

F7 

F8 

J3 

J5 

G3 

NC_24 G4 

NC_25 G6 

NC_26 G7 

NC_34 

NC_35 

NC_36 

NC_37 

NC_38 

L1 

L2 

L9 

L10 

M1 

NC_39 M2 

NC_40 M9 

NC_41 M10 

C6 

C3 

C8 

D5 

C4 

D4 

C7 

G5 

CE 

WP 

R/B 

CLE 

ALE 

RE 

WE 

LOCK 

A1 

A2 

A9 

A10 

B1 

B9 

B10 

D3 

D6 

D7 

D8 

E3 

E4 

E5 

E6 

E7 

E8 

F3 

NC_0 

NC_1 

NC_2 

NC_3 

NC_4 

NC_5 

NC_6 

NC_7 

NC_8 

NC_9 

NC_10 

NC_11 

NC_12 

NC_13 

NC_14 

NC_15 

NC_16 

NC_17 

J5 

HE-142 1 

2 

Place on the 

top side 

C44 

LCK 

C43 

Package 0306 Package 0306 

C45 C46 C47 C48 

C38 C37 C39 C40 

NA_1V8 

NA_1V8 

R15 

NA_LCK 

NA_CS0_N 

NA_LCK 

NA_CS0_N 

R22 0 

DNI 

1k 

NA_RY0 

NA_CLE 

NA_CLE 

NA_RY0 



NA_ALE 

NA_ALE 



A 

NA_RE_N 

NA_WE_N 

NA_RE_N 

NA_WE_N 

R16 

DNI 

1k 

Title 

ITALY 

A 

NA_WP_N 

NA_WP_N 

R18 0 

NAND_WP 

NAND 

R17 

DNI 


M I C R O N - P I S M O 2 - 0 0 0 0 1 


4 . 0 

Size 

A-3 

1k 

Vcc_1 

J6 

Vcc_2 H8 

FLASH NAND x8 - BGA 

Vss_1 

Vss_2 

Vss_3 

K8 

C5 

K3 

3 

NA_1V8 

2 

2 

NA_1V8 

Vcc_2 H8 

Vcc_1 

J6 

1.8V NAND x16 - BGA 

Vss_1 

Vss_2 

Vss_3 

K8 

C5 

K3 

C41 

C42 






1 

1 



Advance



Figure 11: EEPROM Interface Schematic 

5 

5 

4 

4 

3 

D D 

SERIAL MEMORY (PD) 

C DNI 

R19 

R20 

C 

0 

0 

0805 

0805 

AUX_SA0_BOT 

AUX_SA1_BOT 

AUX_SA2_BOT 

AUX_SA0_BOT 

AUX_SA1_BOT 

AUX_SA2_BOT 

U9 

1 

A0 

2 

A1 

3 

A2 

4 

VSS 

VCC 8 

WP 7 

SCL 

6 

SDA 5 

24xx64-I/ST 

AUX_SCL 

AUX_SDA 

C35 

100n 

AUX_3V3 NA_1V8 

AUX_SCL 

AUX_SDA 

C36 

100n 

B B 





ITALY 

A A 

Title 

3 

2 

2 

EEPROM 


M I C R O N - P I S M O 2 - 0 0 0 0 1 


1 

1 


4 . 0 





Size 

A-3 



Advance

Appendix A 

Figure 12: PISMO2-00001 Part Number Diagram 

Micron Module 

Part Number 

Table 9: Reference Documents 

Advance 


Appendix A 

Mobile DDR SDRAM Density 

D28 = 128Mb 

D56 = 256Mb 

D12 = 512Mb 

D10 = 1Gb 

Mobile DDR SDRAM Cycle Timing 

C06 = 6ns @ CAS latency = 3 

C75 = 7.5ns @ CAS latency = 3 

PISMO2-00001-D12-C75-N1-X8-B 

Document Description Manufacturer Part Numbers 

PISMO2 specification – – 

1Gb NAND Flash data sheet Micron MT29F1G8AB MT29F1G16AB 

128Mb Mobile DDR SDRAM data sheet Micron MT46H4M32LF 



PISMO2-P6960 LSA adapter data sheet Micron PISMO2-P6960 

Serial EEPROM data sheet Microchip 24AA64-I/ST I2C 

Notes: 1. Micron data sheets can be downloaded from www.micron.com. 

Operating Temperature Range 

Blank = Commercial (0° to +70°C) 

IT = Industrial/Extended (–40° to +85°C) 

NAND Package 

B = 63-ball VFBGA 

NAND Bus Width 

x8 = 8-bit 

x16 = 16-bit 

NAND Density 

N1 = 1Gb 

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective 

owners. 

Advance: This data sheet contains initial descriptions of products still under development.

Micron ® PISMO ™ Module Data Sheet

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