A 90 nm Communication Technology Featuring SiGe HBT ...

A 90 nm Communication Technology
Featuring SiGe HBT Transistors,
RF CMOS, Precision R-L-C R C RF
Elements and 1 mm 2 6-T T SRAM Cell
K. Kuhn, M. Agostinelli, , S. Ahmed, S. Chambers, S. Cea, , S. Christensen,
P. Fischer, J. Gong, C. Kardas, , T. Letson, , L. Henning, A. Murthy, , H.
Muthali, , B. Obradovic, , P. Packan, , S. W. Pae, , I. Post, S. Putna, , K. Raol, , A.
Roskowski, , R. Soman, , T. Thomas, P. Vandervoorn, , M. Weiss and I. Young
Logic Technology Development
Intel Corporation, Hillsboro, OR 97124, USA
IEDM 2002 1

Outline
• Technology Features
• CMOS
• SiGe:C HBT
• Isolation
• Passives
• Validation Vehicles
• Conclusions
IEDM 2002 2

Baseline CMOS
• Shallow Trench Isolation
• CMOS Well Implants
• Thin gate and poly
• Tip implants
• Spacer Formation
• NSD/PSD
• Silicide & contacts
• Metal 1 - 6 Layers
• Metal 7
Integration
Communications
• High resistivity substrate
• Triple Well (deep n-well)
• LP CMOS 15Å (1.2V)
• Analog CMOS 50Å (2.5V)
• SiGe HBT module
• Poly Resistor
• MIM Capacitor / TF resistor
• Inductors
IEDM 2002 3

Matching Circuit Needs to Device Type
VHS differential
RF power amp
Low-noise amp
Mixer
Op amp
Limiting amp
Switch cap filter
ADC/DAC
Bandgap ref
MUX/DeMUX
VCO
Logic MOS
Analog MOS
?
Precision R
Precision C
Logic and analog MOS are the foundation for the majority of
critical communications circuits
IEDM 2002 4
High-Q L
Varactors
LN BJT
HF BJT
HV BJT
III-V FET
III-V HBT

Matching Circuit Needs to Device Type
VHS differential
RF power amp
Low-noise amp
Mixer
Op amp
Limiting amp
Switch cap filter
ADC/DAC
Bandgap ref
MUX/DeMUX
VCO
Logic MOS
Analog MOS
?
Precision R
Precision C
IEDM 2002 5
High-Q L
Varactors
LN BJT
HF BJT
HV BJT
III-V FET
Precision single elements are key to many circuits
III-V HBT

Matching Circuit Needs to Device Type
VHS differential
RF power amp
Low-noise amp
Mixer
Op amp
Limiting amp
Switch cap filter
ADC/DAC
Bandgap ref
MUX/DeMUX
VCO
Logic MOS
Analog MOS
?
Precision R
Precision C
Most circuits have multiple implementation paths,
redundancy is important in process definition
IEDM 2002 6
High-Q L
Varactors
LN BJT
?
?
?
HF BJT
?
HV BJT
III-V FET
III-V HBT

Matching Circuit Needs to Device Type
VHS differential
RF power amp
Low-noise amp
Mixer
Op amp
Limiting amp
Switch cap filter
ADC/DAC
Bandgap ref
MUX/DeMUX
VCO
Logic MOS
Analog MOS
?
Precision R
Precision C
Specialized BJT devices cover gaps
where MOS falls short
IEDM 2002 7
High-Q L
Varactors
LN BJT
?
?
?
HF BJT
?
HV BJT
III-V FET
III-V HBT

Outline
• Technology Features
• CMOS
IEDM 2002 8

90nm CMOS
Performance versus Low Power
10000
IOFF (nA/mm)
1000
100
10
1
0.1
Performance
Devices
Low Power
Devices
0.01
0.5 1.5 2.5 3.5
CV/I (Gate delay in pS)
IEDM 2002 9

FREQUENCY (GHz)
90nm Communications CMOS
RF Performance (Low Power Device)
240
200
160
120
NMOS
F T
F MAX
0 0.5 1 1.5
FREQUENCY (GHz)
PMOS
120
100
F T
80
F MAX
60
0 0.5 1
IDSAT (mA/mm)
IDSAT (mA/mm)
NMOS: 225/143 F T /F
PMOS: 114/70 F T /F
(Vg=0.7V, Vds=1.2V)
/F MAX
/F MAX
IEDM 2002 10

F T : Intrinsic NMOS Performance
FT (GHz)
(CUT-OFF FREQUENCY)
500
200
100
50
20
[6]
[3]
[1]
This work
[4]
[2]
10
0.02 0.05 0.1 0.2 0.5 1.0
L GATE (mm)
IEDM 2002 11

F T : Intrinsic PMOS Performance
500
FT (GHz)
(CUT-OFF FREQUENCY)
200
100
50
20
[8]
[7]
This work
[6]
10
0.02 0.05 0.1 0.2 0.5 1.0
L GATE (mm)
IEDM 2002 12

Fmax: : Layout
• Make R G small
Two-sided gates
Minimize field extension
Contacts close to devices
Multiple fingers
• Minimize pad coupling
HiRES substrates
Isolate/shield signal pads
Use higher-level metal
• Minimize cap/scatter
Isolate gate from drain
Taper source bus
Similar to: L. F. Tiemeijer, et al.
“A record high 150 GHz fmax
realized at 0.18 um gate length
in an industrial RF-CMOS
technology,” IEDM 2001.
IEDM 2002 13

Comparison of CMOS: F T and F MAX
FMAX (GHz)
(MAX OSC. FREQUENCY)
250
200
150
100
50
0
[1]
[2] This work
[3]
[4]
[5]
0 100 200 300
F T (GHz)
(CUT-OFF FREQUENCY)
IEDM 2002 14

Outline
• Technology Features
• CMOS
• SiGe:C HBT
IEDM 2002 15

Criteria for BJT device definition
• Manufacturing simplicity
• Maximum leverage of the main 90nm
microprocessor process (all tools shared,
no special tools)
• Meets the needs of the circuit design
community
• No impact to CMOS performance
IEDM 2002 16

SiGe:C HBT Architecture
Extrinsic base implant
2
1
Emitter poly
B
a.
E
SiGe
C
Quasi-
Self-aligned
B
b.
1
Replacement emitter
pedestal
Spacer
Fully
Self-aligned
Quasi-self-aligned chosen as the better tradeoff
between manufacturing complexity and performance
IEDM 2002 17

HBT: SiGe:C
Epitaxy
B
Ge
E
C
B
0 20 40 60 80
Depth (nanometers)
G.L. Patton, et al. “SiGe-base heterojunction bipolar transistors: physics and
design issues,” Electron Devices Meeting, 1990.
L.D. Lanzerotti et al. “Suppression of boron outdiffusion in SiGe HBTs by
carbon incorporation,” Electron Devices Meeting, 1996
H.J. Osten, et al. “The effect of carbon incorporation on SiGe heterobipolar
transistor performance and process margin,” Electron Devices Meeting, 1997.
IEDM 2002 18

Baseline: 130/100 F T /F
/F MAX
H21 and Mason’s gain (dB)
50
40
30
H21
20
Mason’s gain
10
-20dB/dec
0
0.1 1 10 100 1000
FREQUENCY (GHz)
Cum Prob %
95%
90%
80%
70%
50%
30%
20%
10%
5%
80
100
OJ
MH
NI
GF
EB
DC
PA
HO
JM
IG
NP
FE
BD
CA
HHHH I
III
AAAAA
HI GO OOOOOOO HHH III J JJJJJJJ GGGGGGG M MMMMMMM AB BBBBBBB N NNNNNNN PE PPPPPPP EEEEEEE DF C DDDDDDD AA FFFFFFF CCCCCCC
GO
IH
JM
NA
BP
EC
DF
HI
OJ
MN
BC
F
120
140
300 mm BASELINE LOT, WIW and
WTW F T VARIATION (GHz)
IEDM 2002 19

No CMOS Degradation
IOFF [LOG (nA/ /µM)]
-4.0
-4.5
-5.0
-5.5
-6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
NMOS WITH HBT
POR NMOS
-6.0
0.60 0.80 1.00 1.20 1.40 -7.0
1.60
IDSAT [mA/µm]
IOFF [LOG (nA/ /µM)]
-4.0
-5.0
-8.0
-9.0
-10.0
-11.0
-12.0
-0.15
-0.25
•NMOS and PMOS
I ON versus I OFF
characteristics are
not degraded by
HBT integration
PMOS WITH HBT
POR PMOS
-0.35
-0.45
IDSAT [mA/µm]
-0.55
-0.65
IEDM 2002 20

BJT Yield issues: impact of volume
Incoming to EPI
OLD Process
Start of epi dep
NEW Process
Start of epi dep
Increased wafer
volume generated
Ge deposits on
chamber walls:
Fixed with purges
and pre-coats
OLD Process
After epi dep
NEW Process
After epi dep
IEDM 2002 21

Outline
• Technology Features
• CMOS
• SiGe:C HBT
• Isolation
IEDM 2002 22

Isolation: P-P
versus P+ epi (with DNW)
-20
Guard ring on p+ epi (LoRes)
-40
Guard ring on p- (HiRes)
S21 (dB)
-60
-80
DNW on
P- (HiRes)
DNW on
P+ epi
(LowRes)
-100
10 MHz 100 MHz 1 GHz 10 GHz 100 GHz
FREQUENCY
S21 = forward transmission gain/loss
IEDM 2002 23

Substrates: Latch-up, P-P
versus P+ epi
|CROSSTALK in dB|
80
70
60
50
40
30
24-36
Ω-cm
5.5 µm epi
on p+
24-36
Ω-cm
10 µm epi
on p+
25-45
Ω-cm
Non-epi
13
11
9
7
5
LATCH-UP
OVERVOLTAGE
Merrill, R.B.; Young, W.M.; Brehmer, K. Effect of substrate
material on crosstalk in mixed analog/digital integrated circuits
Electron Devices Meeting, 1994.
IEDM 2002 24

Substrates: Latch-up, P-P
versus P+ epi
with and without DNW
HOLDING VOLTAGE (V)
3.0
2.0
1.0
P-
(50 ohm-cm)
P+ epi
DNW (magenta)
No DNW (cyan)
0.4 77 100 0.4 77 100
N+ TO PWELL TAP
DISTANCE (microns)
IEDM 2002 25

Outline
• Technology Features
• CMOS
• SiGe:C HBT
• Isolation
• Passives
IEDM 2002 26

MIM Capacitor
1.10
M7
SiN
V6
Ta
M6
M7
V6
NORMALIZED
CAPACITANCE
1.05
1.00
0.95
0.90
R38
R58
R60
R68
RB4
RC1
RC9
BASELINE TREND
IEDM 2002 27

TTF seconds
(0.2%C at Bias=0V, 1MHz)
1.E+09
1.E+07
1.E+05
1.E+03
1.E+01
MIM Capacitor BiasTemp. Reliability (T=125C)
0 5 10 15 20 25 30
Bias (V)
317 years
< MIM Cap
Bias Temp.
MIM Cap
CV >
NORMALIZED
CAPCITANCE
1.002
1.0015
1.001
1.0005
1
0.9995
15 -10 -5 0 5 10 15
Bias (V)
IEDM 2002 28

MIM Capacitor Reliability
OLD Process >
Cum %
3
2
1
0
-1
-2
Cum Prob %
99.9%
99%
90%
50%
10%
After Stress
Before Stress
0.01 0.1 1 10 100
Qbd (C/cm2)
< New Process
1%
A=5.2k um 2 A=26k um 2 A=130k um 2
0.1%
1.E-07 1.E-06 1.E-05 1.E-04
MIM CAP LEAKAGE AT HIGH BIAS [A]
IEDM 2002 29

Hi-Q Q Inductor Library Templates
PEAK Q
60
50
40
30
20
10
This work
0 0.5 1 1.5 2 2.5
INDUCTANCE (nH)
Literature
Focusing on lower L, Hi-Q inductors to support 10/40G circuits
IEDM 2002 30

Hi-Q Q Inductor Library Templates
60
PEAK Q
70
60
50
40
30
PEAK Q
40
20
0 20 40 60
FREQUENCY OF PEAK Q (GHz)
20
10
0 0.5 1 1.5 2 2.5
This work
INDUCTANCE (nH)
IEDM 2002 31

Measuring Q
0.4
0.2
0.0
Imaginary
Short
De-embedded
-0.2
-0.4
Real
1 GHz
10 GHz
S_dev(1,1)
S_open(1,1)
S_short(1,1)
S_dev_final(1,1)
As Measured
Q =
- Im (Y11)
Re (Y11)
Open
FREQUENCY
(250.0MHz to 50.25GHz)
IEDM 2002 32

Measured versus simulated Q
Inductor Dimension:
Do = 154 um W = 12 um
S = 1 um T = 1.5
20
10
Simulated
Q
0
-10
Measured
1GHz 10 GHz
FREQUENCY
IEDM 2002 33

Hi-Q Q Inductors and substrates
PEAK Q
30
25
20
15
10
5
0
50 ohm-cm
w/o parasitic
control
P+epi
w/o parasitic
control
50 ohm-cm
with parasitic
control
P+ epi
with parasitic
control
0.1 1 10 100
FREQUENCY (GHz)
IEDM 2002 34

Outline
• Technology Features
• CMOS
• SiGe:C HBT
• Isolation
• Passives
• Validation Vehicles
• Conclusions
IEDM 2002 35

Validation vehicles
GHz
10
9
10GHz
LC-VCO
Tuning
Curve
8
0.5 1.0 1.5
VCTL
A large variety of learning vehicles are being supported
Illustrated is an LC-VCO from a 10G SerDes test circuit
IEDM 2002 36

Intel CMOS 10G SerDes Test Circuit
Transmit PLL – Measured Jitter
Meets jitter
transfer function
specification >
This work
OC-192
OC-192 Specification is integral
under curve = 100 mUI;
Actual performance is 40 mUI
~ 2X better
IEDM 2002 37

Conclusions
• Manufacturable communications process
integrated into 90nm digital CMOS
• RF NMOS devices at 225/140 F T /F
• RF PMOS devices at 114/70 F T /F
/F MAX
/F MAX
• Baseline HBT device at 130/100 F T /F
/F MAX
• Reliable 1.15 fF/mm 2 Cu-MIM and resistor
• Hi-Q Q inductors
IEDM 2002 38

Acknowledgment
The authors gratefully acknowledge the
many people at Intel who contributed to this
work, including individuals from the
following organizations:
– PTD Process and Design Groups
– Sort Test Technology Development
– Quality and Reliability Engineering
– Technology Computer Aided Design
IEDM 2002 39

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A record high 150 GHz fmax realized at 0.18 um gate length in an industrial RF-CMOS technology
Electron Devices Meeting, 2001. IEDM Technical Digest. International , 2001. Page(s): 10.4.1 -10.4.4
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IEDM 2002 40

References
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microwave inductors using silicon CMOS technology. Radio Frequency Integrated Circuits (RFIC)
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Electron Devices Meeting, 1996
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IEDM 2002 41

A soft copy of this and other recent Intel
presentations can be found at:
www.intel.com/research/silicon
IEDM 2002 42