A 90 nm Communication Technology Featuring SiGe HBT ...

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Hi-Q Q Inductors and substrates PEAK Q 30 25 20 15 10 5 0 50 ohm-cm w/o parasitic control P+epi w/o parasitic control 50 ohm-cm with parasitic control P+ epi with parasitic control 0.1 1 10 100 FREQUENCY (GHz) IEDM 2002 34
Outline • Technology Features • CMOS • SiGe:C HBT • Isolation • Passives • Validation Vehicles • Conclusions IEDM 2002 35
Page 1 and 2: A 90 nm Communication Technology Fe
Page 3 and 4: Baseline CMOS • Shallow Trench Is
Page 5 and 6: Matching Circuit Needs to Device Ty
Page 7 and 8: Matching Circuit Needs to Device Ty
Page 9 and 10: 90nm CMOS Performance versus Low Po
Page 11 and 12: F T : Intrinsic NMOS Performance FT
Page 13 and 14: Fmax: : Layout • Make R G small T
Page 15 and 16: Outline • Technology Features •
Page 17 and 18: SiGe:C HBT Architecture Extrinsic b
Page 19 and 20: Baseline: 130/100 F T /F /F MAX H21
Page 21 and 22: BJT Yield issues: impact of volume
Page 23 and 24: Isolation: P-P versus P+ epi (with
Page 25 and 26: Substrates: Latch-up, P-P versus P+
Page 27 and 28: MIM Capacitor 1.10 M7 SiN V6 Ta M6
Page 29 and 30: MIM Capacitor Reliability OLD Proce
Page 31 and 32: Hi-Q Q Inductor Library Templates 6
Page 33: Measured versus simulated Q Inducto
Page 37 and 38: Intel CMOS 10G SerDes Test Circuit
Page 39 and 40: Acknowledgment The authors grateful
Page 41 and 42: References 9. Min Park; Seonghearn

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