A 90 nm Communication Technology Featuring SiGe HBT ...

More documents

Recommendations

Info

No CMOS Degradation IOFF [LOG (nA/ /µM)] -4.0 -4.5 -5.0 -5.5 -6.0 -6.5 -7.0 -7.5 -8.0 -8.5 -9.0 NMOS WITH HBT POR NMOS -6.0 0.60 0.80 1.00 1.20 1.40 -7.0 1.60 IDSAT [mA/µm] IOFF [LOG (nA/ /µM)] -4.0 -5.0 -8.0 -9.0 -10.0 -11.0 -12.0 -0.15 -0.25 •NMOS and PMOS I ON versus I OFF characteristics are not degraded by HBT integration PMOS WITH HBT POR PMOS -0.35 -0.45 IDSAT [mA/µm] -0.55 -0.65 IEDM 2002 20
BJT Yield issues: impact of volume Incoming to EPI OLD Process Start of epi dep NEW Process Start of epi dep Increased wafer volume generated Ge deposits on chamber walls: Fixed with purges and pre-coats OLD Process After epi dep NEW Process After epi dep IEDM 2002 21
Page 1 and 2: A 90 nm Communication Technology Fe
Page 3 and 4: Baseline CMOS • Shallow Trench Is
Page 5 and 6: Matching Circuit Needs to Device Ty
Page 7 and 8: Matching Circuit Needs to Device Ty
Page 9 and 10: 90nm CMOS Performance versus Low Po
Page 11 and 12: F T : Intrinsic NMOS Performance FT
Page 13 and 14: Fmax: : Layout • Make R G small T
Page 15 and 16: Outline • Technology Features •
Page 17 and 18: SiGe:C HBT Architecture Extrinsic b
Page 19: Baseline: 130/100 F T /F /F MAX H21
Page 23 and 24: Isolation: P-P versus P+ epi (with
Page 25 and 26: Substrates: Latch-up, P-P versus P+
Page 27 and 28: MIM Capacitor 1.10 M7 SiN V6 Ta M6
Page 29 and 30: MIM Capacitor Reliability OLD Proce
Page 31 and 32: Hi-Q Q Inductor Library Templates 6
Page 33 and 34: Measured versus simulated Q Inducto
Page 35 and 36: Outline • Technology Features •
Page 37 and 38: Intel CMOS 10G SerDes Test Circuit
Page 39 and 40: Acknowledgment The authors grateful
Page 41 and 42: References 9. Min Park; Seonghearn

A 90 nm Communication Technology Featuring SiGe HBT ...

Create successful ePaper yourself

Delete template?

Save as template?