V - Index of

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• ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING
CONDITIONS (Ta =Oto+70°C, Vcc=5V±10%)
• AC Test Conditions
Input Pulse Levels .....•..••• 2.4V.O.4V
Input Rise and Fall Times ........... 5ns
Timing Measurement level ........... 2.2V.O.BV
Reference level .................•• VOH = 2.0V. VOL" O.BV
Output load ................... 1 TTL and 100pF
Item
Random Read or Write Cycle Time
Chip Enable Access Time
Output Enable Access Time
Chip Disable to Output In High Z
Chip Enable to Output In Low Z
Output Disable to Output In High Z
Output Enable to Output In Low Z
Chip Enable Pulse Width
Chip Enable Precharge Time
Address Set-up Time
Address Hold Time
Read Command Set-up Time
Read Command Hold Time
RFSH Hold Time
Chip Select Set-up Time
Chip Select Hoid Time
Write Command Pulse Width
Chip Enable to End of Write
Data In to End of Write
Data In Hold Time for Write
Output Active from End of Write
Write to Output In High Z
Transition Time (Rise and Fall)
Refresh Command Delay Time
Refresh Precharge Time
Refresh Command Pylse Width for Automatic
Refresh
Automatic Refresh Cycle Time
Refresh Command Pulse Width for Self Refresh
Refresh Reset Time for Self Refresh
Refresh Period (512 c~cles)
Symbol
tRC
tCEA
tOEA
tCHZ
tCLZ
tOHZ
tOLZ
tCE
tp
tAS
tAH
tRCS
tRCH
tRHC
tcss
tCSH
twp
tcw
tDW
tDH
tow
tWHZ
tT
tRFD
tFP
tFAP
tFC
tFAS
tRFS
t,..,lI'
HM658128P- IO HM658128P-12 HM658128P-15
HM658128LP-10 HM658128LP-12 HM658128LP-15
mln. max. mln. max. mln. max.
180 - 210 - 250 - ns
- 100 - 120 - 150 ns
- 30 - 40 - 50 ns
- 25 - 30 - 35 ns
30 - 35 - 40 - ns
- 25 - 30 - 35 ns
5 - 5 - 5 - ns
lOOn 2011 120n 2011 150n 2011 s
70 - 80 - 90 - nl
0 - 0 - 0 - ns
25 - 30 - 35 - ns
0 - 0 - 0 - ns
0 - 0 - 0 - ns
15 - 15 - 15 - ns
0 - 0 - 0 - ns
25 - 30 - 35 - ns
20 - 25 - 30 - ns
100 - 120 - 150 - ns
15 - 20 - 25 - ns
0 - 0 - 0 - ns
5 - 5 - 5 - ns
- 25 - 30 - 35 ns
3 SO 3 50 3 50 ns
70 - 80 - 90 - ns
40 - 40 - 40 - ns
80n 811 80n 811 80n 811 s
180 - 210 - 250 - ns
8 - 8 - 8 - 115
180 - 210 - 250 - ns
- 8 - 8 - 8 ms
nit
I
Notes:
(1) tCHZ. tOHZ and tWHZ deime the time at which the
output achieves the open circuit conditions.
(2) tCLZ' tOLZ and tow are sampled under the condition
of t T = Sns and not 100% tested.
(3) A write occurs during the overlap of a low CE and low
W.......
_
(4) If CE~es low simultaneously with WE going low or
after WE going low. the outputs remaln In high impedance
state.
(5) If lnput signals of opposite phase to the outputs are
applied In write cycle. OE or WE must disable output
buffers prior to applying data to the device and data
lnputs must be floating prior to OE or WE turning on
output buffers.
(6) VIH (mln) and VI1- (max) are reference levels for
measuring timing 0 mput signals. Also. transition times
are measured between VJH and VIL'
(7) An lnitial pause of 100115 is required after power-up
followed by a minimum of 8 lnitialization cycles.
~HITACHI
Hitachi America Ltd. • 2210 O'Toole Avenue • San Jose, CA 95131 • (408) 435-8300
295