Week 10: MOS Logic Circuits

ELE 2110A Electronic Circuits 

Week 10: 

MOS Logic Circuits 

(45 minutes only) 

ELE2110A © 2008 

Lecture 10 - 1

• CMOS Inverter 

– Static characteristics 

– Dynamic characteristics 

– Power dissipation 

• Other CMOS logic gates 

Topics to cover … 

Reading Assignment: 

Chap 6.1-6.3, 7.1-7.4 of Jaeger and Blalock or 

Chap 7.1 - 7.3, 7.7 of Sedra and Smith 



Digital IC Technologies and Logic-Circuit Family 

Digital IC technologies & logic circuit family 

CMOS Bipolar BiCMOS GaAs 

CMOS 

This course 

Pseudo 

-NMOS 

Pass 

Transistor 

Logic 

Dynamic 


Transistor- 

Transistor 

Logic (TTL) 

Emitter 

Coupled 


(ECL) 



Ideal Inverter 

V O 

V OH 

=V DD 

V OL 

=0 

V DD 

/2 

V DD 

V I 

The Voltage Transfer 

Characteristic (VTC) 

of an ideal inverter 



CMOS Inverter 

pmos 

nmos 

PU: pull up network, responsible for producing HIGH output 

PD: pull down network, responsible for producing LOW output 



Case 1: V I =V DD 

) 

“pull-down” 

Q P 

OFF 

Q N 

ON: output pulled down 

V O 

=0V 

The output resistance of Q N 

(linear mode): 

r 

DSN 

= 

⎛ 

k ′ 

n ⎜ 

⎝ 

W 

L 

1 

⎞ 

⎟( 

V 

⎠ 

DD 

− V 

tn 



Case 2: V I = 0V 

“pull-up” 

Q N 

OFF 

Q P 

ON: output pulled up. 

The output resistance of Q P 

(linear mode): 

r 

DSN 

= 

→V O 

=V DD 

) 

k ′ 

p 

⎛ W 

⎜ 

⎝ L 

1 

⎞ 

⎟( 

V 

⎠ 

DD 

− V 

tp 











Dynamic Characteristic: Rise and Fall times 

• The rise and fall times, t f and t r , 

are measured at the 10% and 

90% points on the transitions 

between the two states. 

V 10% = V L + 0.1∆V 

V 90% = V L + 0.9∆V 

= V H – 0.1∆V 



Dynamic Characteristic: Propagation Delay 

• Propagation delay: the time between 

a change at the 50% point input to 

cause a change at the 50% point of 

the output 

• The high-to-low prop delay, τ PHL 

, and 

the low-to-high prop delay, τ PLH 

, are 

usually not equal, but can be 

described as an average value: 

τ 

P 

τ 

= 

PHL 

+ τ 

2 

PLH 


Lecture 10 - 10

Propagation Delay 

• C represents parasitic capacitances: 

– MOS gate capacitance of next logic gate 

– Wire capacitance to ground 

• Output parasitic capacitor voltage cannot change instantaneously 

• Capacitive charging/discharging contributes to propagation delay 



Propagation Delay Estimate 

• It can be shown (see section 7.3.1 and 6.14.12) 

τ 

PHL 

∝ 

where 

R 

R 

onN 

onN 

µ 

nCox 

( VH 

−VTN 

) 

⎛W 

⎞ 

µ C ⎜ ⎟ = µ 

⎝ L ⎠ n 

• The delay also depends on R ON 

C 

= 

• For matched nmos and pmos ( n ox 

p ox ), τ PLH = τ PHL 

W 

L 

• The delay depends on C 

– In smaller feature size CMOS process, wires and transistors are smaller 

– Parasitic C is smaller 

– Delay is smaller Circuits run faster 

1 

C 

⎛ W ⎞ 

⎜ ⎟ 

⎝ L ⎠ 

p 



Example 

Given that: 

For C=1pF, 

τ 

p 

= 6. 4ns 

τ = ? 

τ p 

= ? 

p 



Ring Oscillator 

1 2 3 4 5 6 

To OSC input 

• If odd number of inverters (at least 3) are connected as a ring, it 

oscillates. 

• Oscillation frequency relates to the propagation delay of the inverters 

• Waveform at 6 = waveform at 1 5 Delays = T/2 Delay = T/10 

At 1 

At 2 

At 3 

At 4 

At 5 

At 6 

T/2 

T 

0V 











Power Dissipation 

• CMOS logic has no static power dissipation 

– The is no DC path between VDD and GND at any time 

• But, when the inverter changes its output… 



Dynamic Power Dissipation 

• When the inverter charges or discharges the output capacitor, it 

consumes power. 

Charging 

Discharging 




• The energy delivered from the VDD is: 

E 

D 

∞ 

∞ 

VC 

( ∞) 

dq( 

t) 

2 

= V ∫ DD 

i( t) 

dt = V ∫ DD 

dt = CV ∫ DD 

1dvC 

= CVDD 

dt 

0 

0 

V (0) 

• The energy stored by the capacitor is: 

E = 

D 

CV 

2 

2 

DD 

• The difference between the above two terms represents the energy 

lost in the resistive elements: 

C 

E = E − E = 

L 

D 

S 

CV 

2 

2 

DD 




• The total energy lost in the first charging and discharging of the 

capacitor through resistive elements is given by: 

2 

2 

CVDD 

CVDD 

E 

TD 

= + = 

2 2 

CV 

2 

DD 

• For every clock cycle, the dynamic power dissipation is: 

P 

D 

= Energy/Tim e = 

CV 

2 

DD 

f 

– This result can be extended to a complex digital IC, where 

C represents the area of the IC 

– Lower V DD 

is very effective for reducing power supply 

– Reducing C also helps reducing power 











CMOS NOR Gate 

Pull-up Network: 

Y = 

AB 

Pull-down Network: 

Y = A + 

B 

Y = A + 

B 



Gate Sizing 

• Want to keep the delay times the same as a reference inverter 

under the worst case input conditions. 

• Consider a two-input NOR gate: 

– (W/L) n 

should be same as that of the inverter 

– (W/L) p 

should be twice as large as that of the inverter 

Reference Inverter 



CMOS NAND Gate 

Pull-up Network: 

Y = A + 

Y = 

B 

Pull-down Network: 

AB 

Y = 

AB

Week 10: MOS Logic Circuits

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