Intel IXA SDK ACE Programming Framework - Department of ...

The ACE Programming Framework for Packet Handling
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The core component of a microACE is a complete conventional ACE, with
C/C++, NCL, and IXA IDL code. The core component runs on the core processor
in the IXP1200.
The acceleration component of a microACE, called a microblock, is hardwarespecific
and is written in IXP1200 microcode (machine code). The microblock runs
on the microengines in the IXP1200. It performs fast-path processing, but can
exchange packets with its core component on the core processor to handle exception
cases.
For more information on hardware platforms and deployment options, see “Hardware
Architecture: The IXP1200 Network Processor” on page 14.
You use microACEs for optimized, high-speed (fast-path) processing. Because the
IXP1200 network processor contains a number of microengines running in parallel,
each with multiple threads, microACEs provide extremely high efficiency in basic
packet handling. Most system ACEs and library ACEs are implemented as micro-
ACEs.
The IXA SDK includes a complete set of tools, including compilers, linkers, and
debuggers, for working with microcode to develop microACEs. For more information
on the architecture of microACEs, see Chapter 6, “Writing MicroACEs.”
Dividing Tasks
Among ACE
Types
Generally, a microACE looks in a packet to classify it, performs simple transformations
(such as NAT or protocol conversion), and routes it to the appropriate target.
Exceptions are reported to another (conventional) ACE for handling. This allows
time-consuming operations to run in parallel without slowing down traffic.
The following figure shows an example of a forwarding application that uses a
microACE for data processing and a conventional ACE for control.
8 Introduction and Overview
Revision 3.3, August 2001