Synopsys University Program - Power.org

ASIA 

POWER 

ARCHITECTURE 

CONFERENCE 

SHENZHEN, CHINA 

1 SEPTEMBER 2011 

THINKPOWER 

CELEBRATING 20 YEARS OF POWER ARCHITECTURE INNOVATION 

Advancing Engineering Education 

with Power Architecture 

Vazgen Melikyan 

Director, Synopsys Armenia Education Department 

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org.

About Synopsys University 

Program

Synopsys Worldwide University Program 

Mission 

Synopsys’ worldwide university program provides 

industry-leading tools and resources for teaching and academic 

research to universities around the globe to train industry-ready 

graduates with the knowledge and skills required to meet the 

needs of the global semiconductor industry 

Global Presence 

• 1375 University Sites Worldwide 

• 60+ countries 

• Global Distribution: 

~355 in North & South America ~600 in Europe & Middle East 

~345 in Asia Pacific &India ~75 in Japan 


Educating Tomorrow’s Engineers Today 

• Synopsys managed degree programs 

• State-of-the-art curriculum 

• Graduates are productive on day one 

• Accredited in three countries 

• Adopted in seven countries 

• Industry-standard tools & curriculum available to 

universities 

• Unique programs 

• President’s awards 

• Microelectronics Olympiads 

• Charles Babbage Grant 

Synopsys University Program 

>72 licensed sites in China 


State-of-the-Art Curriculum 

Includes: 

Syllabus 

Lectures 

Labs 

Homework 

Exams 


Users of Synopsys Curriculum 

And hundreds more!… 


Synopsys 90nm Education Design Kit (EDK) 

Free of IP Restrictions 

* 

* Requires separate license through IBM Academic Initiative 


Synopsys University Program Tools Package 

Comprehensive RTL-2-GDSII & more suite of design tools 

HSPICE 

Hercules 

StarRC 

Milkyway Environment 

Liberty NCX 

Library Compiler 

coreBuilder 

coreAssembler 

VCS 

Design Compiler 

DFT Compiler 

HDL Compiler 

Power Compiler 

Formality 

TetraMAX 

IC Compiler 

Physical Compiler 

PrimeTime SI 


Why Power Architecture for 

Education?

Requirements for Education 

• Real-world hardware IP 

• Education Design Kits (EDK’s) free from IP restrictions 

• RTL-2-GDS EDA design tools from industry-leading supplier 


Attraction of Power Architecture for Education 

• Implements modern technologies 

• Enables education using more real-world complex designs 

• Can be used as basis for exploring novel architectures and technologies 


PowerPC 405 for Education 

Available for license through IBM Academic Initiative to 

qualified Synopsys University Program members 

Complete Synthesizable Solution 

• Specification 

• Design RTL (Verilog) 

• Synthesis scripts 

• Verification test suites 

• Full simulation environment 


Synopsys 90nm EDK support for Power Architecture 

EDK updated to include necessary memories 

for PowerPC 405*-based curriculum 

• SRAMs were designed and added to EDK 

• Four cache size configurations 

• 32-bit 

• Fully associative translation lookaside 

buffer 

Courseware developed based on PowerPC 405 

• Complete RTL-2-GDSII design flow course 

using Synopsys Tools 



90nm EDK Design Flow Using Synopsys Design Tools 

Updated to support RTL-2-GDSII Power Architecture curriculum 

• Added support for design of 4 different cache configurations 

• Updated to work with synthesizable PowerPC 405* constraints and scripts 



Use of Power Architecture in 

Synopsys Curriculum

Power Architecture use in Synopsys Curriculum 

PowerPC-based Digital Design Course 

Based on the synthesizable PowerPC 405* using the Synopsys 90nm EDK 

Implements complete digital design flow using Synopsys EDA tools and 

includes: 

• Lectures covering RTL-to-GDSII design steps in the flow 

• Labs that highlight the logic and physical synthesis steps in the design flow 

Power Architecture Digital Design course and 90nm EDK are available for 

download at Synopsys.com with a SolvNet id and password 

• https://www.synopsys.com/apps/protected/university/members.html 



Power Architecture Digital Design Course Lectures 

• Introduction to Digital Design Flow 

• Data Preparation for Design Compiler 

(DC) 

• Importing the Design into DC Design 

Constraints 

• Design Mapping and Writing Results 

• Data Preparation for IC Compiler (ICC) 

• Design Importing, Floorplanning, 

Power Planning and FP Placement 

• Placement 

• Clock Tree Synthesis 

• Route and Finishing 

• Working with final data 

Physical Synthesis (2) 

IC Compiler 

Synopsys University Courseware 

© 2010 Synopsys, Inc. 

Developed By: Vazgen Melikyan 

Command for Routing (1) 

-effort 

-xtalk_reduction 

-only_xtalk_reduction 

-skip_initial_route 

-stage 

-power 

route_opt 

-incremental 

-size_only 

-optimize_wire_via 

-area_recovery 

-wire_size 

-only_wire_size 

Invoke ICC 

Data preparation 

Floorplanning 

Power Planning 

Placement 

CTS 

Routing 

Finishing 

Results (.v,.gds, .spef) 

Incremental Routing 







To switch on incremental 

mode, select Incremental 

mode. 


Power Architecture Digital Design Course Labs 

• Data preparation for normal operation in DC GUI 

• Importing design into DC. Design constraints 

• Design synthesis using technology specific libraries 

• Data preparation for normal operation in ICC 

• Design synthesis using technology specific libraries 

• Placement 

• Clock tree synthesis 

• Route 

• Finishing 


Power Architecture Lab Example (1) 

Lab 2: Importing design into DC, Design constraints 

2.1 Invoking DC 

2.2 Reading the design 

2.3 Sourcing constraints 

Screens Shots of Steps 

. 

. 

Design Constraints 

## CLOCK BASICS 

create_clock -name "clock" -period $PERIOD [get_ports clock] 

set_clock_latency $CLOCK_LATENCY [get_clocks clock ] 

set_clock_uncertainty 0.3 [get_clocks clock ] 

set_clock_transition 0.4 [get_clocks clock ] 

## IN/OUT 

set INPUTPORTS [remove_from_collection [all_inputs] [get_ports 

clock ]] 

set OUTPUTPORTS [all_outputs] 

set_input_delay -clock "clock" -max $INPUT_DELAY $INPUTPORTS 

set_output_delay -clock "clock" -max $OUTPUT_DELAY $OUTPUTPORTS 

set_input_delay -clock "clock" -min $MIN_IO_DELAY $INPUTPORTS 

set_output_delay -clock "clock" -min $MIN_IO_DELAY $OUTPUTPORTS 

. 

. 


Power Architecture Example (2) 

Lab 6: Placement 

Screens Shots of Steps 

6.1 Invoke ICC 

6.2 Read design 

6.3 Floorplan 

6.4 Perform power planning 

6.5 FP placement 

6.6 Placement 


Summary

Summary 

• Access to real world designs and open design kits is vital for 

educational purposes 

• Synopsys has developed an open EDK and educational materials 

designed to be used with the synthesizable PowerPC 405 licensed 

through the IBM Academic Initiative 

• Use of this licensed IP and educational material provides practical 

real world design experience leading to productive graduates on day 

one 


Thank You!

Synopsys University Program - Power.org

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?