Animating the Datapath Animating the Datapath: R-type Instruction ...

Animating the DatapathMIPS Datapath I: Single-CycleInput is either register (R-type) or sign-extendedlower half of instruction (load/store)op rs rt offset/immediate5 5RN1 RN2 WNRD1Register FileWDRegWriteRD216EXTND3216OperationALUPC +4 frominstructiondatapathZero

Instruction3216Animating the Datapath:Store Instruction5 5RN1 RN2 WNRD1Register FileWDRegWrite5RD2E16 X 32 TNDMUXALUSrcOperation3ALUsw rt,offset(rs)ZeroMemWriteADDRDataMemoryWDMemReadRDMemtoRegMUXMIPS Datapath II: Single-CyclePC4ReadaddressInstructionInstructionmemoryAddSeparate instruction memoryas instruction and data readoccur in the same clock cycleSeparate adder as ALU operations and PCincrement occur in the same clock cycleReadregister 1Readregister 2WriteregisterWritedataRegWriteRegistersReaddata 1Readdata 216 Sign 32extendALUSrcMuxAdding instruction fetch3ALU operationZeroALU ALUresultAddressWritedataMemReadMemWriteReaddataDatamemoryMemtoRegMuxMIPS Datapath III: Single-CycleDatapath Executing addadd rd, rs, rtPCSrcNew multiplexorPC4ReadaddressAddInstructionInstructionmemoryInstruction address is eitherPC+4 or branch target addressReadregister 1Readregister 2WriteregisterWritedataRegistersReaddata 1Readdata 2RegWrite16Sign32extendShiftleft 2ALUSrcMuxAdd ALUresultMuxExtra adder needed as bothadders operate in each cycle3 ALU operationMemWriteZeroALU ALUresultAddressWritedataMemReadReaddataDatamemoryMemtoRegMuxPC4ADDADDRInstructionMemoryRDInstruction32165 5RN1 RN2 WNRD1Register FileWDRegWrite5RD216EXTND32

Datapath Executing lwlw rt,offset(rs)Datapath Executing swsw rt,offset(rs)ADDADD4ADDMUX4ADDMUXPCADDRInstructionMemoryRDInstruction32165 5RN1 RN2 WNRD1Register FileWDRegWrite5RD216EXTND32

ALU Control• Plan to control ALU: main control sends a 2-bit ALUOp control field tothe ALU control. Based on ALUOp and funct field of instruction theALU control generates the 3-bit ALU control fieldRecall from Ch. 4– ALU control Funcfieldtion000 and001 or010 add110 sub111 sltMainControlALUControl• ALU must perform– add for load/stores (ALUOp 00)– sub for branches (ALUOp 01)– one of and, or, add, sub, slt for R-type instructions, depending on theinstruction’s 6-bit funct field (ALUOp 10)6Instructionfunct field2ALUOpALUOp generationby main control3ALUcontrolinputToALUSetting ALU Control BitsInstruction AluOp Instruction Funct Field Desired ALU controlopcodeoperation ALU action inputLW 00 load word xxxxxx add 010SW 00 store word xxxxxx add 010Branch eq 01 branch eq xxxxxx subtract 110R-type 10 add 100000 add 010R-type 10 subtract 100010 subtract 110R-type 10 AND 100100 and 000R-type 10 OR 100101 or 001R-type 10 set on less 101010 set on less 111*Typo in textFig. 5.15: if it is Xthen there is potentialconflict betweenline 2 and lines 3-7!ALUOp Funct field OperationALUOp1 ALUOp0 F5 F4 F3 F2 F1 F00 0 X X X X X X 0100*1 X X X X X X 1101 X X X 0 0 0 0 0101 X X X 0 0 1 0 1101 X X X 0 1 0 0 0001 X X X 0 1 0 1 0011 X X X 1 0 1 0 111Truth table for ALU control bitsDesigning the Main ControlDatapath with Control IPCSrcR-typeLoad/storeor branchopcode31-26 25-21 20-16 15-11 10-6 5-0opcodersrsrtrtrd shamt functaddress31-26 25-21 20-16 15-0• Observations about MIPS instruction format– opcode is always in bits 31-26– two registers to be read are always rs (bits 25-21) and rt (bits 20-16)– base register for load/stores is always rs (bits 25-21)– 16-bit offset for branch equal and load/store is always bits 15-0– destination register for loads is in bits 20-16 (rt) while for R-typeinstructions it is in bits 15-11 (rd) (will require multiplexor to select)PC4AddReadaddressInstruction[31– 0]InstructionmemoryNew multiplexorInstruction [25– 21]Instruction [20– 16]1MuInstruction [15– 11] x0RegDstInstruction [15– 0]WriteregisterWritedataRegWriteReadregister 1Readregister 2Readdata 1Readdata 2Registers16 Sign 32extendInstruction [5– 0]Shiftleft 2ALUSrc1Mux0ALUcontrolALUOpALUAddresultZeroALU ALUresult1Mux0MemWriteAddressWritedataDatamemoryMemReadReaddataMemtoRegAdding control to the MIPS Datapath III (and a new multiplexor to select field tospecify destination register): what are the functions of the control signals?1Mux0

Control SignalsDatapath with Control II0Signal Name Effect when deassertedEffect when assertedRegDst The register destination number for the The register destination number for theWrite register comes from the rt field (bits 20-16) Write register comes from the rd field (bits 15-11)RegWrite None The register on the Write register input is writtenwith the value on the Write data inputAlLUSrc The second ALU operand comes from the The second ALU operand is the sign-extended,second register file output (Read data 2) lower 16 bits of the instructionPCSrc The PC is replaced by the output of the adder The PC is replaced by the output of the adderthat computes the value of PC + 4that computes the branch targetMemRead None Data memory contents designated by the addressinput are put on the first Read data outputMemWrite None Data memory contents designated by the addressinput are replaced by the value of the Write data inputMemtoReg The value fed to the register Write data input The value fed to the register Write data inputcomes from the ALUcomes from the data memoryPC4ReadaddressInstructionmemoryAddInstruction[31– 0]Instruction [31 26]Instruction [25 21]Instruction [20 16]Instruction [15 11]Instruction [15 0]Control0Mux1RegDstBranchMemReadMemtoRegALUOpMemWriteALUSrcRegWriteReadregister 1Readdata 1Readregister 2Registers ReadWrite data 2registerWritedata16 32SignextendShiftleft 20Mux1ALUcontrolAddresultALUZeroALU ALUresultWritedataMux1AddressPCSrcDatamemoryReaddata1Mux0Effects of the seven control signalsInstruction [5 0]MIPS datapath with the control unit: input to control is the 6-bit instructionopcode field, output is seven 1-bit signals and the 2-bit ALUOp signal4AddRegDstBranchMemReadShiftleft 2AddALUresult0Mux1PCSrcPCSrc cannot beset directly from theopcode: zero testoutcome is requiredControl Signals:R-Type InstructionInstruction [31 26]MemtoRegControlALUOpMemWriteALUSrcRegWritePCReadaddressInstructionmemoryInstruction[31– 0]Instruction [25 21]Instruction [20 16]Instruction [15 11]Instruction [15 0]0Mux1Readregister 1Readregister 2RegistersWriteregisterWritedataInstruction [5 0]16 32SignextendInstruction RegDst ALUSrcMemto-RegRegWriteMemReadMemWrite Branch ALUOp1 ALUp0R-format 1 0 0 1 0 0 0 1 0lw 0 1 1 1 1 0 0 0 0sw X 1 X 0 0 1 0 0 0beq X 0 X 0 0 0 1 0 1Readdata 1Readdata 20Mux1ALUcontrolZeroALU ALUresultDetermining control signals for the MIPS datapath based on instruction opcodeAddressWritedataDatamemoryReaddata1Mux0PC4ADDADDR RDInstructionMemoryimmediate/offsetI[15:0]Control signalsshown in blueInstructionI 3216rsI[25:21]rtI[20:16]5 5RN1 RN2 WNRD1Register FileWDRegWrite10rdI[15:11]5MUX5RD21E16 X 32TND10???RegDstOperation01MUXALUSrc

Drag‐and‐drop programmingTeachers have quickly realized that adding actionable objects in lessons is a great way of creating even moreinteresting and intriguing activities for your students. You will find that ActivInspire makes it easier and quickerthrough a new Drag‐and‐Drop option.Open your Browser by choosing View > Browser, and clicking on the Action Browser icon as indicated by the redarrow below. Next, click on the Drag‐and‐Drop tab. If you want to make something interactive, just drag thefunction you want the software to do onto the flipchart. Drop it on the page and an icon will then appear withthat action ready to click.If you drop the action item on top of an object, then that object will carry out the assigned action. For example,you can drag the Notes Browser onto the question mark shown on the flipchart page below, or drag the NextPage onto the blue arrow. When you click on either one, the appropriate action will occur.Quick Tip: If you want to add an action to an object on the page and your browser window is not open, you canquickly bring up the Action browser by choosing the object and its Object Edit menu, and selecting ActionBrowser! Then drag your action onto the object!Creating interactive lessons couldn’t be easier, or faster!9

Step 2: Instruction Decode andRegister Fetch (ID)• Read registers rs and rt in case we need them.Compute the branch address in case the instruction is a branch.• RTL:A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC + (sign-extend(IR[15-0])

Multicycle Datapath with Control IINew gatesFor the jump addressNew multiplexorMulticycle Control Step (1):FetchPCWriteCondPCWriteIorDMemReadMemWriteMemtoRegOutputsControlPCSourceALUOpALUSrcBALUSrcARegWriteIR = Memory[PC];PC = PC + 4; 1IRWritePC0Mux1AddressWritedataMemoryMemDataInstruction[31-26]Instruction[25– 21]Instruction[20– 16]Instruction[15– 0]InstructionregisterInstruction[15– 0]MemorydataregisterIRWriteInstruction [25– 0]Instruction[15– 11]Op[5– 0]0Mux10Mux1RegDst16Readregister 1Readregister 2WriteregisterWritedataRegistersSignextendComplete multicycle MIPS datapath (with branch and jump capability)and showing the main control block and all control linesReaddata 1Readdata 232Instruction [5– 0]Shiftleft 2AB401 Mu2 x30Mux126 28ShiftALUcontrolleft 2PC [31-28]ZeroALU ALUresultJumpaddress [31-0]ALUOut012Mux1PCWr*PC0IorD0 MU1 X0MemWriteADDRMemoryWDMemRead1RDIRMDRInstruction I321 MU0 XMemtoRegXimmediatersrt5 5RN1 RN2 WNRegisters RD1WDRegWrite0E16 X 32TNDjmpaddrI[25:0]5rd0MUX1 RegDst5RD2

Multicycle Control Step (3):ALU Instruction (R-Type)Multicycle Control Step (3):Branch InstructionsALUOut = A op B;0IRWriteif (A == B) PC = ALUOut;0IRWrite0PCWr*PCXIorD0 MU1 XMemWriteADDRMemoryWDMemRead00 132RegDst5 5 MUX5 X10RDIRMDRInstruction I1 MU0 XMemtoRegXimmediatersrtRN1 RN2 WNRegisters RD1WDRegWrite0E16 X 32TND5RD2jmpaddrI[25:0]rd

Multicycle Execution Steps (4)Memory Access - Write (sw)Memory[ALUOut] = B;IRWrite0Multicycle Control Step (4):ALU Instruction (R-Type)Reg[IR[15:11]] = ALUOut; (Reg[Rd] =ALUOut) 0IRWrite0PCWr*PC1IorD0 MU1 XMemWriteADDRMemoryWDMemRead10321 RegDst5 5 MUX5 XX0RDIRMDRInstruction I1 MU0 XMemtoRegXimmediatersrtRN1 RN2 WNRegisters RD1WDRegWrite0E16 X 32TND5RD2jmpaddrI[25:0]rd

Implementing ControlReview: Finite State Machines• Value of control signals is dependent upon:– what instruction is being executed– which step is being performed• Finite state machines (FSMs):– a set of states and– next state function, determined by current state and the input– output function, determined by current state and possibly input• Use the information we have accumulated to specify a finitestate machine– specify the finite state machine graphically, or– use microprogrammingInputsCurrent stateClockNext-statefunctionNextstate• Implementation is then derived from the specificationOutputfunctionOutputs– We’ll use a Moore machine – output based only on current stateStartExample: Moore Machine• The Moore machine below, given input a binary stringterminated by “#”, will output “even” if the string has an evennumber of 0’s and “odd” if the string has an odd number of 0’s1Even stateNooutputOutput“even”00Odd stateNooutput# #Output“odd”1FSM Control: High-level ViewAsserted signalsshown insidestate circlesMemory accessinstructions(Figure 5.38)StartStartMemory reference FSM(Figure 5.38)Instruction fetch/decode and register fetch(Figure 5.37)R-type instructions(Figure 5.39)Branch instruction(Figure 5.40)High-level view of FSM control(Op = 'LW') or (Op = 'SW')Instruction fetch0MemReadALUSrcA = 0IorD = 0IRWriteALUSrcB = 01ALUOp = 00PCWritePCSource = 00R-type FSM(Figure 5.39)(Op = R-type)Branch FSM(Figure 5.40)Jump instruction(Figure 5.41)(Op = 'BEQ')Instruction decode/Register fetch1ALUSrcA = 0ALUSrcB = 11ALUOp = 00(Op = 'JMP')Jump FSM(Figure 5.41)Output even stateOutput odd stateInstruction fetch and decode steps of every instruction is identical

FSM Control: Memory Reference2From state 1ALUSrcA = 1ALUSrcB = 10ALUOp = 00(Op = 'LW') or (Op = 'SW')Memory address computationFSM Control: R-type InstructionFrom state 1(Op = R-type)Execution63(Op = 'LW')Memoryaccess(Op = 'SW')5MemoryaccessALUSrcA = 1ALUSrcB = 00ALUOp = 104MemReadIorD = 1Write-back stepMemWriteIorD = 17RegDst = 1RegWriteMemtoReg = 0R-type completionRegWriteMemtoReg = 1RegDst = 0To state 0(Figure 5.37)FSM control for memory-reference has 4 statesTo state 0(Figure 5.37)FSM control to implement R-type instructions has 2 statesFSM Control: Branch InstructionFSM Control: Jump Instruction8From state 1(Op = 'BEQ')ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCondPCSource = 01Branch completion9From state 1(Op = 'J')PCWritePCSource = 10Jump completionTo state 0(Figure 5.37)FSM control to implement branches has 1 stateTo state 0(Figure 5.37)FSM control to implement jumps has 1 state

EXMEMWB23FSM Control: Complete View4Memory addresscomputationALUSrcA = 1ALUSrcB = 10ALUOp = 00(Op = 'LW')MemReadIorD = 1MemoryaccessRegDst = 0RegWriteMemtoReg =1(Op = 'SW')5Write-back stepStart(Op = 'LW') or (Op = 'SW')MemWriteIorD = 1IFMemoryaccess67Instruction fetch0MemReadALUSrcA = 0IorD = 0IRWriteALUSrcB = 01ALUOp = 00PCWritePCSource = 00ExecutionALUSrcA =1ALUSrcB = 00ALUOp= 10RegDst = 1RegWriteMemtoReg = 08R-type completion(Op = R-type)BranchcompletionIDALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCondPCSource = 01(Op = 'BEQ')Instruction decode/register fetch19ALUSrcA = 0ALUSrcB = 11ALUOp = 00(Op = 'J')JumpcompletionPCWritePCSource = 10Labels on arcs are conditionsthat determine next stateThe complete FSM control for the multicycle MIPS datapath:refer Multicycle Datapath with Control IIExample: CPI in a multicycleCPU• Assume– the control design of the previous slide– An instruction mix of 22% loads, 11% stores, 49% R-type operations,16% branches, and 2% jumps• What is the CPI assuming each step requires 1 clock cycle?• Solution:– Number of clock cycles from previous slide for each instruction class:• loads 5, stores 4, R-type instructions 4, branches 3, jumps 3– CPI = CPU clock cycles / instruction count= Σ (instruction count class i× CPI class i) / instruction count= Σ (instruction count class I/ instruction count) × CPI class I= 0.22 × 5 + 0.11 × 4 + 0.49 × 4 + 0.16 × 3 + 0.02 × 3= 4.04FSM Control:ImplementationOp5Op4Op3PCWritePCWriteCondIorDMemReadMemtoRegPCSourceALUOpALUSrcBALUSrcARegWriteRegDstHigh-level view of FSM implementation: inputs to the combinational logic block arethe current state number and instruction opcode bits; outputs are the next statenumber and control signals to be asserted for the current stateOp2Op1Instruction registeropcode fieldControl logicInputsOp0Four state bits are required for 10 statesS3S2OutputsS1S0State registerMemWriteIRWriteNS3NS2NS1NS0FSMControl:PLAImplementationOp5Op4Op3Op2Op1Op0S3S2S1S0PCWritePCWriteCondIorDMemReadMemWriteIRWriteMemtoRegPCSource1PCSource0ALUOp1ALUOp0ALUSrcB1ALUSrcB0ALUSrcARegWriteRegDstNS3NS2NS1Upper half is the AND plane that computes all the products. The products are carriedto the lower OR plane by the vertical lines. The sum terms for each output is given bythe corresponding horizontal lineE.g., IorD = S0.S1.S2.S3 + S0.S1.S2.S3NS0

FSM Control: ROMImplementation• ROM (Read Only Memory)– values of memory locations are fixed ahead of time• A ROM can be used to implement a truth table– if the address is m-bits, we can address 2 m entries in the ROM– outputs are the bits of the entry the address points tomnROM m = 3n = 4address output0 0 0 0 0 1 10 0 1 1 1 0 00 1 0 1 1 0 00 1 1 1 0 0 01 0 0 0 0 0 01 0 1 0 0 0 11 1 0 0 1 1 01 1 1 0 1 1 1The size of an m-input n-output ROM is 2 m x n bits – such a ROM canbe thought of as an array of size 2 m with each entry in the array beingn bitsFSM Control: ROM vs. PLA• First improve the ROM: break the table into two parts– 4 state bits give the 16 output signals – 2 4 x 16 bits of ROM– all 10 input bits give the 4 next state bits – 2 10 x 4 bits of ROM– Total – 4.3K bits of ROM• PLA is much smaller– can share product terms– only need entries that produce an active output– can take into account don't cares• PLA size = (#inputs ´ #product-terms) + (#outputs ´ #productterms)– FSM control PLA = (10x17)+(20x17) = 460 PLA cells• PLA cells usually about the size of a ROM cell (slightly bigger)Microprogramming• Microprogramming is a method of specifying FSM control thatresembles a programming language – textual rather graphic– this is appropriate when the FSM becomes very large, e.g., if theinstruction set is large and/or the number of cycles per instructionis large– in such situations graphical representation becomes difficult asthere may be thousands of states and even more arcs joining them– a microprogram is specification : implementation is by ROM or PLA• A microprogram is a sequence of microinstructions– each microinstruction has eight fields (label + 7 functional)• Label: used to control microcode sequencing• ALU control: specify operation to be done by ALU• SRC1: specify source for first ALU operand• SRC2: specify source for second ALU operand• Register control: specify read/write for register file• Memory: specify read/write for memory• PCWrite control: specify the writing of the PC• Sequencing: specify choice of next microinstructionMicroprogramming• The Sequencing field value determines the execution order ofthe microprogram– value Seq : control passes to the sequentially next microinstruction– value Fetch : branch to the first microinstruction to begin the nextMIPS instruction, i.e., the first microinstruction in the microprogram– value Dispatch i : branch to a microinstruction based on controlinput and a dispatch table entry (called dispatching):• Dispatching is implemented by means of creating a table, calleddispatch table, whose entries are microinstruction labels and which isindexed by the control input. There may be multiple dispatch tables –the value Dispatch i in the sequencing field indicates that the i thdispatch table is to be used

Control Microprogram• The microprogram corresponding to the FSM control showngraphically earlier:LabelALUcontrol SRC1 SRC2Registercontrol M em oryPCW ritecontrol SequencingFetch Add PC 4 Read PC ALU SeqAdd PC Extshft Read Dispatch 1M em 1 Add A Extend Dispatch 2LW 2 Read ALU SeqW rite M DRFetchSW 2 W rite ALU FetchRform at1 Func code A B SeqW rite ALUFetchBEQ 1 Subt A B ALUO ut-cond FetchJUM P1 Jum p address FetchMicroprogram containing 10 microinstructionsDispatch ROM 1Op Opcode name Value000000 R-format Rformat1000010 jmp JUMP1000100 beq BEQ1100011 lw Mem1101011 sw Mem1Dispatch Table 1Dispatch ROM 2Op Opcode name Value100011 lw LW2101011 sw SW2Dispatch Table 2Microcode: Trade-offs• Specification advantages– easy to design and write– typically manufacturer designs architecture and microcode in parallel• Implementation advantages– easy to change since values are in memory (e.g., off-chip ROM)– can emulate other architectures– can make use of internal registers• Implementation disadvantages– control is implemented nowadays on same chip as processor so theadvantage of an off-chip ROM does not exist– ROM is no longer faster than on-board cache– there is little need to change the microcode as general-purposecomputers are used far more nowadays than computers designed forspecific applicationsSummary• Techniques described in this chapter to design datapaths andcontrol are at the core of all modern computer architecture• Multicycle datapaths offer two great advantages over single-cycle– functional units can be reused within a single instruction if they areaccessed in different cycles – reducing the need to replicate expensivelogic– instructions with shorter execution paths can complete quicker byconsuming fewer cycles• Modern computers, in fact, take the multicycle paradigm to a higherlevel to achieve greater instruction throughput:– pipelining (next topic) where multiple instructions executesimultaneously by having cycles of different instructions overlap in thedatapath– the MIPS architecture was designed to be pipelined