An Iterative Algorithm and Low Complexity Hardware Architecture ...

More documents

Recommendations

Info

40 Yeung and ChuggF 0 = 0 (14)B M = 0 (15)F k+1 [0] = min(F k [0], F k [2] + LI 1 k ) (16)F k+1 [1] = min(F k [0] + RI k + LI 0 k + LI 1 k ,F k [2] + RI k + LI 0 k ) (17)F k+1 [2] = min(F k [1] + LI 0 k , F k [3] + LI 0 k+LI 1 k ) (18)F k+1 [3] = min(F k [1] + RI k + LI 1 k , F k [3] + RI k )(19)B k−1 [0] = min(B k [0], B k [1] + RI k + LI 0 k+LI 1 k ) (20)B k−1 [1] = min(B k [2] + LI 0 k , B k [3] + RI k + LI 1 k )(21)B k−1 [2] = min(B k [0] + LI 1 k , B k [1] + RI k + LI 0 k )(22)B k−1 [3] = min(B k [2] + LI 0 k + LI 1 k , B k [3] + RI k )(23)RI k = LO 0 k+22 + LO 1 k+44 + M ch [k] (27)LI 0 k+22 = RO k + LO 1 k+44 + M ch [k] (28)LI 1 k+44 = RO k + LO 0 k+22 + M ch [k] (29)M dec = RO k + LO 0 k+22 + LO 1 k+44 + M ch [k]Acknowledgment(30)The authors would like to thank Mingrui Zhu for helpfuldiscussion on this research.Notes1. As shown in [2], this model and the algorithms developed inthis paper can be modified to work in sinusoidal carrier systemssuch as direct sequence spread spectrum system (DS/SS). In suchsystems, the model of (2) should be generalized to account for anunknown carrier phase, θ c . The approach suggested in [2] is tosearch over a finite set of carrier phase values.2. Note that this is the feedback polynomial. Viewed as a code, thegenerator is 1/(1 + D), which is an accumulator.ReferencesLO 0 k = min(F k [0] + B k+1 [1] + RI k + LI 1 k , F k [1]+ B k+1 [2], F k [2] + B k+1 [1] + RI k , F k [3]+ B k+1 [2] + LI 1 k ) − min(F k [0] + B k+1 [0],(24)F k [1] + B k+1 [3] + RI k + LI 1 k , F k [2]+B k+1 [0] + LI 1 k , F k [3] + B k+1 [3] + RI k )LO 1 k = min(F k [0] + B k+1 [1] + RI k + LI 0 k , F k [1]+B k+1 [3] + RI k , F k [2] + B k+1 [0], F k [3]+B k+1 [2] + LI 0 k ) − min(F k [0] + B k+1 [0],(25)F k [1] + B k+1 [2] + LI 0 k , F k [2] + B k+1 [1]+RI k + LI 0 k , F k [3] + B k+1 [3] + RI k )RO k = min(F k [0] + B k+1 [1] + LI 0 k + LI 1 k ,F k [1] + B k+1 [3] + LI 1 k , F k [2] + B k+1 [1]+LI 0 k , F k [3] + B k+1 [3]) − min(F k [0]+B k+1 [0], F k [1] + B k+1 [2] + LI 0 k , (26)F k [2] + B k+1 [0] + LI 1 k , F k [3] + B k+1 [2]+LI 0 k + LI 1 k )1. M.K. Simon, J.K. Omura, R.A. Scholtz, and B.K. Levitt, SpreadSpectrum Communications Handbook, McGraw-Hill, 1994.2. K.M. Chugg and M. Zhu, “A New Approach to Rapid PN CodeAcquisition using Interative Message Passing Techniques,”IEEE J. Select. Areas Commun., vol. 23, no. 51, June 2005.3. E.A. Homier and R.A. Scholtz, “Rapid Acquisition of Ultra-Wideband Signals in the Dense Multipath Channel,” in Digestof Papers, IEEE Conference on Ultra Wideband Systems andTechnologies, May 2002, pp. 105–109.4. M. Zhu and K.M. Chugg, “Iterative Message Passing Techniquesfor Rapid PN code Acquisition,” in Proc. IEEE MilitaryComm. Conf., Boston, MA, October 2003, pp. 434–439.5. I.D. O’Donnell, S.W. Chen, B.T. Wang, and R.W. Brodersen,“An Integrated, Low Power, Ultra-Wideband ReansceriverArchitecture for Low-Rate, Indoor Wireless Systems,” IEEECAS Workshop on Wireless Communications and Networking,September 2002.6. A. Polydoros and C.L. Weber, “A Unified Approach to SerialSearch Spread-Spectrum Code Acquisition,” IEEE Trans. Commununication,vol. 32, pp. 542–560, 1984.7. L. Yang and L. Hanzo, “Iterative Soft Sequential EstimationAssisted Acquisition of m-Sequence,” IEE Electronics Letters,vol. 38, no. 24, 2002, pp. 1550–1551.8. R.G. Gallager, “Acquisition of I-Sequences Using RecursiveSoft Sequential estimation,” IEEE Trans. Commununication,vol. 52, no. 2, Feb 2004 pp. 199–204.9. B. Vigoda, J. Dauwels, N. Gershenfeld, and H. Loeliger, “Low-Complexity lfsr Synchronization by Forward-only MessagePassing,” IEEE Trans. Information Theory, June 2003, submitted.
An Iterative Algorithm and Low Complexity Hardware Architecture 4110. S.W. Golomb, Shift Register Sequences, revised edition. AegeanPark Press, 1982.11. C. Berrou, A. Glavieux, and P. Thitmajshima, “Near ShannonLimit Error-Correcting Coding and Decoding: Turbo-Codes,”in Proc. International Conf. Communications, Geneva, Switzerland,pp. 1064–1070, 1993.12. C. Berrou and A. Glavieux, “Near Optimum Error CorrectingCoding and Decoding: Turbo-Codes,” IEEE Trans. Commununication,vol. 44, no. 10, pp. 1261–1271, October 1996.13. R.G. Gallager, “Low Density Parity Check Codes,”IEEE Trans. Information Theory, vol. 8, January 1962pp. 21–28.14. R.G. Gallager, Low-Density Parity-Check Codes. MIT Press,Cambridge, MA, 1963.15. D.J.C. MacKay and R.M. Neal, “Near Shannon Limit Performanceof Low Density Parity Check Codes,” IEE ElectronicsLetters, vol. 32, no. 18, August 1996 pp. 1645–1646.16. N. Wiberg, Codes and Decoding on General Graphs, Ph.D. dissertation,Linköping University (Sweden), 1996.17. R.J. McEliece, D.J.C. MacKay, and J.F. Cheng, “Turbo Decodingas an Instance of Pearl’s “Belief Propagation” Algorithm,”IEEE J. Select. Areas Commun., vol. 16, February 1998, pp.140–152.18. S.M. Aji, “Graphical Models and Iterative Decoding,” Ph.D.dissertation, California Institute of Technology, 1999.19. S.M. Aji and R.J. McEliece, “The Generalized DistributiveLaw,” IEEE Trans. Information Theory, vol. 46, no. 2, pp. 325–343, March 2000.20. F. Kschischang, B. Frey, and H.-A. Loeliger, “Factor Graphs andthe Sum-Product Algorithm,” IEEE Trans. Information Theory,vol. 47, Feb. 2001, pp. 498–519.21. K.M. Chugg, A. Anastasopoulos, and X. Chen, Iterative Detection:Adaptivity, Complexity Reduction, and Applications.Kluwer Academic Publishers, 2001.22. S. Benedetto and G. Montorsi, “Design of Parallel ConcatenatedConvolutional Codes,” IEEE Trans. Commununication, vol. 44,May 1996, pp. 591–600.23. S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara, “SerialConcatenation of Interleaved Codes: Performance Analysis, Design,and Iterative Decoding,” IEEE Trans. Information Theory,vol. 44, no. 3, May 1998, pp. 909–926.24. R.M. Tanner, “A Recursive Approach to Low ComplexityCodes,” IEEE Trans. Information Theory, vol. IT-27, September,pp. 533–547, 1981.25. S. Benedetto, D. Divsalar, G. Montorsi, and F. Pollara, “Soft-Input Soft-Output Modules for the Construction and DistributedIterative Decoding of Code Networks,” EuropeanTrans. Telecommun., vol. 9, no. 2, March/April, pp. 155–172,1998.26. J.S. Yedidia, J. Chen, and M. Fossorier, “Generating Code RepresentationsSuitable for Belief Propagation Decoding,” in Proc.40-th Allerton Conference Commun., Control, and Computing,Monticello, IL., October 2002.27. N. Santhi and A. Vardy, “On the Effect of Parity-Check Weightsin Iterative Decoding,” in Proc. IEEE Internat. Symp. InformationTheory, Chicago, IL., July 2004, p. 322.28. M. Schwartz and A. Vardy, “On the Stopping Distance and theStopping Redundancy of Codes,” IEEE Trans. Information Theory,2005, submitted.29. L.R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal Decodingof Linear Codes for Minimizing Symbol Error Rate,” IEEETrans. Information Theory, vol. IT-20, 1974, pp. 284–287.30. A.J. Viterbi, “Justification and Implementation of the MAP Decoderfor Convolutional Codes,” IEEE J. Select. Areas Commun.,vol. 16, February 1998, pp. 260–264.31. G. Masera, G. Piccinini, M.R. Roch, and M. Zamboni, “VLSIArchitectures for Turbo Codes,” IEEE Trans. VLSI, vol. 7, no. 3,1999.32. J. Dielissen and J. Huisken, “State Vector Reduction for Initializationof Sliding Windows MAP,” in 2nd Internation Symposiumon Turbo Codes & Related Topics, Brest, France, 2000, pp.387–390.33. S. Yoon and Y. Bar-Ness, “A Parallel MAP Algorithm forLow Latency Turbo Decoding,” IEEE Communications Letters,vol. 6, no. 7, 2002, pp. 288–290.34. A. Abbasfar and K. Yao, “An Efficient and Practical Architecturefor High Speed Turbo Decoders,” in IEEE 58th VehicularTechnology Conference, Vol. 1, 2003, pp. 337–341.35. A.P. Hekstra, “An Alternative to Metric Rescaling in Viterbi Decoders,”IEEE Trans. Commununication, vol. 37, no. 11, November1989.On Wa Yeung received the B. Eng. degree in Electronic Engineeringfrom the Chinese University of Hong Kong, Hong Kong in 1994 andMSEE from the University of Southern California (USC) in 1996. In1997–2003, he was a hardware engineer in Hughes Network Systems,San Diego, CA, designing hardware platforms for fixed wireless andsatellite terminals. He is currently working towards the Ph.D. degreein EE at USC. His research interests are in the areas of iterativedetection algorithms and their hardware implementation.oyeung@usc.eduKeith M. Chugg (S’88-M’95) received the B.S. degree (high distinction)in Engineering from Harvey Mudd College, Claremont, CA in1989 and the M.S. and Ph.D. degrees in Electrical Engineering (EE)from the University of Southern California (USC), Los Angeles, CAin 1990 and 1995, respectively. During the 1995–1996 academic year
Page 1: Journal of VLSI Signal Processing 4
Page 5 and 6: An Iterative Algorithm and Low Comp
Page 7: An Iterative Algorithm and Low Comp
Page 10 and 11: 34 Yeung and ChuggIterative Decoder
Page 12 and 13: 36 Yeung and ChuggIteration 0 Itera
Page 14 and 15: 38 Yeung and ChuggM chChannelMetric
Page 18: 42 Yeung and Chugghe was an Assista

An Iterative Algorithm and Low Complexity Hardware Architecture ...

Create successful ePaper yourself

Delete template?

Save as template?