An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data ...

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS250250200150STH = disabledEAF = 1200150STH = "S0001000"EAF = 0.86100100501 1.1 1.2 1.3 1.4 1.5 1.6x 10 4250501 1.1 1.2 1.3 1.4 1.5 1.6x 10 4250200150100STH = "S0010000"EAF = 0.76200150100STH = "S0100000"EAF = 0.03501 1.1 1.2 1.3 1.4 1.5 1.6x 10 4501 1.1 1.2 1.3 1.4 1.5 1.6x 10 4Fig. 21. Measured digital output of the activity-dependent ADC. The x-axis and y-axis represent the time in μs and the output code, respectively. Theasymmetric rejection of the background noise is due to the fact that only five bits were used to encode S TH .Relative ADC Power ConsumptionRelative Output Data Rate10.90.80.70.60.50.40.3σ n=100 mVrmsσ n=33.3 mVrmsσ n=133.3 mVrms0.20 50 100 150 200 25010080604020σ n=100 mV rmsσ n=33.3 mV rmsThreshold S TH(in codes)(a)σ n=133.3 mV rms00 50 100 150 200 250Threshold, S TH(in codes)Fig. 22. Relative reduction in power consumption (P max = 10.7 μW) andODR with different σ n and S TH .Higher is the K eff,vga , more power efficient is the VGA.Table II presents the comparison of the VGA with that inthree state-of-the-art NRSs.(b)V. CONCLUSIONWe presented an 8-to-1 bit, 1 MS/s SAR ADC in UMC0.13-μm CMOS technology. An energy efficient DAC switchingscheme was proposed, which consumes the lowest powerto date without using extra capacitors or clock cycles. TheDAC switching scheme consumes 37% less energy than thepresent state-of-the-art. For multichannel input, use of pingponginput sampling was emphasized to save power in VGAand reference buffer. The proposed ADC also consumes lowerpower in clock buffers as we employ clock of half of thesampling speed. Also the resolution of the ADC can be variedbased on the dynamic range to avoid unnecessary processingand save power.For neural recording application, the ODR was reducedusing the proposed activity-dependent A/D scheme, whichkeeps important spike features preserved in the ADC output.This scheme saves both power and area when compared tospike feature extraction schemes, which employ complicatedon-chip DSP. The savings in power consumption of the ADCand ODR due to the scheme are calculated and expressedin term of EAF. An experiment with the real neural datawas carried out to show the usefulness of the scheme forthe application. An emphasis was put on the requirement oflarge programmable voltage gain in the VGA for NRS. Thepresented VGA provides a voltage gain of 8 dB-35 dB ineight steps.The presented SAR ADC consumes 8.8 μW from 1 Vsupply and achieves ENOB of 7.7 bit for a near Nyquistinput at 1 MS/s speed. FlipDAC switching technique makesenergy consumption in the DAC small compared to digitalswitching energy. The DAC switching scheme will prove tobe more beneficial in higher resolution and higher speed SARADCs where the DAC switching energy is more comparableto the digital switching energy. The ADC achieves a FoM of42.3 fJ/conversion. The power consumption in the ADC is