Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers

2D to 3D
MOS Technology Evolution
for Circuit Designers
Alvin Loke 1 , Ray Stephany 1 , Andy Wei 2 ,
Bich-Yen Nguyen 3 , Tin Tin Wee 1 ,
John Faricelli 1 , Jung-Suk Goo 2 ,
and Shawn Searles 1
1
Advanced Micro Devices
2
GlobalFoundries
3
Soitec
AUTHORIZATION
All copyrights to the material contained in this document are retained by us and our employers.
IEEE Solid-State Circuits Society – Delhi and Bangalore Distinguished Lecturer Colloquia

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 1

CMOS Scaling Still Alive…
Intel 22nm
tri-gate finFET
in production
Keating, Synopsys [1]
• Leading foundries frantically after manufacturable tri-gate
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 2

…But Slowing Down
• MOS performance improves with scaling
• BUT $$$ (as always) is THE main reason to scale
• Each new CMOS node shrinks dimensions by 2
• Same functionality in half the area
• Cost-per-functionality if area reduction exceeds
increased cost-per-area for more complex manufacturing
• Enables more functionality on a single die
• Fewer dies fewer packages lower cost
• Moving to planar 20nm CMOS is not so obvious
• Wafer cost is getting prohibitive, e.g., double patterning
• Fully-depleted option (e.g., tri-gate fins) is compelling to
enable low-power operation, especially with high demand
for portable ICs
• 28nm likely to be around for a while
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 3

Bleeding-Edge IC Development
• Design concurrently developed with technology to shorten
time-to-market
• Multiple models
• Multiple iterations
• Design feedback
• Earlier start/finish
Model Uncertainty
Speculative
Models
Test Chip
Initial
Design
Silicon-Influenced
Models
Updated
Design
Silicon-Based
Models
Final
Design
Time
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Bair, AMD [2]
Slide 4

Why Should We (Designers) Care?
• Models bridge the technology and design worlds
• The truth about our models
– Speculative and inherently uncertain
– Cannot assume they are accurate and to 10 sig figs
– Primarily tailored to logic, not analog
– Limited to fab understanding of design usage of devices
– Intrinsically late to capture new effects, e.g., proximity
• We can design better circuits when we understand
– the technology that our models are attempting to capture
– the technology effects that are not in our models
– What the fab prioritizes
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 5

Our Objective
• Understand how MOSFET structure has evolved
• Learn about enabling technologies
• Understand why it has evolved this way
L=35nm
SiGe
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 6

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 8

The Basis of All CMOS Digital ICs
inputs
pull-up
logic
t
delay
Q
I
load
eff
C
load
I
eff
V
DD
pull-down
logic
P
dynamic
C
load
V
2
DD
f
• Charging and discharging a capacitor… very quickly!
• For shorter delay and lower power
• C load reduce parasitics (wires, gates, junctions, …)
• V DD reduce logic swing
• I eff move charge quicker
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 8

Important MOSFET Current Parameters
I D
(mA)
1.5
1.0
28nm, VDD=1.0V
IDhigh
IDsat
V GS
1.0V
IDeff
0.7V
0.5
IDlow
0.5V
IDlin
IDoff
0.0
0.2V
0.0 0.2 0.4 0.6 0.8 1.0
V (V) DS
typical analog usage
V GS =V T to V T +0.2V
IDeff estimates effective
inverter current drawn
during switching event,
more realistic and way
less optimistic than IDsat
IDlow IDhigh
IDeff
2
VDD
IDlow IDVGS
, V
2
IDhigh IDV
GS
V
DD
, V
DS
DS
V
DD
V
2
DD
Na et al., IBM [3]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 9

Flatband Condition (V GS =V FB )
V BS
V DS
M O S
V GS
silicon
surface
E C
silicon
surface
poly gate
E F
q s
q b
E i
E F
E V
p + body
contact
n +
source
n +
drain
q s = q b
p-type
body
source-tobody
depletion
drain-to-body
depletion
Energy
Band
Diagram
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 10

Onset of Surface Inversion ( s =0)
V BS
V DS
M O S
V GS
surface
undoped
+
poly gate
+ +
+
q b
q s
q s = 0
p + body
contact
n +
source
– – –
–
n +
drain
p-type
body
+ charge terminating on – charge
Energy
Band
Diagram
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 11

Onset of Strong Surface Inversion
(V GS =V T )
V BS
V DS
M O S
V GS
inversion
layer
poly gate
+ + + + + + + + + + +
+ + + + + + + + + + + +
qV T
s
q s
q b
p + body
contact
p-type
body
n +
source
V
T
– – – – – – – – – – – –
– – – –
– – –
– – – –
V
FB
2
b
Q
C
dep
ox
n +
drain
q s = q b
Energy
Band
Diagram
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 12

Lower the Surface Barrier
V GS = 0
V DS = 0 (no current)
Large source barrier
(back-to-back diodes)
electron
current
V GS V T
V DS = 0 (no net current)
Source barrier lowered
Surface is inverted
V GS > V T
V DS > 0 (net source-to-drain current flow)
Carriers easily overcome source barrier
Surface is strongly inverted
Sze [4]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 13

Quantifying Charge to Move s by 2 b
gate
body
+ – – – – –
+
– – – – –
+ +
E
0
qNx d
Si
V
2 b
0
2
b
–
–
x d
x d
qN
Q
E dA
x d
V
qNx
2
E
Si
2
d
• Assume uniformly
doped p-type body
• How much body must
be depleted to reach
strong inversion?
2
Si
2
b
qN
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
x
x
Si
dx
x
d
Qdep qNx d
1
N
Slide 14

The Roads to Higher Performance
source
channel
drain
Decrease L – steepen the hill
source
channel
drain
lithography
scaling
Increase µ – move carriers faster
source
channel
drain
strain engineering
Must contain parasitic
R & C from undoing all
the I FET gains
Increase C ox – move more carriers
source
channel
drain
high-K dielectric
metal gate
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 15

Short-Channel Effects (SCEs)
L
V T
gate
n +
source
n +
drain
L
V T
source-to-body
depletion
drain-to-body
depletion
DIBL
V DD not scaling as aggressively as L
Higher channel electric fields
– Velocity saturation
– Mobility degradation
V DS
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 16

Overcoming Short-Channel Effects
Improve gate electrostatic control of
channel charge
• Higher body doping but higher V T
• Shallower source/drain but higher R s
• Thinner t ox but higher gate leakage
• High-K dielectric to reduce tunneling
• Metal gate to overcome poly depletion
• Fully-depleted structures (e.g., fins)
Stressors for mobility enhancement
1
x j
doping
n +
source
gate
n +
drain
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 17

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 18

The Roads to Higher Performance
source
channel
drain
Decrease L – steepen the hill
source
channel
drain
lithography
scaling
Increase µ – move carriers faster
source
channel
drain
strain engineering
Increase C ox – move more carriers
source
channel
drain
high-K dielectric
metal gate
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 19

Let There Be Light
Resolution = k 1
NA
• Tooling has traditionally driven resolution scaling
• Shorter : 436nm 365nm 248nm 193nm
• Higher NA lenses capping at 1.35
/ NA (nm)
• Both and NA have hit
a wall
• No new litho tool for
22/20nm nodes
(EUV not primetime yet)
• Single patterning limited
to ~80nm pitch
Wei, GlobalFoundries [5]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 20

Step-and-Scan Projection Lithography
• Slide both reticle & wafer across narrow
slit of light
• Only need high-NA optics orthogonal to
scan but now high-precision constantspeed
stages to move mask & wafer
Slit Source
Excimer Laser
KrF (248nm) or ArF (193nm)
• Cheaper than high-NA 2-D optics
• 6” x 6” physical reticle size (4× reduction)
• 25 x 33mm or 26 x 32mm field size
• Weak intensity of deep-UV source
requires sensitive chemically-amplified
resists for better throughput
• Enables dose mapping (adjust light dose
during scan to compensate for loading)
Nikon [6]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers Slide 21

Immersion Lithography
• Remember oil immersion microscopy in biology class?
• Extend resolution of refractive optics by squirting water
puddle on wafer surface prior to exposure
• n water ~1.45 vs. n air ~ 1
• Tedious but EUV is not primetime yet
Resolution = k 1
NA
NA = n sin = d / 2 f
water
light
lens
12-inch
wafer
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 22

Lithography Misalignment / Overlay
• Mask misalignment tolerance is not keeping pace with gate
CD scaling
• ASML has near monopoly on lithography tools largely
because of good overlay control (global zero layer patterns)
• Many layout enclosure & spacing rules not scaling with CD
• Examples:
• Poly overhang beyond active
• Contact spacing to poly
• Active enclosure around contact
• Metal enclosure around vias
• Layout for matching must be robust against overlay errors
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 23

Resolution Enhancement Technology
Wei, GlobalFoundries [5]
Resolution = k 1
NA
Rayleigh k 1 Factor
• Reducing k 1 is the remaining ticket to better resolution
• Attack problem from all fronts: mask, source & wafer
• Imposes significant restrictions on layout design rules
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 24

Mask – Optical Proximity Correction
• Sharp features are lost because diffraction attenuates higher
spatial frequencies (mask behaving as low-pass optical filter)
• Compensate for diffraction effects when feature sizes

Mask – Sub-Resolution Assist Features
SRAFs
• Difficulty to concurrently print dense and isolated lines
• SRAFs are features intentionally placed on mask that are
too small to print but provide enough diffraction to make
isolated features print well
• Imposes forbidden pitches on layout
Sivakumar, Intel [8]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 26

Mask – Phase Shift
• Create differential optical path length to invert electric field
of adjacent features
Sivakumar, Intel [8]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 27

Source – Off-Axis Illumination
-2
• Offers significant boost in resolution
• Imposes restrictions in orientation & pitch
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Sivakumar, Intel [8]
Slide 28

Source – Aperture Shape Optimization
• Keep pixels that contribute to image enhancement
• Discard pixels that degrade image contrast
Sivakumar, Intel [8]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 29

Double Patterning Pitch Division
Litho-Etch-Litho-Etch (LELE)
Litho-Freeze-Litho-Etch (LFLE)
Sivakumar, Intel [8]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 30

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 31

130nm MOSFET Fabrication
1 STI
oxide
p-Si substrate
Shallow Trench Isolation
4
halos
Source/Drain Extension
& Halo Implantation
2 n-well p-well
5
Well Implantation
gate oxide
Spacer Formation &
Source/Drain Implantation
silicide
3
Gate Oxidation &
Poly Definition
6
PMOS
NMOS
Salicidation
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 32

LOCOS Isolation – 350nm & Earlier
1
2
3
bird’s
beak
Deposit & pattern thin
Si 3 N 4 oxidation mask
Grow thermal field oxide
• Industry played lots of tricks to reduce width of bird’s beak &
reduce field oxide to active area topography
Depth of Focus Resolution / NA
Strip Si 3 N 4 mask
• Barriers to scaling: bird’s beak, topography for gate patterning
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 33

Shallow Trench Isolation – After 350nm
1
4
Deposit & pattern thin Si 3 N 4
etch mask & polish stop
CMP excess SiO 2
2
5
Etch silicon around active area –
profile critical to minimize stress
Recess SiO 2
Strip Si 3 N 4 polish stop
3
Grow liner SiO 2 , then deposit
conformal SiO 2 – void-free
deposition is critical
Advantages over LOCOS
• Reduced active-to-active
spacing (no bird’s beak)
• Planar surface for gate
lithography
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 34

Chemo-Mechanical Polishing (CMP)
wafer
(facing down)
wafer
carrier
optical
endpoint
detection
slurry
polishing
pad
in situ pad
conditioner
(critical)
polishing
table
oxide
CMP
• Balance between material
removal from chemical
reaction vs. mechanical
abrasion
• Scratches vs. poor planarity
• Polishing pad will flex to
track wafer undulations
• Pioneered by IBM –
leveraged expertise from
lens polishing
dishing
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 35

Topography Buildup is Costly Later
After STI
Oxide CMP
STI
After ILD0
Oxide CMP
(contact dielectric)
poly
metal shorts!!!
After Metal-1
Copper CMP
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 36

Consistent Pattern Density for CMP
• Ideal world for CMP: perfectly periodic pattern throughout wafer
• Dummification is key to minimize topography in any CMP process
• Add dummy patterns to open areas to minimize density variation
• Also critical to step dummy dies along wafer circumference
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 37

Well Implant Engineering
Retrograded well dopant profile
(implants before poly deposition)
Shallow/steep surface channel implant
• V T control
• Slow diffusers critical (In, Sb)
STI
oxide
p-well
STI
oxide
Substrate
Doping
Deeper subsurface implant
• Extra dopants to prevent subsurface
punchthrough under halos
• Prevent parasitic channel inversion on
STI sidewall beneath source/drain
• Faster diffusers (B, As/P)
Depth
substrate
background
Very deep high-dose implant
• Latchup prevention
• Noise immunity
• Faster diffusers (B, As/P)
Sequence implant to reduce ion channeling, especially for shallow implant
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 38

Gate Oxide Growth
• Need two gate oxide t ox ’s – thin for core FET & thick for I/O FET
1 2 3
Grow 1 st oxide gate
oxide
Strip oxide for core FET Grow 2 nd oxide
Si substrate
I/O FET
gate oxide
core FET
gate oxide
• Oxide is grown, not deposited
• Need high-quality Si-SiO 2 interface with low Q f & D it
• Gate oxide is really made of silicon oxynitride (SiO x N y )
• Nitrogen prevents boron diffusion from p+ poly to channel
• Improves GOI (gate oxide integrity) reliability
• Side benefit – increased ox
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 39

Poly Gate Definition
• Gate CD way smaller than lithography capability
resist
anti-reflection
layer (ARL)
poly-Si
gate
oxide
poly
gate
Si substrate
1 Pattern resist
2 Trim resist
3
(oxygen ash)
Etch gate stack
• Process control is everything – resist & poly etch chamber
conditioning is critical (don’t clean residues in tea cups or woks)
• Trim more for smaller CD (requires tighter control)
• Less trimming if narrower lines can be printed immersion litho
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 40

Multi-Chamber Cluster Tools
• Gate oxide no longer furnace grown
• Pre-oxidation clean, gate oxidation
& poly/ARL deposition performed in
separate chambers without breaking
vacuum
• Better thickness & film composition
control (native SiO 2 grows instantly
when exposed to air)
• Fast – minutes-seconds per wafer
vs. hours per wafer batch
• Economically feasible with trend
towards larger wafer sizes
Top
View
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 41

1
Channel & Source/Drain Engineering
self-aligned source/drain
extension implant (n-type)
poly
gate
3
dielectric spacer
formation
poly
gate
p-well
p-well
self-aligned high-tilt
halo/pocket implant (p-type)
self-aligned source/drain
implant (n-type)
2
poly
gate
4
poly
gate
p-well
halos
p-well
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 42

Benefits of Halo and Extension
Resulting structure
• Less short-channel effect
• Shallow junction where
needed most
• Low junction capacitance
poly
gate
halos
halos
Not to be confused with LDD in I/O FET
• Same process with spacers but Iightly doped drain (LDD) is
used for minimizing peak electric fields that cause hot
carriers & breakdown
• Extensions need to be heavily doped to minimize series
resistance
Different halo & extension/LDD implants for each FET variant
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 43

Feed-Forward Manufacturing Control
• Adjust resist trim ash time to compensate for poly photo variations
poly
shorter
ash time
longer
ash time
• Adjust halo dose to compensate for poly etch variations
(modulate position of pn junction where counter-doping occurs)
higher
halo dose
well
lower
halo dose
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 44

Rapid Thermal Processing (RTP)
Temperature
RTP
Temperature
Furnace
substantial
ramp times
Time
Time
• Initially developed for short anneals
• Impossible to control short thermal cycles in furnaces
• Want minimum diffusion for shallow & abrupt junctions
• Process steps:
• Annealing repair implant damage, activate dopants
• Oxidation gate oxide
• Nitridation spacers, ARL
• Poly deposition gate
• RTP in single-wafer multi-chamber cluster tools
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 45

Non-CMP Density Effects – RTA
Before
Optimization
After
Optimization
Poly Layout Extraction
• Poly density impacts surface
heat absorption & anneal
temperature uniformity
• Non-uniform anneal results
in non-uniform dopant
activation and device
variation
Temperature Simulation
Auth, Intel [9]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 46

Self-Aligned Silicidation (Salicidation)
• Need to reduce poly & diffusion R s , or get severe I FET degradation
poly
1
diffusion
STI
well
Deposit sicilide metal (Ti, Co, Ni)
3
Strip unreacted metal
2
4
RTA1 (low temperature)
Selective formation of metal
silicide from metal reaction with Si
RTA2 (high temperature)
Transforms silicide into low-
phase by consuming more Si
•TiSi x CoSi x Ni/PtSi x
• Scaling requires smaller grain size to minimize R s variation
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 47

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 48

Constant-Current V T Measurement
• Onset of strong inversion near
impossible to measure
log I DS
high V DS low VDS
• Sweep log I DS vs. V GS
• Find V GS when I DS crosses
user-specified threshold I 0
normalized to W/L
I 0 ×W/L
DIBL
• Foundry-specific I 0 ~ 10 to 500 nA
• No physical connection to
“fundamental” V T definition
V Tsat V Tlin
V T
V GS
I
DS
I
0
W
L
drawn
drawn
V GS
Loke et al., AMD [10]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 49

Not So Fundamental After All
M O S
qV T
f s
qf s
inversion
layer
q b
q s = q b
Energy
Band
Diagram
V
T
V
FB
2
• Body doping has increased by 2–3
orders of magnitude over the decades
• Surface way more conductive at strong
inversion condition using “fundamental”
V T definition
• What matters is how much OFF leakage
you get for a given ON current
• IDoff vs. IDsat (or IDeff) universal plots
have become more useful to summarize
device performance
b
Q
C
dep
ox
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 50

log (I DS )
I OFF1
I OFF2
V T1 V T2
I OFF –I ON Universal Plots
I ON2
V DD
I ON1
V GS
OFF Leakage Current (nA/m)
Comparison of 90nm Technology Foundry Vendors
1000.0
100.0
10.0
1.0
0.1
1.0V
1.2V
PMOS
1.0V
1.2V
NMOS
0 200 400 600 800 1000 1200
ON Drive Current (A/m)
• High I ON high I OFF & low I ON low I OFF
• OFF leakage prevents V T from scaling with gate length
• Several V T ’s enable trade-off between high speed vs. low leakage
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 51

Subthreshold Leakage
• MOSFET is not perfectly OFF below V T
• V G s lower source-to-channel barrier
• Gradually more carriers diffuse from source to drain
• Capacitive divider between gate and undepleted body
source
s
V
G
V G
V B
C
ox
Cox
C
Si
V G
drain
s
gate
C ox
source
drain
body
C Si
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 52

Subthreshold Slope
• V G needed for 10 change in current
V G
S
k T
q
B
ln 10
C
ox
C
C
ox
Si
s
C ox
S
mV / dec
C
C
C
ox Si
60 at 25°C
ox
V B
C Si
• Planar 28nm: S = 100–110mV/dec at 25°C
• Want tight coupling of V G to s but have to overcome C Si
• Large C ox thinner gate oxide, HKMG
• Small C Si lower body doping, FD-SOI, finFET
• Get diode limit when C ox & C Si 0 (η = 1)
• Reducing S enables lower V T , V DD & power for same I OFF
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 53

Drain-Induced Barrier Lowering (DIBL)
• OFF leakage gets worse at higher V D
• E field from drain charge terminating in body, reducing gate
charge required to reach V T
• Characterized as V T reduction for some V D
• Planar 28nm: 150–160mV for V D =1V
• Reducing DIBL also enables lower V DD & power for same I OFF
source
gate
+ + + + + + + +
– –
–
– –
–
– –
–
– –
– –
–
drain
+ + +
E field
source
reduction of barrier height
at edge of source
drain
V DD
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 54

3-Way Competition for Body Charge
What’s happening to surface
potential?
V B
p-well
source
V G
gate
V D
drain
source
V G
source
|V B |
gate control
(what we want)
drain
body
effect
DIBL
drain
drain
V D
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 55

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 56

Partially-Depleted Silicon-On-Insulator
STI
STI
buried oxide
substrate
•Pros
• Low junction area capacitance
•No V T increase for stacked FETs
•4 lower SRAM soft-error rate
• Body isolation from substrate noise
• Simpler isolation process, reduced well proximity effect
• Cons
• Body hysteresis effect – floating body gets kicked around
• Requires conservative margining for digital timing
• Major pain for analog/mixed-signal design
• Substrate heating – buried oxide is good insulator
• More expensive substrate, and from a single supplier
STI
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 57

Making SOI Starting Material
• Challenge: making defect-free single-crystalline SOI layer on buried oxide
1
Si substrate
Oxidize Si wafer
reuse as
substrate
2
Si substrate
H +
4
Si substrate
Implant hydrogen
(protons)
Smart Cut
3
Si substrate
H +
5
SOI layer
buried oxide
Si substrate
Flip & bond to another
oxidized wafer
Si substrate
Anneal & polish
Soitec [11]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers Slide 58

The Dreaded Hysteresis Effect
• Floating body is coupled to source, gate, drain & body
• Body voltage has memory or history of other terminals,
analogous to intersymbol interference in wireline I/O
• Floating body voltage noise V T noise I D noise
V G
poly
gate
V D
n+
source
n+
drain
p-well
buried
oxide
substrate
V SUB
undepleted
floating body
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 59

All About Impedance Division
V S
V G
V D
n+
source
Z S
Z G
V B
Z SUB
Z D
p-well
n+
drain
buried
oxide
substrate
V SUB
V
B
V
D
Z
D
ZG
|| ZS
|| Z
Z || Z || Z
V
S
G
Z
S
S
D
SUB
SUB
ZD
|| ZG
|| Z
Z || Z || Z
G
V
SUB
G
SUB
Z
G
ZD
|| ZS
|| Z
Z || Z || Z
V
D
SUB
Z
S
SUB
SUB
SUB
ZD
|| ZG
|| ZS
Z || Z || Z
D
G
S
• Z SUB

Body-Tied PD-SOI MOSFET (T-Gate)
• Enables body connection to undepleted FET well
• High R body and extra C gate limits bandwidth of body connection
• NMOS example
p + diffusion
p + body-tie
Poly gate
SOI active
island
p +
n + n +
n +
source
n +
drain
p-well
Lateral connection to
undepleted p-well
n + diffusion
body node
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 61

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 62

The Roads to Higher Performance
source
channel
drain
Decrease L – steepen the hill
source
channel
drain
lithography
scaling
Increase µ – move carriers faster
source
channel
drain
strain engineering
Increase C ox – move more carriers
source
channel
drain
high-K dielectric
metal gate
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 63

Mechanical Stresses & Strains
Stress
Tension
(positive stress)
Force
Area
vs.
Strain
0
Compression
(negative stress)
atomic spacing > equilibrium spacing
atomic spacing < equilibrium spacing
• Stretching / compressing FET channel atoms by as little as 1%
can improve electron / hole mobilities by several times
• Strain perturbs crystal structure (energy bands, density of states,
etc.) changes effective mass of electrons & holes
• Increase I ON for the same I OFF without increasing C OX
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 64

Longitudinal Uni-Axial Strain
tension (stretch atoms apart) faster NMOS
compression (squeeze atoms together) faster PMOS
• Most practical means of incorporating strain for mobility boost
• Want 1-3GPa (high-strength steel breaks at 0.8GPa)
• How? Deposit strained materials around channel
• Material in tension wants to relax by pulling in
• Material in compression wants to relax by pushing out
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 65

Transferring Strain from Material A to B
A
B
A
A
B
A
more A
A
B
A
limited
scalability
less B
need short
channel
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 66

Ways to Incorporate Uni-Axial Strain
• NMOS wants tension, PMOS wants compression
• Un-Intentional (comes for free)
• Shallow Trench Isolation – NMOS / PMOS
• Intentional (requires extra processing)
• Stress Memorization Technique – NMOS
• Embedded-SiGe Source/Drain – PMOS
• Embedded-SiC Source/Drain – NMOS
• Dual-Stress Liners – NMOS & PMOS
• Strain methods are additive
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 67

Shallow Trench Isolation (STI)
NMOS & PMOS
• STI oxide under compression
• High-Density Plasma CVD SiO 2 process (alternating deposition/etch)
deposits intrinsically compressive oxide for good trench fill
• 10 CTE mismatch between Si & SiO 2 increases compression when
cooled from deposition temperature
• Migrated to High Aspect Ratio Process (HARP) fill in recent nodes
less compressive oxide
Plummer et al., Stanford [7] Bianchi et al., AMD [12]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers Slide 68

Stress Memorization Technique (SMT)
NMOS
1
Amorphize poly & diffusion
with silicon implant
2
3
tensile
Deposit tensile nitride
Anneal to make nitride more
tensile and transfer nitride
tension to crystallizing
amorphous channel
I off (A/µm)
10 -5
10 -6
control
10 -7
10 -8
10 -9
disposable
tensile nitride
stressor
600 800 1000 1200 1400
I on (µA/µm)
4
Remove nitride stressor
(tension now frozen in diffusion)
Chan et al., IBM [13]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 69

Periodic Table Trends
lattice spacing
bandgap
• Compound semiconductor like Si x Ge 1-x has lattice spacing &
bandgap between Si & Ge
• Same idea with Si x C 1-x
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 70

Embedded-SiGe Source/Drain (e-SiGe)
PMOS
• SiGe constrained to Si lattice will be in
compression
• Compressive SiGe source/drain
transfers compression to Si channel
L=35nm
SiGe
1
P
Etch source/drain recess
Chan et al., IBM [13]
10 -7 600
2
SiGe
P
SiGe
Grow SiGe epitaxially in
recessed regions
I off
(A/µm)
10 -8
• e-SiC is similar but introduces tension instead
• Epitaxial SiC much tougher to do than SiGe
10 -9
200 300 400 500 700
I on (µA/µm)
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 71

Dual-Stress Liners
NMOS & PMOS
• Deposit tensile/compressive PECVD SiN (PEN) liners on N/PMOS
• Liner stress is dialed in by liner deposition conditions (gas flow,
pressure, temperature, etc.)
TPEN for NMOS
CPEN for PMOS
tensile
compressive
tensile
compressive
Chan et al., IBM [13]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers Slide 72

Strain Relaxation
When materials of different strain come together…
Material A Tensile
Material B Compressive
interface
• Both materials will relax at the interface
• Extent of relaxation is gradual, depends on distance from interface
• No relaxation far away from interface
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 73

Strain Depends on Channel Location
• SA, L & SB specify where channel
is located along active area
SA L SB
• Critical for modeling device
mobility change due to STI,
SMT & e-SiGe/e-SiC
• Strain at source & drain ends
of channel may be different
• Important consideration for
matching, e.g., current mirrors
STI
effect
only
Xi et al., UC Berkeley [14]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 74

Longitudinal DSL Proximity
• Opposite device type nearby in longitudinal direction reduces
impact of stress liner mutually slow each other down
• Opposite PEN liner absorbs/relieves stress introduced by PEN
PMOS Longitudinal Proximity
CPEN
TPEN
hn_str_wnwp_infp-11-15
PMOS
NMOS
1.05
1
0.95
CPEN
TPEN
Ieff Ratio
0.9
0.85
0.8
Data
Model
PMOS
NMOS
0.75
0.7
0 0.2 0.4 0.6 0.8 1 1.2
WNWP Long. Distance (um )
Faricelli, AMD [15]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 75

Transverse DSL Proximity
• Both NMOS & PMOS like tension in transverse direction, unlike
longitudinal direction
• NMOS near PMOS in width direction helps PMOS, hurts NMOS
desired
NMOS
strain
CPEN
CPEN
PMOS
PMOS Transverse Proximity
1.06
1.04
desired
PMOS
strain
PMOS
NMOS
TPEN
NMOS
Norm alized Ideff
1.02
1
0.98
0.96
0.94
0.92
0.9
0.88
0 0.2 0.4 0.6 0.8 1 1.2
Transverse Distance
Data W=0.4
Model W=0.4
Data W=1.25
Model W=1.25
TPEN
Faricelli, AMD [15]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 76

A
Pop Quiz
Which FET has more channel strain?
P
1
SiGe
SiGe vs.
B
SiGe
P
SiGe
B. Extending SiGe source/drain transfers more compression to channel
A
TPEN
2 vs.
N
TPEN
CPEN CPEN CPEN
CPEN
B
N
A. Shorter channel feels more surrounding stresses – short L vs. long L
A
B
TPEN
N
vs.
TPEN
3
CPEN CPEN CPEN
CPEN
N
B. Extending PEN liner transfers more stress to channel
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 77

Well Implant Proximity Effect
• V T magnitude if FET is too close to well implant resist edge
• Dopant ions scatter off resist sidewall into active during implant
• Not issue in SOI since well implant resist masks are short
• Symmetric spacing to well now critical for FET matching
high-energy
well implant
V T, (V)
90nm
Core NMOS
active
tall
resist
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Average Distance Between MOS
Channel & Well Mask Edge
Hook et al., IBM [16]
Sheu et al., TSMC [17]
Slide 78

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 79

The Roads to Higher Performance
source
channel
drain
Decrease L – steepen the hill
source
channel
drain
lithography
scaling
Increase µ – move carriers faster
source
channel
drain
strain engineering
Increase C ox – move more carriers
source
channel
drain
high-K dielectric
metal gate
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 80

Direct Tunneling Gate Leakage
• t ox had to scale with channel
length to maintain gate control
• Less SCE
• Better FET performance
• Significant direct tunneling for t ox
< 2nm
• High-K gate dielectric achieves
same C ox with much thicker t ox
Gate Leakage (A/cm 2 )
10 4 High Performance
Low Power
SiO 2 Trendline
10 3
10 2
10 1
10 0
10 -1
10 -2
10 -3
10 -4
10 -5
McPherson, Texas Instruments [18]
Nitrided oxide
0 5 10 15 20 25 30
EOT (Å)
EOT = Equivalent Oxide Thickness
C
ox
t
gate
gate
ox
EOT
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 81

Poly Depletion & Charge Centroid
Dielectric Only Half the Story
poly depletion
(band bending)
surface charge centroid
few Å’s away
from oxide interface
C ox
poly-Si
gate
gate charge centroid
few Å’s away from
oxide interface
p-well
1.5nm (15Å)
gate
oxide
Si
substrate
n + poly gate
gate
oxide
Wong, IBM [19]
• Even heavily-doped poly is a limited conductor
• Discrepancy between electrical & physical thicknesses since charge
is not intimately in contact with oxide interface
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers Slide 82

Enter High-K Dielectric + Metal-Gate
• High-K Dielectric (HK)
• Hf-based material with K~20–30 (Zr-based also considered)
• Need to overcome hysteretic polarization
• High deposition temperature for good film quality
• Metal-Gate (MG)
• Thin conductive film intimately in contact with high-K dielectric
to set gate work function M V FB V T
• Want band-edge M , i.e., NMOS @ E C & PMOS @ E V
(just like n + poly & p + poly) different MG for NMOS & PMOS
• Typically complex stack of different metal layers secret sauce
• Conductive fill metal on top of M -setting metal-gate
• Key challenges
• INTEGRATION, INTEGRATION, INTEGRATION
• M shifts when exposed to dopant activation anneals
• Getting the right V T for both NMOS & PMOS
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 83

Atomic Layer Deposition
• Deposit monolayer at a time using sequential pulses of gases
• Introduce one reactant at a time & purge before introducing next
reactant
• Key to precise film thickness control of HKMG stack
• e.g., SiO 2 (SiCl 4 +H 2 O) HfO 2 (HfCl 4 +H 2 O) TiN (TiCl 4 +NH 3 )
Introduce pulse of HfCl 4 gas
repeat cycle for
desired number
of monolayers
Surface reaction to form HfO 2
Monolayer adsoprtion of HfCl 4
Introduce pulse of H 2 O gas
ICKnowledge.com [20]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 84

HK-First / MG-First Integration
1 2
3
4
Deposit HK
Deposit MG1
Pattern MG1
Deposit MG2
Pattern MG2
Deposit gate
Pattern gates /
MGs / HK
Implant/anneal S/ D
Form silicide
Deposit/CMP ILD0
Form contacts
• Obvious extension of poly-Si gate integration
• Seems obvious & “easy” at first but plagued with unstable work
function when HKMG is exposed to activation anneals
• Especially problematic with PMOS V T coming out too high
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 85

GlobalFoundries 32nm-SOI
NMOS
PMOS
epi-cSiGe to
set channel
M
IDoff (nA/µm)
poly/
SiON
+35%
HKMG
IDoff (nA/µm)
poly/
SiON
+25%
HKMG
IDsat (µA/µm)
IDsat (µA/µm)
Horstmann et al., GlobalFoundries [21]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 86

HK-First / MG-Last Integration
1 2
3
4
Deposit HK / gate
Pattern gate / HK
Implant/anneal S / D
Form silicide
Deposit ILD0
CMP ILD0 to expose
top of gate
Remove gate
Deposit MG1
Pattern MG1
Deposit MG2
Pattern MG2
Deposit gate-fill
CMP gate-fill / MGs
Deposit more ILD0
Form contacts
• High thermal budget available for middle-of-line
• Low thermal budget for metal gate more gate metal choices
• Enhanced strain when sacrificial poly is removed & resulting
trench is filled with gate fill metal
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 87

Intel 45nm
NMOS
PMOS
Auth et al, Intel [9]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 88

HK-Last / MG-Last Integration
1 2
3
4
Deposit oxide / gate
Pattern gate / oxide
Implant/anneal S / D
Deposit ILD0
CMP ILD0 to expose
top of gate
Remove gate/oxide
Deposit HK
Deposit MG1
Pattern MG1
Deposit MG2
Pattern MG2
Deposit gate-fill
CMP gate-fill / MGs
Deposit more ILD0
Pattern contacts
Form silicide
Form contacts
• Same advantages as HK-first / MG-last integration
• Overcomes EOT scaling limitations in HK-first / MG-last
• Need to postpone silicidation to after contact etch
• Need trench contacts to accommodate silicide metal deposition
• DSL relax & no longer useful since contacts cut through FET width
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 89

Intel 32nm
Packan et al, Intel [22]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 90

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 91

What Does Fully-Depleted Really Mean?
• Consider what happens when SOI layer thins down
fully-depleted when turned on
source
drain
source
drain
buried p-well oxide
depletion
region
substrate
p-well
depletion
region
substrate
• Conservation of charge cannot be violated
• So once body is fully depleted, extra gate charge must be balanced
by charge elsewhere, e.g., beneath buried oxide
• If substrate is insulator, then charge must come from source/drain
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 92

Maintain
IDsat & IDoff
Benefits of Lower DIBL & S
Same S
Lower DIBL
Lower S
Same DIBL
IDoff
log (I DS )
V Tsat V Tlin
V DD
IDsat
IDlin
V GS
IDoff
log (I DS )
V Tsat V Tlin
log (I DS )
IDsat
IDlin
IDoff
V
V GS
DD
V Tsat V Tlin
V DD
IDsat
IDlin
V GS
• Fully-depleted options
• Planar: FD-SOI, Bulk with retrograded well
• 3-D: FinFET or Tri-Gate – SOI or Bulk
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 93

The Big Deal with Lower DIBL
Higher performance for the same IDsat & IDoff
L. Wei et al, Stanford [23]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 94

Body Thickness for Fully-Depleted
x
d
2 Si
2
b
qN
x d
x d (nm)
1000
100
10
fully
depleted
partially
depleted
p-well
depletion
region
substrate
1
10 15 10 16 10 17 10 18 10 19 10 20
Body Doping, N (cm -3 )
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 95

Fully-Depleted Planar on SOI
• a.k.a. ET (Extremely Thin) or
UTBB (Ultra-Thin Body & BOX)
SOI to refer to very thin SOI
and Buried Oxide (BOX) layers
• SOI Si layer is so thin that
charge mirroring gate charge
comes from beneath BOX
buried oxide
substrate
K. Cheng et al, IBM [24]
thick to reduce series
resistance & apply stress
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 96

Thin BOX to Suppress SCE
T. Skotnicki, STMicroelectronics [25]
• Fully-depleted alone does not eliminate SCE
• Field lines from drain are still competing for body charge
• If body is fully depleted, these field lines cannot terminate in the
body since there’s no charge to terminate to no DIBL
• Charge elsewhere must be nearby or field lines from drain will
terminate on source charge
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 97

Performance Tuning with Backgate Bias
Yamaoka et al., Hitachi [26]
T. Skotnicki, STMicroelectronics [27]
• Like a “body effect” in planar bulk with C Si spanning SOI & BOX
• Backgate bias can modulate both NMOS and PMOS V T at 80mV/V
• Not option in finFETs but finFET subthreshold slope is better
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 98

Fully-Depleted Planar on Bulk
1 Low-doped layer for RDF reduction
(fully depleted)
2 V T setting layer for multiple V T devices
3 Highly-doped screening layer to
terminate depletion
4 Sub-surface punchthrough prevention
Reduced RDF for tighter V T
control & lower SRAM V DDmin
Fujita et al., Fujitsu & SuVolta [28]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 99

Random Dopant Fluctuation (RDF)
50
V T (mV)
40
30
20
minimum
length
NMOS
??
10
0
130nm 90nm 65nm 45nm
• RDF more prevalent with scaling since number of dopants is
decreasing with each MOS generation
• Why does RDF impact magically disappear in fully-depleted?
Auth, Intel [9]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 100

RDF in Conventional MOS
• Back to basics
• Conservation of charge
V E dx
• Electric field lines start at +ve charge & end at –ve charge
• Random locations of dopant atoms
• Lengths of field lines exhibit variation
• Integrated field (voltage or band bending) has V T variation
poly gate
n +
source
+ + + + + + + + + + + +
–
–
– –
–
–
–
–
–
– –
–
n +
drain
partially depleted
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 101

Why Fully-Depleted Eliminates RDF
• In fully-depleted SOI, field lines from gate cannot terminate in
the undoped body (no charge there)
• Mirror charges are localized beneath BOX
• Lengths of field lines have very tight distribution
• V T variation is small
• However, V T now very sensitive to dimensional variation,
e.g., SOI and BOX thickness
poly gate
undoped
poly gate
+ + + + + + + + + + + +
+ + + + + + + + + + + +
n +
source
–
–
–
–
– –
–
–
–
– –
–
n +
drain
n +
source
n +
drain
– – – – – – – – – – – –
partially depleted
fully depleted
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 102

Outline
• Part 1
– Motivation
– MOSFET & Short-Channel Fundamentals
– Lithography
– Getting to 130nm
– More MOSFET Fundamentals
– Partially-Depleted SOI
• Part 2
– Strain Engineering (90nm & Beyond)
– High-K / Metal-Gate (45nm & Beyond)
– Migrating to Fully-Depleted (22nm & Beyond)
– Tri-Gate FinFETs
– Conclusions
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 103

What is Fully-Depleted Tri-Gate?
32nm planar
22nm tri-gate
• Channel on 3 sides
• Fin width is quantized
(SRAM & logic implications)
Hu, UC Berkeley [29]
M. Bohr, Intel [30]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 104

Tri-Gate FinFETs in Production
32nm planar
22nm tri-gate
Truly impressive!!!
gate
fin
M. Bohr, Intel [30]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 105

Crystallography Basics
• Planes indexed by (xyz) of normal vector (Miller indices)
• Directions indexed by
• Negative indices denoted by bar on top of number
• Planes of interest: (100), (110), (111)
– Many planes are equivalent due to symmetry
x
direction
direction
direction
y
(100)
plane
z
(110)
plane
(111)
plane
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 106

Conventional Wafer Surface
Orientation & Channel Direction
x (100)
(100)
z (001)
0° notch
y (010)
• Wafer normal is (100), current flows in direction
• Tri-Gate FinFET: top surface (100), sidewall surfaces (110)
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 107

Mobility Dependence on Surface
Orientation & Direction of Current
NMOS
PMOS
top of fin
sidewalls of fin
sidewalls of fin
top of fin
Yang et al., IBM [31]
• Strain-induced mobility boost also depends on surface
orientation & channel direction – not as strong for current
along sidewalls vs. top of fin
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 108

Fin Patterning – Sidewall Image Transfer
1 Deposit & pattern sacrificial mandrel
mandrel
4
Etch target material using spacer
as hard mask
substrate to etch
2 Deposit & etch spacer
spacer
5 Remove spacer mask
3 Remove mandrel
hard mask
for patterning
• Standard approach for
patterning fins down to
60nm pitch (Intel 22nm)
• In principle, pitch can go
down to ~40nm without
double patterning
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 109

Process Flow Summary I
• Example shows tri-gate on SOI but
bulk flow is similar
• Pattern fins using SIT
• Deposit/CMP STI oxide
• Recess STI oxide by fin height
• Deposit, CMP & pattern poly
• Deposit spacer dielectric & etch,
leaving spacer on gate sidewalls
• Spacer must be removed on fin
sidewall
gate oxide on top &
both sidewalls of fin
fin
buried oxide
Paul, AMD [32]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 110

Process Flow Summary II
• Recess fins
• Grow Si epitaxially to merge fins
together for reduced source/drain
resistance
• Induce uni-axial channel strain by
growing e-SiGe or e-SiC
• Source/drain dopants come from
in situ doping during epi
• Deposit ILD0 & CMP to top of poly
• Do replacement-gate HKMG
module
• Deposit & pattern contact dielectric
• Form trench contacts (note
overlap capacitance to gate)
trench
contact
epi
growth
metal
gate
Paul, AMD [32]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 111

Some Tri-Gate Considerations
• Field lines of from gate
terminates at base of fins
• Fin base must be heavily
doped for fin-to-fin isolation
• Dimensional variation of fins
device variation
• Current density is not uniform
along width of device – V T &
S varies along sidewall
trench
contact
• Series resistance vs. overlap
capacitance
metal
gate
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 112

Intel 22nm TEM Cross-Sections
Single fin (along W)
NMOS (along L)
Epi merge (along W)
PMOS (along L)
Auth, Intel [33]
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 113

IDSAT (A/m)
1.E-02
1.E-03
1.E-04
1.E-05
1.E-06
1.E-07
Intel 22nm Performance at 0.8V
0.80V
0.05V
PMOS
VGS (V)
NMOS
0.80V
0.05V
1.E-08 SS ~72mV/dec SS ~69mV/dec
DIBL ~50 mV/V DIBL ~46 mV/V
1.E-09
-1.0 -0.6 -0.2 0.2 0.6 1.0
1000
IOFF (nA/m)
100
10
1
VDD = 0.8V
32nm
SP:
0.88 mA/m
HP:
1.26 mA/m
MP:
1.07 mA/m
0.1
0.6 0.8 1 1.2 1.4 1.6
IDSAT (mA/m)
1000
IOFF (nA/m)
100
10
1
NMOS
VDD = 0.8V
PMOS
32nm
SP:
0.78 mA/m
HP:
1.10 mA/m
MP:
0.95 mA/m
Auth, Intel [33]
0
0.6 0.8 1 1.2 1.4
IDSAT (mA/m)
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 114

Conclusions
• Digital needs will continue to drive CMOS scaling
but at slower pace
• Expect new learning in 20nm & 14nm as we cope
with fin design & layout
• SPICE models will lag to include new effects
• Designers with good technology knowledge are best
positioned for silicon success
• Exciting time to be designing
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 115

References I
[1] M. Keating, “Science fiction or technology roadmap: a look at the future of SoC design,” in SNUG San Jose Conf., Mar.
2010.
[2] L. Bair, “Process/product interactions in a concurrent design environment,” in Proc. IEEE Custom Integrated Circuits Conf.,
pp. 779782, Sep. 2007.
[3] M. Na et al., “The effective drive current in CMOS inverters,” in IEEE Int. Electron Devices Meeting Tech. Dig., pp. 121–
124, Dec. 2002.
[4] S.M. Sze, Physics of Semiconductor Devices (2 nd ed.), John Wiley & Sons, 1981.
[5] A. Wei, “Foundry trends: technology challenges and opportunities beyond 32nm,” in IEEE Vail Computer Elements
Workshop, Jun. 2010.
[6] www.nikon.com
[7] J. Plummer et al., Silicon VLSI Technology– Fundamentals, Practice and Modeling, Prentice-Hall, 2000.
[8] S. Sivakumar, “Lithography for the 15nm node,” in IEEE Int. Electron Devices Meeting Short Course, Dec. 2010.
[9] C. Auth, “45nm high-k + metal-gate strain-enhanced CMOS transistors,” in Proc. IEEE Custom Integrated Circuits Conf.,
pp. 379–386, Sep. 2008.
[10] A. Loke et al., “Constant-current threshold voltage extraction in HSPICE for nanoscale CMOS analog design,” in SNUG
San Jose Conf., Mar. 2010.
[11] www.soitec.com
[12] R. Bianchi et al., “Accurate modeling of trench isolation Induced mechanical stress effects on MOSFET electrical
performance,” in IEEE Int. Electron Devices Meeting Tech. Dig., pp. 117-120, Dec. 2002.
[13] V. Chan et al., “Strain for CMOS performance improvement,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 667–674,
Sep.2005.
[14] X. Xi et al., BSIM4.3.0 MOSFET Model – User’s Manual, The Regents of the University of California at Berkeley, 2003
[15] J. Faricelli, “Layout-dependent proximity effects in deep nanoscale CMOS,” in Proc. IEEE Custom Integrated Circuits
Conf., pp. 1–8, Sep.2010.
[16] T. Hook et al., “Lateral ion implant straggle and mask proximity effect,” IEEE Trans. Electron Devices, vol. 50, no. 9, pp.
1946-1951, Sep. 2003.
[17] Y. Sheu et al., “Modeling well edge proximity effect on highly-scaled MOSFETs,” in Proc. IEEE Custom Integrated Circuits
Conf., pp. 831–834, Sep. 2005.
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 116

References II
[18] J. McPherson, “Reliability trends with advanced CMOS scaling and the implications on design,” in Proc. IEEE Custom
Integrated Circuits Conf., pp. 405–412, Sep. 2007.
[19] P. Wong, “Beyond the conventional transistor,” IBM J. Research & Development, pp. 133–168, vol. 2-3, no. 46, Mar. 2002.
[20] www.ICKnowledge.com
[21] M. Horstmann et al., “Advanced SOI CMOS transistor technologies for high-performance microprocessor applications,” in
Proc. IEEE Custom Integrated Circuits Conf., pp. 149–152, Sep. 2009.
[22] P. Packan et al., “High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors,” in
IEEE Int. Electron Devices Meeting Tech. Dig., pp. 1–4, Dec. 2009.
[23] L. Wei et al., “Exploration of device design space to meet circuit speed targeting 22nm and beyond,” in Proc. Int. Conf.
Solid State Devices and Materials, pp. 808–809, Sep. 2009.
[24] K. Cheng et al., “Fully depleted extremely thin SOI technology fabricate by a novel integration scheme featuring implantfree,
zero-silicon-loss, and faceted raised source/drain,” in IEEE Symp. VLSI Technology Tech. Dig., pp. 212–213,
Jun.2009.
[25] T. Skotnicki, “CMOS technologies – trends, scaling and issues ,” in IEEE Int. Electron Devices Meeting Short Course, Dec.
2010.
[26] M. Yamaoka et al., “SRAM circuit with expanded operating margin and reduced stand-by leakage current using thin BOX
FD-SOI transistors,“ IEEE J. Solid-State Circuits, vol. 41, no.11, Nov. 2006.
[27] T. Skotnicki, “Competitive SOC with UTBB SOI,” in Proc. IEEE SOI Conf., Oct. 2011.
[28] K. Fujita et al., “Advanced channel engineering achieving aggressive reduction of V T variation for ultra-low power
applications,” in IEEE Int. Electron Devices Meeting Tech. Dig., pp. 32.3.1–32.3.4, Dec. 2011.
[29] C. Hu, “FinFET 3D transistor and the concept behind it,” in IEEE Electron Device Soc. Webinar, Jul. 2011.
[30] M. Bohr, “22 nm tri-gate transistors for industry-leading low power capabilities,” in Intel Developer Forum, Sep. 2011.
[31] M. Yang et al., “Hybrid-orientation technology (HOT): opportunities and challenges,” IEEE Trans. Electron Devices, vol. 53,
no. 5, pp. 965–978, May 2006.
[32] S. Paul, “FinFET vs. trigate: parasitic capacitance and resistance”, AMD Internal Presentation, Aug. 2011.
[33] C. Auth et al., “A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors,
self-aligned contacts and high density MIM capacitors,” in IEEE Symp. VLSI Technology Tech. Dig., pp. 131–132, Jun.
2012.
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 117

Acknowledgments
Thanks to the authors of the countless
published material used as illustrations
in this presentation
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Slide 118

The Shoulders I Humbly Stand On
Bob Barnes
Agilent
Larry Bair
AMD
John Bravman
Bucknell
Tom Cynkar
Avago
Dick Dowell
Avago
Bruce Doyle
AMD
Emerson Fang
Apple
John Faricelli
AMD
Dennis Fischette
AMD
Phil Fisher
Avago
Mike Gilsdorf
Avago
Jung-Suk Goo
GlobalFoundries
Rick Hernandez
PMC-Sierra
Mark Horowitz
Stanford
Ron Kennedy
Avago
Takamaro Kikkawa
Hiroshima Univ.
Greg Kovacs
Stanford
Steve Kuehne
LSI
Tom Lee
Stanford
Justin Leung
Intel
Ying-Keung Leung
GlobalFoundries
Tom Lii
TI
Joe McPherson
TI
Bich-Yen Nguyen
Soitec
Charles Moore
Avago
Michael Oshima
AMD
Chintamani Palsule
Sionyx
Jim Pfiester
Avago
Jim Plummer
Stanford
Dave Pulfrey
UBC
Gary Ray
Intel
Changsup Ryu
Samsung
Krishna Saraswat
Stanford
Matt Angyal
IBM
Qi-Zhong Hong
TI
Wei-Yung Hsu
Applied Materials
Shawn Searles
AMD
Ray Stephany
AMD
Gerry Talbot
AMD
Tom Tiedje
Univ. Victoria
Paul Townsend
SBA Materials
Jeff Wetzel
SVTC
Martin Wedepohl
UBC
Tin Tin Wee
AMD
Simon Wong
Stanford
Bruce Wooley
Stanford
Andy Wei
GlobalFoundries
© Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers Slide 119