Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
…But Slowing Down<br />
• <strong>MOS</strong> per<strong>for</strong>mance improves with sc<strong>al</strong>ing<br />
• BUT $$$ (as <strong>al</strong>ways) is THE main reason <strong>to</strong> sc<strong>al</strong>e<br />
• Each new C<strong>MOS</strong> node shrinks dimensions by 2<br />
• Same function<strong>al</strong>ity in h<strong>al</strong>f the area<br />
• Cost-per-function<strong>al</strong>ity if area reduction exceeds<br />
increased cost-per-area <strong>for</strong> more complex manufacturing<br />
• Enables more function<strong>al</strong>ity on a single die<br />
• Fewer dies fewer packages lower cost<br />
• Moving <strong>to</strong> planar 20nm C<strong>MOS</strong> is not so obvious<br />
• Wafer cost is g<strong>et</strong>ting prohibitive, e.g., double patterning<br />
• Fully-depl<strong>et</strong>ed option (e.g., tri-gate fins) is compelling <strong>to</strong><br />
enable low-power operation, especi<strong>al</strong>ly with high demand<br />
<strong>for</strong> portable ICs<br />
• 28nm likely <strong>to</strong> be around <strong>for</strong> a while<br />
© <strong>Loke</strong> <strong>et</strong> <strong>al</strong>., <strong>2D</strong> <strong>to</strong> <strong>3D</strong> <strong>MOS</strong> <strong>Technology</strong> <strong>Evolution</strong> <strong>for</strong> <strong>Circuit</strong> <strong>Designers</strong><br />
Slide 3
Change language