Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers

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Lithography Misalignment / Overlay • Mask misalignment tolerance is not keeping pace with gate CD scaling • ASML has near monopoly on lithography tools largely because of good overlay control (global zero layer patterns) • Many layout enclosure & spacing rules not scaling with CD • Examples: • Poly overhang beyond active • Contact spacing to poly • Active enclosure around contact • Metal enclosure around vias • Layout for matching must be robust against overlay errors © Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers Slide 23
Resolution Enhancement Technology Wei, GlobalFoundries [5] Resolution = k 1 NA Rayleigh k 1 Factor • Reducing k 1 is the remaining ticket to better resolution • Attack problem from all fronts: mask, source & wafer • Imposes significant restrictions on layout design rules © Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers Slide 24
Page 1 and 2: 2D to 3D MOS Technology Evolution f
Page 3 and 4: CMOS Scaling Still Alive… Intel 2
Page 5 and 6: Bleeding-Edge IC Development • De
Page 7 and 8: Our Objective • Understand how MO
Page 9 and 10: The Basis of All CMOS Digital ICs i
Page 11 and 12: Flatband Condition (V GS =V FB ) V
Page 13 and 14: Onset of Strong Surface Inversion (
Page 15 and 16: Quantifying Charge to Move s by 2
Page 17 and 18: Short-Channel Effects (SCEs) L V T
Page 19 and 20: Outline • Part 1 - Motivation - M
Page 21 and 22: Let There Be Light Resolution = k 1
Page 23: Immersion Lithography • Remember
Page 27 and 28: Mask - Sub-Resolution Assist Featur
Page 29 and 30: Source - Off-Axis Illumination -2
Page 31 and 32: Double Patterning Pitch Division Li
Page 33 and 34: 130nm MOSFET Fabrication 1 STI oxid
Page 35 and 36: Shallow Trench Isolation - After 35
Page 37 and 38: Topography Buildup is Costly Later
Page 39 and 40: Well Implant Engineering Retrograde
Page 41 and 42: Poly Gate Definition • Gate CD wa
Page 43 and 44: 1 Channel & Source/Drain Engineerin
Page 45 and 46: Feed-Forward Manufacturing Control
Page 47 and 48: Non-CMP Density Effects - RTA Befor
Page 51 and 52: Not So Fundamental After All M O S
Page 53 and 54: Subthreshold Leakage • MOSFET is
Page 55 and 56: Drain-Induced Barrier Lowering (DIB
Page 59 and 60: Making SOI Starting Material • Ch
Page 61 and 62: All About Impedance Division V S V
Page 65 and 66: Mechanical Stresses & Strains Stres
Page 67 and 68: Transferring Strain from Material A
Page 69 and 70: Shallow Trench Isolation (STI) NMOS
Page 71 and 72: Periodic Table Trends lattice spaci
Page 73 and 74: Dual-Stress Liners NMOS & PMOS
Page 75 and 76:
Strain Depends on Channel Location
Page 77 and 78:
Transverse DSL Proximity • Both N
Page 79 and 80:
Well Implant Proximity Effect • V
Page 81 and 82:
The Roads to Higher Performance sou
Page 83 and 84:
Poly Depletion & Charge Centroid Di
Page 85 and 86:
Atomic Layer Deposition • Deposit
Page 87 and 88:
GlobalFoundries 32nm-SOI NMOS PMOS
Page 89 and 90:
Intel 45nm NMOS PMOS Auth et al, In
Page 91 and 92:
Intel 32nm Packan et al, Intel [22]
Page 93 and 94:
What Does Fully-Depleted Really Mea
Page 95 and 96:
The Big Deal with Lower DIBL Higher
Page 97 and 98:
Fully-Depleted Planar on SOI • a.
Page 99 and 100:
Performance Tuning with Backgate Bi
Page 101 and 102:
Random Dopant Fluctuation (RDF) 50
Page 103 and 104:
Why Fully-Depleted Eliminates RDF
Page 105 and 106:
What is Fully-Depleted Tri-Gate? 32
Page 107 and 108:
Crystallography Basics • Planes i
Page 109 and 110:
Mobility Dependence on Surface Orie
Page 111 and 112:
Process Flow Summary I • Example
Page 113 and 114:
Some Tri-Gate Considerations • Fi
Page 115 and 116:
IDSAT (A/m) 1.E-02 1.E-03 1.E-04 1.
Page 117 and 118:
References I [1] M. Keating, “Sci
Page 119 and 120:
Acknowledgments Thanks to the autho
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Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers

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