Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
Loke et al., 2D to 3D MOS Technology Evolution for Circuit Designers
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Rapid Therm<strong>al</strong> Processing (RTP)<br />
Temperature<br />
RTP<br />
Temperature<br />
Furnace<br />
substanti<strong>al</strong><br />
ramp times<br />
Time<br />
Time<br />
• Initi<strong>al</strong>ly developed <strong>for</strong> short anne<strong>al</strong>s<br />
• Impossible <strong>to</strong> control short therm<strong>al</strong> cycles in furnaces<br />
• Want minimum diffusion <strong>for</strong> sh<strong>al</strong>low & abrupt junctions<br />
• Process steps:<br />
• Anne<strong>al</strong>ing repair implant damage, activate dopants<br />
• Oxidation gate oxide<br />
• Nitridation spacers, ARL<br />
• Poly deposition gate<br />
• RTP in single-wafer multi-chamber cluster <strong>to</strong>ols<br />
© <strong>Loke</strong> <strong>et</strong> <strong>al</strong>., <strong>2D</strong> <strong>to</strong> <strong>3D</strong> <strong>MOS</strong> <strong>Technology</strong> <strong>Evolution</strong> <strong>for</strong> <strong>Circuit</strong> <strong>Designers</strong><br />
Slide 45