DS18S20 High-Precision 1-Wire Digital Thermometer

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DS18S20CRC GENERATIONCRC bytes are provided as part of the DS18S20’s 64-bit ROM code and in the 9 th byte of the scratchpadmemory. The ROM code CRC is calculated from the first 56 bits of the ROM code and is contained in themost significant byte of the ROM. The scratchpad CRC is calculated from the data stored in thescratchpad, and therefore it changes when the data in the scratchpad changes. The CRCs provide the busmaster with a method of data validation when data is read from the DS18S20. To verify that data hasbeen read correctly, the bus master must re-calculate the CRC from the received data and then comparethis value to either the ROM code CRC (for ROM reads) or to the scratchpad CRC (for scratchpad reads).If the calculated CRC matches the read CRC, the data has been received error free. The comparison ofCRC values and the decision to continue with an operation are determined entirely by the bus master.There is no circuitry inside the DS18S20 that prevents a command sequence from proceeding if theDS18S20 CRC (ROM or scratchpad) does not match the value generated by the bus master.The equivalent polynomial function of the CRC (ROM or scratchpad) is:CRC = X 8 + X 5 + X 4 + 1The bus master can re-calculate the CRC and compare it to the CRC values from the DS18S20 using thepolynomial generator shown in Figure 8. This circuit consists of a shift register and XOR gates, and theshift register bits are initialized to 0. Starting with the least significant bit of the ROM code or the leastsignificant bit of byte 0 in the scratchpad, one bit at a time should shifted into the shift register. Aftershifting in the 56 th bit from the ROM or the most significant bit of byte 7 from the scratchpad, thepolynomial generator will contain the re-calculated CRC. Next, the 8-bit ROM code or scratchpad CRCfrom the DS18S20 must be shifted into the circuit. At this point, if the re-calculated CRC was correct, theshift register will contain all 0s. Additional information about the Dallas 1-Wire cyclic redundancy checkis available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with DallasSemiconductor Touch Memory Products.CRC GENERATOR Figure 8INPUTXOR XOR XOR(MSB)(LSB)8 of 22
DS18S201-WIRE BUS SYSTEMThe 1-Wire bus system uses a single bus master to control one or more slave devices. The DS18S20 isalways a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”system; the system is “multidrop” if there are multiple slaves on the bus.All data and commands are transmitted least significant bit first over the 1-Wire bus.The following discussion of the 1-Wire bus system is broken down into three topics: hardwareconfiguration, transaction sequence, and 1-Wire signaling (signal types and timing).HARDWARE CONFIGURATIONThe 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to thedata line via an open drain or 3-state port. This allows each device to “release” the data line when thedevice is not transmitting data so the bus is available for use by another device. The 1-Wire port of theDS18S20 (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 9.The 1-Wire bus requires an external pullup resistor of approximately 5k; thus, the idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idlestate if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wirebus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480s,all components on the bus will be reset.HARDWARE CONFIGURATION Figure 9V PUDS18S20 1-WIRE PORTR X4.7k1-wire BusDQPinR X5µATyp.T XT XR X = RECEIVET X = TRANSMIT100MOSFETTRANSACTION SEQUENCEThe transaction sequence for accessing the DS18S20 is as follows:Step 1. InitializationStep 2. ROM Command (followed by any required data exchange)Step 3. DS18S20 Function Command (followed by any required data exchange)It is very important to follow this sequence every time the DS18S20 is accessed, as the DS18S20 will notrespond if any steps in the sequence are missing or out of order. Exceptions to this rule are the SearchROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM commands, themaster must return to Step 1 in the sequence.9 of 22
Page 1 and 2: www.maxim-ic.comFEATURESUnique 1-Wi
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Page 10 and 11: DS18S20INITIALIZATIONAll transactio
Page 12 and 13: DS18S20READ POWER SUPPLY [B4h]The m
Page 14 and 15: DS18S20READ-TIME SLOTSThe DS18S20 c
Page 16 and 17: ROM COMMANDS FLOW CHART Figure 14DS
Page 18 and 19: DS18S20 OPERATION EXAMPLE 1In this
Page 20 and 21: ABSOLUTE MAXIMUM RATINGS*Voltage on
Page 22: TIMING DIAGRAMS Figure 17DS18S2022

DS18S20 High-Precision 1-Wire Digital Thermometer

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