VITA 46.9: Ensuring mezzanine I/O pinout interoperability for VPX ...

HardwareVPX ... Almost REDIVITA 46.9: Ensuring mezzanine I/O pinoutinteroperability for VPX and VPX-REDIBy Jing KwokThe emerging VITA 46 (VPX) and VITA 48 (VPX-REDI) bus architecture standards are bringing newlife – and faster speeds – to high-performance processing configurations previously untouchable tolegacy VME systems. They also provide more I/O pins, giving more freedom in I/O definition to systemintegrators; however, this increased freedom can result in mezzanine/baseboard incompatibility issuesfor end users. Now VITA 46.9, a subsidiary specification of VPX, steps into the front line by solvingXMC and PMC I/O mapping issues and increasing interoperability among vendors.The VITA 46 (VPX) family of standardsdefines an embedded computer modulethat builds on the utility of the VMEbusEurocard form factor by providing a seriesof high-speed, fabric capable backplaneMultiGig RT-2 connectors, in lieu of theconventional DIN pin and socket connectors.Proper use of these connectorsfor a variety of backplane signaling standardsis defined further in the VPX “dot”subsidiary specifications. These “dot”standards dictate the type of connectorpopulated at each allowable location ona VPX card and the interface signal mappingsof the different serial fabric options.VPX cards, like earlier VME boards,will typically provide mezzanine cardinstallation sites for the addition of application-specificfunctions. PCI MezzanineCard (PMC) and/or Switched MezzanineCard (XMC) mezzanines may be optionallyinstalled on the VPX card, dependingon the functionality designed into thebase plug-in module or “carrier” by thedesigner. VITA provides several standardsfor bus signaling on PMC and XMC cardsto ensure interoperability among boardvendors. These standards also define the“user I/O” connector contacts that areavailable to the mezzanine card designer.VITA 46.9 is one such standard, definingthe differential pairs to be used inmapping mezzanine I/O to the VPX backplaneconnectors.VITA 46.9 to the forefrontIn the past, the failure to define the consistentusage of I/O pins has createdproblems resulting in mezzanine cardsthat were incompatible with certainbaseboards. In the VME specification,I/O signals for the VME P0 and P2 wereonly defined for single-ended configuration.Single-ended signaling is typicallyused on PMC mezzanine cards to addresscommon I/O interfaces that do not requiretightly controlled signal environments.Consequently, differential I/O signalswere left undefined, which encourageddifferent vendors to use different pinoutschemes. This resulted in a variety ofproblems for end users. For example, insome cases mezzanine cards would onlywork with certain specific baseboards.Also, in some cases, mezzanine modulesrequired different layouts depending onwhether the module was to be installed inthe baseboard’s PMC site 1 or in site 2.One layout would be needed to match P0and a different one to match P2.The VPX working group, armed withknowledge of past problems resultingfrom the lack of definition for differentialI/O signals for VME P0 and P2, decidedto eliminate the confusion experienced byearlier VME users and solve the problemby defining differential I/O pinout in theVPX specification. The alternative mighthave resulted in the emergence of numerouscompeting I/O options that couldhamper interoperability.ForSinglePrintOnlyThe VPX working group, to addressthis problem, has created the VITA 46.9“dot-spec,” which defines the standarddifferential pairs to be used for mappingmezzanine I/O to the VPX backplaneconnectors. The working groupalso ensured that the resulting differentialAdvantages of VPX over legacy VMEAdvantageWhile VME has long been the bus architecture of choicefor military and aerospace applications, recent advancesin technologies, particularly in interconnects, have demonstratedthe need for an advance in system development. Thenew VPX (VITA 46) and VPX-REDI (VITA 48) bus architecturespecifications update the VMEbus legacy to provide supportfor high-speed switched serial fabrics, such as Serial RapidIO(SRIO) and PCI Express, and support distributed processingat speeds and in network configurations unreachable byVME64x.One of the key advantages of VPX over legacy VME is thegreater number of I/O pins that it makes available to endusers. This gives integrators the freedom to define I/O asthey need to add market differentiation and meet the requirementsof unique applications. The increased backplane I/Oprovided by VPX also makes it possible for some of theseextra I/O pins to be allocated to additional XMC and PMCcard I/O. This is in contrast to VME and some other newerstandards that provide only limited backplane I/O.In fact, VPX is the only bus architecture format that definesa standard approach for XMC I/O to the backplane. VPXoffers another benefit to XMC module users resulting fromits use of Tyco’s MultiGig RT-2 connectors, greatly improvingsignal integrity for rear-panel mezzanine I/O compared toVME or CompactPCI connectors. Also, the XMC Pn6 connectorprovides superior performance to the PMC Pn4 mezzanineconnector because standard mapping provides interveninggrounds and significant physical separation between pairs.VME and Critical Systems ©2007 OpenSystems Publishing. Not for Distribution.

VPX ... Almost REDIHardwarepinout mapping would be symmetrical,for example, work on either a 6U VPXP3/4 set or on a P5/6 set. In addition, theworking group also defined differentialpinout usage for 3U VPX cards and theirP1/2 set. The result is that VITA 46.9solves XMC/PMC I/O mapping on VPXand ensures and greatly simplifies theinteroperability of basecards and mezzanineI/O cards from different vendors.“VITA 46.9 ensuresinteroperability whileproviding flexibility byoffering a number ofstandard combinations.”Innerworkings of VITA 46.9The objective of the VITA 46.9 standard isto supplement the VITA 46.0 base standardto fully define the user I/O signal mappingbetween the pins of PMC and/or XMC cardsites provided on a VPX compliant carrierfor both 3U and 6U modules. In addition,it defines the fabric mapping for a 3Umodule and placement for two channelsof GbE 1000BASE-T. VITA 46.9 ensuresinteroperability while providing flexibilityby offering a number of standard combinations.The following combinations weredetermined the most likely to be actuallyimplemented in practice: PMC Jn4 assigned to 3U V46-P2differential and single-endedconnector XMC Jn6 assigned to 3U V46-P2differential connector PMC Jn4 assigned to 6U V46-P3,5 differential connector XMC Jn6 assigned to 6U V46-P3/4,5/6 differential connectorTo accommodate this, various mappingpatterns have been defined: P64s – Maps all 64 contacts ofPMC-Jn4 to VPX differential wafers. X12d – Maps 12 selected differentialpairs of XMC-Jn6 to VPX differentialwafers. X20d24s – Maps all 20 differentialpairs of XMC-Jn6 and 24 single-endedpairs to VPX differential wafers. Thispattern fits within one VPX connector. X20d38s – Maps the entire XMCconnector to VPX differential wafers.This consists of all 20 differential pairsof XMC-Jn6 and all 38 single-endedsignals.For 6U cards, several overall configurationscan be accommodated by selectingfrom the previously defined mappingpatterns (see Figure 1): VPX P3/P5 mapped to PMCJn4 using the P64s and P4/P6 mappedto the XMC Jn6 using the X12dpattern VPX P3/4, P5/6 mapped to XMCJn6 using the X20d38s pattern6U VPX ModuleXMC/PMC ModuleJn5 Jn1 Jn2Jn6Jn3X20d38sJn4X12dJn5 Jn1 Jn2X20d38sJn6 Jn3 Jn4X12dP64sP64sFigure 1keyP0P1P2keyP3P4P5P6keyFor 3U cards, the following configurationsare supported, as shown in Figure 2: VPX P2 mapped to PMC Jn4 usingthe P64s and P1 mapped to the XMCJn6 using the X12d pattern VPX P2 mapped to X20d24s3U VPX ModuleXMC/PMC ModuleJ15 J11 J12J16J13X12dJ14X20d24sP64sFigure 2keyP0P1P2keyFigures 1 and 2 both show all configurationsmapped on a carrier card. However,in practice, only one configuration willbe mapped at a time. For example, a VPXcarrier card that supports only a PMCmezzanine will only use the P64s mappingas it will only have Jn4 installed.For a VPX carrier card that supportsonly XMC Jn6, then the X20d38s mappingwill be used in the 6U case and theX20d24s mapping will be used in the3U case. For a VPX carrier card that supportsboth XMC Jn6 and Jn4, then P64sand X12d would be mapped.ForSinglePrintOnlyVME and Critical Systems ©2007 OpenSystems Publishing. Not for Distribution.VITA 46.9 mapping patternsexploredThe mapping pattern P64s is relativelystraightforward. The P64s maps the 64 Jn4I/O pins on a PMC mezzanine to the VPXRT2 connector. The 64 pins are arrangedas two rows of 32 pins each. One columnis labeled odd and the other even. Inselecting the differential pairs, the workinggroup selected pins next to each otheras differential pairs. That is, pins 1-3are considered a differential pair and pins2-4 are considered a differential pair.This approach was taken to ease matchedlength routing on the PMC module and thecarrier card. These pins are then mappedto the VPX RT2 connector.

HardwareVPX ... Almost REDIThe mapping pattern X12d was a morecomplex challenge. The X12d maps12 differential pairs of the XMC Jn6connector to the RT2 connector. Theworking group chose 12 differential pairsas a good tradeoff between the amount ofXMC I/O mapped to the MultiGig RT-2connector versus the number of I/O linesleft over for use by the host card itself. Theworking group spent much time debatingthis mapping. The main issue was which12 pairs should be mapped? The XMCJn6 connector is an open field connectorarranged as 6 columns (A to G) and19 rows of pins, for a total of 114 pins.Much signal integrity work was done inthe XMC working group. It showed that20 differential pairs can be obtained byplacing them on the odd rows on columnsAB, DE with grounds on the even rows ofthose same columns. The XMC workinggroup further defined that rows 1,3,5,7were to be transmit lines and 11,13,15,17were to be receive lines. This approachprovides an XMC mezzanine card with theability to support up to eight lanes of serialtx/rx traffic. The working group decidedto stay with this pattern and allowed8 differential pairs for a fabric port onrows 1,3 and 11,13 and assigned theremaining 12 pairs for the X12d backplaneI/O pattern.The patterns X20d24s and X20d38s hencefell out from this effort once the X12dpattern was defined. The X20d24s patternmaps 20 pairs and 24 single-ended pinsfrom columns C and F to a single RT-2connector. The X20d38s pattern maps20 pairs and 38 single-ended pins fromcolumns C and F over two RT-2 connectors.Note that the X20d38s pattern maps78 pins to the RT-2 connector. This is thefull complement of pins on the 114 pinXMC connector as the rest are dedicatedto grounds.VITA 46.9 speeds futuredevelopmentBy ensuring that mezzanine I/O differentialpair mapping was defined in theVPX specification – and particularlyVITA 46.9 – the VPX working group hasensured that mezzanine, basecard, andbackplane/chassis designers will have theproper information to enable them to designinteroperable PMC and XMC I/O mezzaninecards. This will help ease the adoptionof new high-speed VPX and VPX-REDIapplications, paving a smoother pathto the future for the end users of today’schallenging applications. CSJing Kwok isprincipal engineerin the TechnologyGroup at Curtiss-Wright ControlsEmbeddedComputing. Hehas been involvedwith VMEbus standards work for thepast 15 years. He is editor of one ofthe VITA 46 “dot” specifications nowin working group ballot and was oneof the chapter editors for the VME64specification. Jing is a graduate ofthe British Columbia Institute ofTechnology.For more information, contact Jing at:Curtiss-Wright ControlsEmbedded Computing333 Palladium Drive, m/s 385Kanata, ON, Canada K2V-1A6613-599-9199, Ext. 5825jing.kwok@curtisswright.comwww.cwcembedded.comForSinglePrintOnlyVME and Critical Systems ©2007 OpenSystems Publishing. Not for Distribution.