Embedded Computing Design - OpenSystems Media

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W W W. E M B E D D E D - C O M P U T I N G. C O M 

Vo l u m e 2 • N u m b e r 2 

S U M M E R 2 0 0 4 

CONTENTS 

COLUMNS 

7 Editor’s Foreword 

Switch fabrics move forward ... 

By Mark David Barrera 

8 Industry Report 

By Bonnie Crutcher 

12 Book Review 

ARM System Developer’s Guide 

By Andrew N. Sloss, Dominic Symes, and Chris Wright 

14 EEMBC 

Standardizing a powerful measurement 

By Markus Levy 

16 ZigBee Alliance 

Networking with Zigbee 

By Jon Adams 

19 Linux News 

By Bonnie Crutcher 

61 New Products 

By Eli Shapiro 

EVENTS 

SUPERCOMM 

June 20-24, 2004 • Chicago, Illinois 

www.supercomm2004.com 

Real-Time & Embedded Computing Conference (RTECC) 

June 30, 2004 • Greenbelt 

August 17, 2004 • Dayton 

www.rtecc.com 

Product photo credit: 

SBS Technologies IB4X-PMC-2 

InfiniBand 4x Dual-Port PMC Host 

Channel Adapter (HCA) 

Embedded 

Computing 

Design 

published by: 

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e m b e d d e d - c o m p u t i n g . c o m 

4 / Summer 2004 Embedded Computing Design 

OpenSystems 

Publishing TM 

FEATURES 

SPECIAL: Fabric Diversity 

20 InfiniBand and PCI-Express subsystems: 

A winning combination for embedded applications 

By Lori Dunbar and Steve Cook, SBS Technologies 

25 The current landscape of switch fabrics and RapidIO 

By Luc Torres, Thales Computers 

TECHNOLOGY: Design Tips 

30 Tips for designing DSPs and FPGAs 

By Eric Cigan, AccelChip 

36 Tips for designing complex FPGAs 

By Salil Raje, Hier Design 

42 Leveraging FPGA coprocessors to optimize automotive 

infotainment and telematics systems 

By Paul Ekas, Altera 

APPLICATION: Biometrics 

49 New fingerprint subsystem brings biometrics to the 

mass market 

By Kevin C. Kreitzer, Analog Devices, Inc. 

and Alan Kasten, AuthenTec, Inc. 

52 Government Security 

Surveillance and control systems for the modern military 

By Steve Wigent, Performance Technologies 

PRODUCT GUIDE: Embedded Communications 

55 Blades – Servers – VoIP 

By Chad Lumsden 

E-LETTERS ONLINE 

July E-letter: Making the Switch to RapidIO 

by Paul N. Leroux, QNX Software Systems Ltd. 

www.embedded-computing.com/eletter 

FREE SUBSCRIPTIONS 

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© 2004 Embedded Computing Design

And you thought SHE was 

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©2004 Micro/sys. All brand and/or product names listed are registered trademarks of their respective owners.

W W W. E M B E D D E D - C O M P U T I N G. C O M 

An OpenSystems Publication 

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ISSN: Print 1542-6408, Online 1542-6459 

Embedded Computing Design is published quarterly by OpenSystems Publishing LLC., 

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18 AAEON Electronics – PCM-8500 Compact 

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3701 ABIA – Cube Systems & Low Power 

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63 ACCES I/O Products – PC/104 Analog, 

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9 Acrosser Technology – 486 PC/104 

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66 Advantech – Ruggedized PC Solutions 

35 Analog Devices – Blackfin Processor 

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64 ARM – ARM Developers’ Conference 

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5 Micro/Sys – 12, 14, 16, and 24-bit A/D and D/D 

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Solutions 

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60 TME – Embedded Computer Solutions 



46 Tri-M Systems – Hardware Solutions for 

Embedded Systems 

54 Ultimate Solutions – Development Tools 

68 VersaLogic – OEM Product 

4701 Windows For Devices – Embedded 

Community 

3 WinSystems – Systems Components 

PUBLISHERS 

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© 2004 Embedded Computing Design

S 

Switch fabrics 

Welcome to the special switch fabrics edition of Embedded Computing Design. This issue illustrates the ongoing intensive 

development of switch fabrics. 

The InfiniBand and PCI-Express feature, by Lori Dunbar and Steve Cook of SBS Technologies, is an in-depth discussion of 

connectivity issues with an emphasis on InfiniBand. 

The switch fabric and RapidIO landscape feature, by Luc Torres of Thales Computers, is also an in-depth connectivity discussion, 

but with an emphasis on RapidIO. 

DThese articles point out the ongoing discussions in the development of intersystem and intrasystem connections. 

B 

R 

Switch fabrics move forward... 

Design tips 

This issue also includes useful design information for semiconductor and system engineers. 

The DSP and FPGA design tips article, by Eric Cigan of AccelChip, is an overview of the benefits of using FPGAs in DSP design, 

and concludes with a list of recommended design rules. 

The complex FPGA design tips article, by Salil Raje of Hier Design, discusses advanced design topics including the benefits of 

early design analysis. 

The FPGA coprocessor article, by Paul Ekas of Altera, provides valuable information on automotive infotainment and telematic 

system optimization, and cost reduction. 

Biometrics 

The fingerprint recognition system article, by Kevin Kreitzer of Analog Devices, and Alan Kasten of AuthenTec, describes the 

development and operation of an embedded biometrics application. 

Radar management 

The radar information management article, by Steve Wigent of Performance Technologies, describes 

an example of the use of embedded systems in critical military applications. 

I hope you will find my debut issue as Sr. Technical Editor of Embedded Computing Design to be a 

useful addition to your engineering publications library. I encourage your comments and suggestions 

concerning this, and future issues. 


Sr. Technical Editor 

Embedded Computing Design Magazine 

mbarrera@opensystems-publishing.com 


RSC #7 @ www.embedded-computing.com/rsc 

Embedded Computing Design Summer 2004 / 7

icrutcher@opensystems-publishing.com 

■ INDUSTRY NEWS 

Rugged mobile tablet PC use expected to rise 

IMS Research’s most recent survey found that users of rugged 

mobile computers expect their consumption of tablet PCs to 

significantly increase during the next three years. According to 

IMS, this finding confirms the trend that tablet PCs will become 

more widely accepted in the rugged mobile computer market. 

An IMS survey of companies that purchased rugged mobile 

computers found that some 17.6 percent expected to buy tablet 

PCs within three years, a significant increase over current market 

penetration. 

As IMS Research analyst and report author Tim Dawson points 

out, “Tablet PCs are a versatile alternative to rugged handheld and 

vehicle-fixed PC solutions. The nature of these products means that 

they can be used in both handheld and vehicle-fixed applications.” 

For more information: www.imsresearch.com 

AMI Semiconductor reports record revenues 

in 2003 

AMI Semiconductor (AMIS), a designer and manufacturer of 

integrated mixed-signal and structured digital products for the 

automotive, medical, and industrial sectors, reported record 

revenues of $454 million in 2003, up from $345 million in 2002, 

helped by a strong fourth quarter. The company experienced 

revenue growth in each of its target end markets with communications 

up 56 percent and automotive, medical, and industrial 

growing 44, 27, and 21 percent respectively. AMIS also reported 

a 34 percent growth in three-year revenue from design wins 

over 2002. 

“2003 proved to be a banner year for AMI Semiconductor in all 

facets of the company, including our successful IPO,” said Christine 

King, President and CEO of AMIS. 

For more information: www.amis.com 

Augmentix closes $3 million in funding 

Augmentix, a provider of enhanced commercial servers for missioncritical 

applications, recently announced that it has closed a round 

of funding from Austin Ventures. An initial capital investment of 

$3 million will allow Augmentix to bring to market its first products, 

which have been in development for more than a year. 

“Our preliminary meetings with enthusiastic prospects have 

confirmed the validity of our approach to building cost-effective 

mission-critical servers,” said Augmentix President and CEO 

Chris Melson. “With the support of Austin Ventures, we can now 

focus on delivering systems that will enable telecommunications, 

government agencies, industrial automation, and medical imaging 

companies to keep their most demanding and important applications 

running without interruption.” 

For more information: www.augmentix.com 

Data I/0 announces programming support for 

Texas Instruments’ digital signal controller 

Data I/O, a provider of manual and automated programming 

systems, announced high volume programming support for Texas 

Instruments’ TMS320F2810 digital signal controller on its Sprint 

family of device programmers. 

“We are pleased to announce this support for the F2810,” said 

Bruce Rodgers, Data I/O Director of Semiconductor Relations 

and Marketing. “The automotive market is an important customer 

group for our company, and we expect many users will embrace 

this family of TI devices for their range of applications.” 

For more information: www.data-io.com 

MIPS Technologies verifies newest 24K 

processor family with Mentor Graphics’ 

Vstation TBX accelerator 

MIPS Technologies, Inc. and Mentor Graphics Corp. recently 

announced that the performance of the MIPS32 24K family of 

processors, which operates from 400 MHz to 550 MHz worst case 

in a 0.13-micron process, was verified using the Mentor Graphics 

Vstation TBX verification accelerator. 

“With Mentor Graphics’ verification accelerator, we were able to 

boot both Linux and the Windows CE .NET operating systems. We 

ran thousands of tests and 1.8 billion random verification cycles 

per day while still meeting our internal delivery schedule. With 

this level of verification quality, we are delivering a 24K core that 

is proven, solid, and reliable,” said Don Ramsey, Director of CAD 

operations at MIPS Technologies. 

For more information: www.mentor.com 

WIN Enterprises unveils new website 

WIN Enterprises, Inc., a designer and manufacturer of embedded 

systems for OEMs, has unveiled www.win-ent.com, to highlight 

its design and manufacturing expertise. 

According to the company, every service required for x86-based 

electronic product development is outlined on the new site. The 

site features in-depth product information, an expanded services 

section, several case studies, and a Request for Quotation 

(RFQ) form. 

For more information: www.win-ent.com 

Sun adds SSE support to Solaris 

Sun has released its quarterly update for the Solaris version of 

the UNIX operating system, adding support for several Intel 

processor features and for Sun’s new UltraSparc IV processor, 

the company announced recently. The new version runs faster on 

x86 chips including Intel’s Xeon and Advanced Micro Devices’ 

Opteron through support for Streaming SIMD Extensions (SSE) 

technology, which speeds operations by letting a chip run a single 

instruction on multiple data elements. 

Sun said the support is included both in Solaris itself and in its Java 

software and announced that server maker Rackable Systems will 

offer the x86 version of Solaris on its products. 

For more information: www.sun.com 

8 / Summer 2004 Embedded Computing Design


Systran Corporation’s FibreXtreme Serial 

FPDP links increase to 50 kilometers 

Systran Corporation, a wholly owned subsidiary of Curtiss-Wright 

Controls, Inc. and the originator of the Serial FPDP protocol and 

developer of the FibreXtreme Serial FPDP data link, today further 

extended the reach of their SL100/SL240 Serial FPDP connections 

to up to 50 kilometers. The extension increases the original 

connection distance by 500 percent. According to the company, 

the increase enables designers of radar systems, targeting systems, 

and other sensor-to-processor systems to significantly increase the 

physical separation of the sensor and the DSP system for safety and 

increased system reliability. 

For more information: www.systran.com 

■ CONFERENCES & AWARDS 

Wireless Sensing Solutions advisory board 

members announced 

IDG World Expo, a producer of tradeshows for technology 

markets, and FuelDog Events, a developer of tradeshow concepts 

and solutions, recently announced members of the advisory board 

for Wireless Sensing Solutions, a new event for the burgeoning 

industry of wireless sensor networking. The advisory board will be 

responsible for developing a comprehensive program focused on 

the standards, interoperability, technologies, and product strategy 

driving the wireless sensor networking industry. 

Wireless Sensing Solutions will debut September 21-22, 2004 at 

the Donald E. Stephens Convention Center in Rosemont, IL. 

“The Wireless Sensing Solutions conference answers the very real 

need for education about the great advances achieved in wireless 

sensing and mesh networking technologies of late,” said advisory 

board member Ian Barkin, Managing Director of The FocalPoint 

Group. “We are excited to be an integral part of it.” 

For more information: www.wssconference.com 

■ MERGERS & ACQUISITIONS 

Mercury Computer acquires TGS Group 

Mercury Computer Systems recently announced the acquisition 

of TGS Group, a software developer of 3D image applications 

for medical imaging, biotech, oil and gas exploration, and other 

industries. 

The acquisition is for approximately $18.5 million, consisting of 

$6.0 million in Mercury common stock and the remainder in cash, 

subject to closing adjustments. The transaction is expected to close 

by June 30, 2004, the end of Mercury’s fiscal year. 

TGS will enable Mercury to develop integrated technology products 

for high-growth 3D imaging markets that include TGS software 

and Mercury’s high-performance signal and image processing 

multi-computers. 

For more information: www.mc.com 

Elma acquires Optima EPS 

Elma Electronic, Inc., a global manufacturer of electronic 

packaging products and rotary components, recently announced 

it has acquired Optima Electronic Packaging Systems, a cabinet 

enclosure design and manufacturing division of the Gichner 

Systems Group, Inc. The name will be changed to Optima EPS 

Corp. Components. 

“The acquisition of Optima provides us with a reputable, 

established, high quality cabinet enclosure line with expertise 

in customization services,” said Fred Ruegg, President of Elma 

Electronic, Inc. “This product line is an excellent complement to 

Elma’s design and manufacturing expertise in electronic hardware 

components, subrack enclosures, and system platforms.” 

For more information: www.elma.com 

■ PEOPLE 

DRS Technologies names Joseph E. Hart as 

vice president of marketing, aviation, and 

unmanned programs 

DRS Technologies, Inc. announced recently that Joseph E. Hart 

has been named Vice President of marketing, aviation, and 

unmanned programs, at the company’s Washington Operations in 

Arlington, VA. 

In this new position, Hart will oversee the Washington area 

marketing of all U.S. Navy, Marine Corps, and Air Force aviation 

programs, as well as all product lines associated with unmanned 

vehicle technology, including air, land, and maritime surface and 

subsurface. He joined DRS in 2002. 

“We are pleased to welcome Joe Hart to our Washington office. 

His extensive aviation experience adds tremendous depth to our 

team,” said Mike Bowman, the Senior Vice President of DRS’s 

Washington operations. “A key contributor to the development of 

the company’s unmanned technologies business, he successfully 

managed the launch of our Sentry Unmanned Aerial Vehicle (UAV) 

product line and was instrumental in fully developing and recently 

delivering the new Neptune UAV to our US Navy customer.” 

For more information: www.drs.com 

Aonix selects Ben Goodwin as COO and 

VP of sales North America 

Aonix has appointed Ben Goodwin as Chief Operations Officer 

and Vice President of sales for North America and the Pacific 

Rim. Goodwin is directly tasked with strengthening Aonix’s 

presence in the United States. 

“We are very pleased to welcome Ben back into the Aonix 

leadership team,” said Nicolas Hadjidakis, CEO and President of 

Aonix. “North America is an important market for Aonix. With 

Ben’s strong relationships and extensive experience in the missionand 

safety-critical space, we look forward to extending our US 

position not only in the military and aerospace industries, but also 

in transportation, avionics, telecom, and industrial control, where 

similarly complex, critical applications exist.” 

For more information: www.aonix.com 

■ 

■ 

■ 



ARM System Developer’s 

Guide 

By Andrew N. Sloss, Dominic Symes, and Chris Wright 

Reviewed by Chad Lumsden, Technical Editor 

Table of Contents: 

■ Chapter 1: ARM Embedded Systems 

■ Chapter 2: ARM Processor Fundamentals 

■ Chapter 3: Introduction to the ARM Instruction Set 

■ Chapter 4: Introduction to the Thumb Instruction Set 

■ Chapter 5: Efficient C Programming 

■ Chapter 6: Writing and Optimizing ARM Assembly Code 

■ Chapter 7: Optimized Primitives 

■ Chapter 8: Digital Signal Processing 

■ Chapter 9: Exception and Interrupt Handling 

■ Chapter 10: Firmware 

■ Chapter 11: Embedded Operating Systems 

■ Chapter 12: Caches 

■ Chapter 13: Memory Protection Units 

■ Chapter 14: Memory Management Units 

■ Chapter 15: The Future of the Architecture 

For embedded system developers, some of the main requirements 

for a successful project are a short project life, 

timely time-to-market turnaround, and quick and effective 

development of microprocessor-based products. For these reasons, 

the ARM architecture has become one of the most widely used 

32-bit architectures in the world. They are embedded in a vast 

number of products, and this has led to the organization of a 

worldwide support community. What has lacked in this development 

community is the need to support ARM-based embedded designs. 

The ARM System Developer’s Guide fills this need by describing 

the operation of the ARM core from a product developer’s 

perspective. The text assumes that the reader is experienced with 

embedded systems development, but is inexperienced with ARM 

architecture. Software design is emphasized in the text, and each 

chapter includes an ARM software design example that can be 

adapted for integration into a commercial product. 

The first chapter describes the philosophy behind ARM processor 

design and how it differs from traditional design methods. The 

chapter then describes the characteristics of an ARM-based 

embedded system. Chapter two emphasizes the core of an ARMbased 

system and provides an overview of popular ARM cores. 

Chapters three and four examine the ARM and Thumb instruction 

sets and point out the differences between the two assembly 

code variations. The chapters include the first examples of the 

comprehensive flow-charts, tables, drawings, and design examples 

that are included throughout the entire book. 

Chapter five provides guidelines on how to develop effective C 

code for the ARM architecture, while chapter six provides 

guidelines on the development of effective assembly code. For 

chapter seven, one of the most in-depth chapters in the book, 

the discussion turns to the optimization of primitives for specific 

ARM processors. Chapter eight discusses the proliferation of the 

ARM processor in the DSP realm which has been driven by the 

ever growing requirements of today’s hi-end audio and video 

embedded systems. Chapter nine describes how to effectively 

process addressing exceptions and interrupts to improve system 

performance. 

In chapter 10, the authors review several different types of user 

firmware available for the ARM processor, while chapter 11 

focuses on the broader subject of embedded operating systems. 

Chapters 12-14 discuss the many different solutions for memory 

management problems. To conclude, chapter 15 forecasts what the 

future may hold for ARM processor technology, and is followed by 

several appendices providing detailed reference on the instruction 

sets, cycle timing, and an array of ARM products. 

This nearly 700-page guide is ideal as a definitive reference source 

for any serious ARM-based embedded system developer. 

For information on how to obtain a copy of the ARM System 

Developer’s Guide (ISBN 1-55860-874-5), contact: 

Morgan Kaufmann Publishers 

An Imprint of Elsevier Science 

500 Sansome St., Suite 400 

San Francisco, CA 94111 



By Markus Levy 

Standardizing a 

powerful measurement 

Whether you are designing a processor 

into a mobile phone or a high-end 

network router, power consumption 

is an important issue. Actually, in the 

mobile phone, energy is more important 

than power, as battery life is one of the main 

selling points. In networking equipment, 

or any other type of wall-powered apparatus, 

power must be carefully considered 

for the design of the power supply and to 

deal with cooling methods. 

develop standardized power measurement 

techniques as an additional metric 

that coincides with the consortium’s 

standardized performance measurements. 

Besides providing design engineers with 

more information, an energy metric will 

give processor vendors another way to 

highlight their products. Better yet, a 

performance/energy number may allow a 

“less than stellar” performance processor 

to win at the benchmark competition. 

news 

Linux 

NEWS 

Processor vendors specify typical or 

maximum power consumption for their 

devices at a given frequency and operating 

temperature. However, in reality, many 

system designers are looking for data 

on the behavior of processors running in 

situ. They want to know how much power 

and energy the processor consumes 

running the real application and not just 

arbitrarily chosen test vectors. In addition, 

for our IP vendor members. Secondly, 

a processor’s bcrutcher@opensystems-publishing.com 

consumed energy will be 

much different in an isolated setup compared 

to a processor that has capacitive 

loading on its memory interfaces. 

Providing this information for designers 

is the goal of a new EEMBC charter to 

Deriving a one-size-fits-all 

scheme 

At this point, EEMBC’s energyconsumption 

benchmarks are still taking 

shape. However, the main technical 

issues have been clarified. For one thing, 

it’s obvious that distinct methods will be 

needed for applying the metric to silicon 

devices as well as device simulations 

we know that an important part of the 

benchmarks will be in determining which 

portions of the system to include in the 

measurement. If the goal is to measure 

only the processor’s energy, it will be 

necessary to isolate it physically from the 

rest of the system – which poses a daunting 

challenge. 

Table 1 

to demonstrate a longer battery life than to 

blaze through an application at full clock 

speed and voltage. This necessity will lead 

to new generations of benchmarks that are 

targeted to completing the necessary task 

in an acceptable amount of time. 

Reference: 

1. Table 1 courtesy of Professor David Kaeli and Steven 

VanderSanden of Northeastern University Computer 

Architecture Research Lab. 



Temperature is another factor that substantially 

affects energy measurements. 

While EEMBC has determined that all 

of its measurements will be carried out in 

an ambient temperature of 70°F ± 5°, the 

device junction temperature has a marked 

effect on energy. As an example, Table 1 1 

lists the device current versus elapsed time 

for an Analog Devices BF533 Blackfin 

Processor. How temperature will be taken 

into consideration will have to be resolved 

during member deliberations. 

EEMBC’s benchmarks are traditionally 

focused on getting the job done as quickly 

as possible. However, in the “real world,” 

the primary challenge lies in predicting 

the right level of performance for the 

application. For some processor and/or 

system vendors, it may be more important 

EEMBC 

2222 Francisco Drive 

Suite 510-203 

El Dorado Hills, CA 95762 

Tel: 530-672-9113 

Fax: 530-672-9103 

E-mail: markus@eembc.org 

Website: www.eembc.org

S I D E B A R 

EEMBC 

membership 

growing 

The Embedded Microprocessor 

Benchmark Consortium (EEMBC) 

has announced that its membership 

has grown by 10 percent in the past few 

months with the addition of new board 

of directors and Java Subcommittee 

members. 

Since the end of 2003, the nonprofit 

industry-standard group has added 

Atmel, Cirrus Logic, and Faraday 

Technology to its full board members, 

and palmOne and Time Warner Cable 

to its Java Subcommittee. According to 

EEMBC, the growth signals increasing 

interest in objective performance 

measures for embedded processors 

and Java implementations. 

“The diversity of these five new 

members shows the growing acceptance 

and relevance of EEMBC 

benchmarks among and beyond 

the semiconductor companies that 

spearheaded their development,” said 

Markus Levy, EEMBC President. “In 

joining EEMBC’s Java Subcommittee, 

Time Warner Cable avails itself of the 

opportunity to select the best Java 

implementation in the next generation 

of set-top boxes, while palmOne will 

have an industry-standard tool for 

demonstrating Java performance 

capabilities on its handheld devices.” 

“For their part, our new semiconductor 

members – Atmel, Cirrus Logic, and 

Faraday Technology – are joining at an 

auspicious moment as the consortium 

is significantly updating its original 

application-based benchmark suites 

and launching new initiatives to 

develop benchmarks for Voice over IP 

(VoIP) and power consumption,” Levy 

added. 

For more information: 

www.eembc.org 



Zigbee Alliance 

Networking with ZigBee 

By Jon Adams 

ZigBee, the lightweight, robust wireless networking 

protocol and applications layer developed by the 

ZigBee Alliance, is getting close to releasing its 

final specification. Employing low-power, reliable, and 

inexpensive transceivers based upon the IEEE standard 

802.15.4, ZigBee devices will dramatically reduce the cost 

of deploying and operating wireless control and sensing 

networks over campuses, industrial or commercial 

buildings, and residential areas. 

IEEE 802.15.4 was released in May 2003, and since that release 

multiple vendors have announced single-chip silicon transceiver 

solutions that provide a straightforward way for non-RF-centric 

engineers to replace traditional, inflexible wired connectivity with 

wireless, without the pain that comes from building and supporting 

proprietary technologies. Some vendors, such as Freescale 

Semiconductor (a subsidiary of Motorola), offer development 

platforms that provide silicon, MCUs (Microcontroller Units), 

protocol stacks, development tools, and even reference applications 

to aid the developer or OEM in designing and producing their 

next-generation products. 

Let’s look at the specifics of the networking technology that 

ZigBee brings to the game. First, a ZigBee network, depending 

on the organization, can support tens of thousands of nodes. Many 

networks won’t be that large, but the flexibility is built-in. ZigBee 

allows for three different network topologies: Star Mode, Tree 

Mode, and Mesh Mode. ZigBee’s three network topologies are 

interconnectable, and each type is able to join a different topology 

if so desired and configured. 

Star Mode 

The simplest topology, Star Mode, is the traditional network one 

sees in the Wi-Fi world, where there’s a hub device (an Access 

Point), and then spokes that lead to a number of client devices. 

Figure 1 

For ZigBee, the star topology might be seen in simple scenarios 

like a small home, apartment, or other confined area where all 

devices are within range of the ZigBee Coordinator. While each 

RF hop is specified at 10-75m, practical environments with 

absorbing materials or conducting structures or surfaces mean that 

indoor ranges are probably 10-30m per hop. For the star topology, 

that means a network diameter of at least 20m, which is large 

enough for many confined environments. 

Tree Mode 

The tree mode topology provides for a different kind of network 

structure as shown in Figure 2. 

Figure 2 

Consider the ant living on Leaf A of an oak tree. The ant wants to 

visit his aunt living on Leaf N – but how to get there The ant has 

no difficulty on the inbound portion of the route to find the trunk 

– just walk on successively larger branches. Once at the trunk, the 

challenge is to find the branch with Leaf N out of all of the possible 

branches. If the addresses are distributed with respect to which 

branch each leaf is connected to, then even the outbound portion 

of the route is simple. Use the destination address to determine the 

route. This is similar to the way the Internet uses domain routing. 

Note however that each node has only one route toward the trunk, 

and if that route fails for some reason (tree sap or an ant-eating 

bug) the only option is to wait for the obstacle to clear or to find a 

way to build a new inbound branch bypassing the problem. ZigBee 

tree mode has sophisticated tree repair methods to compensate for 

this situation. 

Tree is especially valuable for sensing environments where all the 

devices are off mains power, potentially even running on primary 

batteries. Forest or agriculture management is one such space. 

Network beacons between adjacent connected nodes allow each 

device to know when the other device is listening, and they can 

sleep at other times to save precious battery energy. There is system 

latency in passing traffic (the beacon interval), but in return, the 

entire network can last for a very long time on battery power. 

Mesh Mode 

The mesh mode topography provides for a strongly robust, lowlatency 

network ideally suited for timing critical control and 

sensing applications, like lighting, HVAC, or machinery control 

(see Figure 3). 

Mesh mode uses the same basic address formation method as 

tree, handing out addresses that have a relationship to the initial 


Zigbee Alliance 

alternate routes via neighbors, and they always deliver low latency 

responses making them ideal for control networks where human 

perception times are important (e.g., turning on a light when 

entering a room). 

Meshes are by far the best choice for most ZigBee control networks. 

Meshes are populated by mains-powered control devices such as 

motor controllers, lighting load controllers, pumps, and other large 

load switching or controlling devices which are usually doubling 

as network routers due to the fact that they’re mains-powered. 

Input devices such as light switches, thermostats, and security 

sensors can take advantage of the mains-powered network devices 

and operate from batteries. Thus, the peel-n’-stick light switch or 

temperature sensor, which runs for the shelf life of an inexpensive 

alkaline cell is a real practicality with ZigBee. 

Figure 3 

position within the mesh, but go beyond tree in allowing for 

additional routes to improve robustness. Meshes are expected to be 

installed in buildings and facilities where the ZigBee Routers and 

Coordinator are mains-powered. For these devices, the receivers 

are always on, which allows the end devices (often battery-operated 

sensors, buttons, or other input devices) to sleep at all times except 

when an event occurs. Router/Coordinator devices hear all of their 

neighbors, which allows them to develop neighbor tables that 

record relative route quality (derived from signal strength) with 

respect to neighbor address. Also, since addresses are generally 

derived from their position in the mesh with respect to the 

coordinator, a node can estimate a neighbor’s position in the mesh 

based upon its address. Meshes heal easily due to the existence of 

Jon Adams is chair of the ZigBee Alliance’s 

Qualification Group and is the director 

of Radio Technology and Strategy for the 

Motorola SPS Wireless and Mobile Systems 

Group. Jon has written and spoken on these 

technologies and has provided regular 

interviews about the topics with industry 

analysts. 

Contact Jon at jta@motorola.com. 

Contact the alliance directly for membership and event details. 

ZigBee Alliance 

Tel: 925-275-6607 • Fax: 925-275-6691 

Website: www.zigbee.org 




Linux 

news 

Japan’s largest grid project uses Linux 

Networx Cluster System 

At the April 7, 2004 ClusterWorld Conference & Expo, Linux 

Networx announced that Japan’s National Institute of Advanced 

Industrial Science and Technology (AIST) has purchased and 

installed a 556-processor Evolocity II (E2) cluster system to join 

the AIST Supercluster. The Supercluster, a TFlops cluster built 

by AIST, integrates with another computing system to form 

Japan’s largest distributed computing grid. 

AIST is Japan’s largest public research organization with the 

mission to research and develop industrial science and technology, 

geological surveys, measurement standards, and technological 

applications for the private sector. 

“The GTRC aims to become the focal point of research and 

development in the grid communities in Japan and Asia-Pacific 

region. To accomplish this goal, we must have cutting-edge cluster 

systems that are reliable and powerful,” said Satoshi Sekigucki, 

director of the GTRC. “The cluster provided by Linux Networx 

and SGI will be a key contributor to the success of the Grid 

program, and we look forward to advances the cluster will make in 

our research programs.” 

For more information: www.linuxnetworx.com 

“Browser-based access is supplanting dumb terminals, front 

panels, and other proprietary client software for monitoring and 

controlling embedded applications,” McObject CEO Steve Graves 

said. “Integrating a Web server with the device almost eliminates 

the need for target programming to support operator interfaces, 

provides a ubiquitous client, and eliminates the need to port device 

management software from one desktop platform to another.” 

Linux 

For more information: www.mcobject.com 

NEWS 

LinuxQuestions.org adds a Linux User 

Groups (LUG) forum 

LinuxQuestions.org is proud to announce the addition of a Linux 

User Group (LUG) forum. The LUG forum will allow members 

of Linux User Groups around the world to post announcements, 

attract more members, coordinate meetings, and communicate 

with other LUGs. It also provides a resource for people who 

are interested in joining a local LUG, making it easier to find one 

in their area. Additionally, a calendar allowing LUGs to post 

Linux-related events is available. 

For more information: www.LinuxQuestions.org 

Linux is a registered trademark of Linus Torvalds. Other brand or product names are 

registered trademarks or trademarks of the respective holders. 

Equator announces Starfish hardware 

platform for Linux-based, multi-format 

Video-over-IP appliances 

Equator Technologies, Inc., a leading provider of high-performance, 

programmable and power-efficient System-on-a-Chip (SoC) 

processors for video streaming and image processing applications, 

recently announced the immediate availability of Starfish 

– a new embedded hardware platform designed for rapid deployment 

of low-cost and Linux-based, multi-format video-over-IP 

appliances. 

The Starfish hardware platform features a low-cost, single 

BSPTM-15 processor chip that handles all system and media 

functions. Equator’s BSP-15 SoC processor runs Linux and system 

software natively while delivering high-performance audio and 

video processing. The BSP-15’s advanced processor architecture, 

strong optimizing compilers, and on-chip MMU support fullfeatured 

Linux with memory protection, making multi-threaded 

complex application software more robust. 

For more information: www.equator.com 

McObject introduces eXtremeWS 

tiny-footprint embedded Web server for 

intelligent devices on Linux 

McObject has announced the final beta release on Linux of 

eXtremeWSTM, its embeddable HTTP server for intelligent, 

connected devices. With a footprint of less than 30K, low CPU 

consumption, and support for devices without a disk or file system, 

eXtremeWS extends the benefits of Web browser-based access to a 

wide range of embedded systems including industrial controllers, 

communications gear, consumer electronics, and other highly 

resource-constrained devices. 



InfiniBand 

and PCI Express 

subsystems: 

A winning 

combination for 

embedded applications 

By Lori Dunbar, Steve Cook 

Because they offer such high-performance and enormous scalability, switched 

fabric network architectures such as the InfiniBand architecture are ideal for 

embedded applications that require a high-speed, low latency data transport. 

These applications include weather modeling, networking, radar, communications, 

medical imaging, storage, sonar, industrial control, and many others. 

But high-performance embedded 

applications cannot live on 

InfiniBand technology alone. 

Data-intensive applications place 

demanding requirements on platform 

hardware, particularly the I/O subsystems. 

As such, a third-generation (3G) I/O bus 

is also needed to provide high-bandwidth, 

low latency connectivity for chip-to-chip, 

adapter cards, and other interconnects 

such as InfiniBand technology. There are 

other switched fabric architectures on 

the market – Rapid I/O and StarFabric 

among them – but over time, a de facto or 

established standard will emerge, driven 

by compatibility with popular I/O bus 

architectures. 

This article will focus on the InfiniBand 

switched fabric network architecture, 

citing its features/benefits for embedded 


applications, and detailing compatible I/O 

bus architectures. These I/O buses include 

PCI Express with a higher bandwidth, 

and scalable I/O technology that is 

compatible with the current PCI software 

environment; VITA-41, for connectivity 

to legacy VMEbus-based applications; 

and the Advanced Telecom Computing 

Architecture (AdvancedTCA) for the next 

generation of carrier grade communications 

equipment. 

In addition, because InfiniBand technology 

has gained market acceptance in the 

HPC (High Performance Computing) 

arena, it is likely that continuing investments 

in the core technology will make 

the technology more robust over time. And 

as InfiniBand technology gains critical 

mass, price/performance ratios should 

continue to improve. In short, this article 

will show developers why InfiniBand 

technology is well poised to become the 

defacto standard switched fabric network 

architecture for high-performance embedded 

applications. 

Local bus connectivity 

For inside-the-box communications, the 

most commonly used buses have been 

VMEbus (for embedded applications), and 

PCI bus (for commercial and embedded 

applications). The PCI bus is a multi-drop, 

parallel bus that is close to its practical 

limits of performance, and as such it cannot 

be easily scaled up in frequency, or 

down in voltage. Its synchronously clocked 

data transfer is signal skew limited, and 

the signal routing rules are at the limit. 

However, recent advances in high-speed, 

low pin count, point-to-point technologies

offer an attractive alternative for major 

bandwidth improvements for I/O communications. 

Originally called Third 

Generation I/O (3GIO), PCI Express 

is designed for use in chip-to-chip 

applications, and is likely to replace the 

PCI/PCI-X buses over time. 

PCI Express is defined as a serial I/O 

point-to-point interconnect that uses dual 

simplex differential pairs to communicate. 

The intent of this serial interconnect is 

to establish very high bandwidth communication 

over a few pins, versus low 

bandwidth communication over many pins. 

It also preserves customer investments in 

the PCI/PCI-X bus to facilitate migration. 

Celebrating its 20-year anniversary last 

year, the VMEbus is still going strong, 

especially in the military, aerospace, 

industrial control, and instrumentation 

markets. However, the need for higher 

performance has shaken up the VMEbus 

market somewhat. While military/ 

aerospace applications are not screaming 

for higher bandwidth at the moment, 

communications and other applications are. 

The new VITA-41 Specifications for the 

VXS backplane allows fabric architectures 

such as InfiniBand technology to run 

across the P0 (Port Zero) portion of a new 

VME64x-type backplane, extending legacy 

VMEbus-based systems dramatically. 

As shown in Figure 1, the new VITA-41 

VXS backplane allows InfiniBand fabric 

architectures to run across the P0 portion 

of a new VME64x-type backplane, thereby 

extending legacy VMEbus-based systems. 

AdvancedTCA is a new bus geared for 

the telecom and communications market 

that offers Gigabit/Terabit performance. 

AdvancedTCA, which is primarily a 

packet-based, switched-blade architecture, 

also interfaces with InfiniBand technology 

and other switch fabric architectures for 

outside-the-box connections. 

Switch fabric connectivity 

PCI Express, the VMEbus, and 

AdvancedTCA were designed for internal 

connections, whereas InfiniBand 

technology provides true fabric architecture 

for internal and external networks. 

Originally known as System I/O, InfiniBand 

supports circuit trace, copper wire, and 

optical fibers. InfiniBand architecture is 

a combination of Intel’s Next Generation 

I/O (NGIO), and Future I/O from IBM, 

HP, and Compaq. 

InfiniBand technology uses switched, 

point-to-point channels similar to those 

used in mainframes. InfiniBand technology 

provides a data path from 500 MBps to 

6 GBps between each pair of nodes, and 

is designed as a true fabric architecture 

that can extend connections via internal 

and external networks. 

InfiniBand technology is implemented 

differently with each local bus. For example, 

a device called the InfiniHost ® II Ex 

from Mellanox can connect directly to 

a PCI Express 8x (20 Gbps) link, and 

dual 10 Gbps InfiniBand links. As an 

additional example, SBS Technologies 

Figure 1 



offers an InfiniBand 4x Dual-Port PMC 

Host Channel Adapter (HCA) that is 

ideal for a connection to a SBC in an 

embedded system. As shown in Figure 2, 

SBS Technologies IB4X-PMC-2 HCA is 

based on Mellanox’s InfiniHost silicon and 

is capable of full wire speed transmissions 

over InfiniBand links. 

With both sides matched in speed, latencies 

are not expected as the PCI Express-to- 

InfiniBand interface enables processor 

level bandwidth throughout the system. In 

short, InfiniBand extends compute nodes 

through the use of PCI Express into an 

intelligent fabric-based cluster. 

InfiniBand is also suited to inside-the-box 

connectivity. A PCI Express-to-InfiniBand 

bridge can be implemented on nodes within 

a chassis such as a single board computer 

(SBC) with VITA-41 standard connectors. 

This is useful in applications where two 

cards need to communicate quickly without 

interrupting other cards in the same 

Figure 2 

chassis. For example, an application 

where data acquisition, processing, and 

display cards in three chassis – one for 

data acquisition, another for data processing, 

and a third to display the results 

– communicate with a traditional system. 

With InfiniBand on the backplane, the 

HCA/InfiniBand silicon can handle the 

networking overhead so the acquisition 

and processing nodes can concentrate on 

their own specific tasks. InfiniBand can 

send the results out-of-the box directly to 

a user’s display computer. 

InfiniBand features/benefits 

InfiniBand has many features and benefits. 

With 10 Gigabits per second full-duplex 

bandwidth for 4X, 30 Gigabits per second 

for 12X, and the announcement of future 

bandwidths up to 120 Gigabits per second, 

the InfiniBand Architecture is a highperformance 

interconnect technology 

that will meet the bandwidth needs of 

today and well into the future. InfiniBand 

technology not only provides high 

speed, but its intelligent fabric offloads 

the computer’s processing system from 

complex overhead and housekeeping tasks. 

InfiniBand technology accesses memory 

directly with its Remote Direct Memory 

Access (RDMA) feature which bypasses 

the CPU for information transfer, and this 

is essential when space and computing 

power are critical. 

As such, InfiniBand technology has caught 

the attention of the HPC market, which 

uses tens to hundreds of servers organized 

in clusters that often run on open source 

operating systems such as Linux. In 

fact, many big companies have replaced 

mainframes with HPC clusters linked by 

InfiniBand technology, thereby achieving 

a huge improvement in price/performance. 

The success of InfiniBand technology in a 

commercial market such as HPC almost 

guarantees that the price of silicon will 

continue to come down due to economies 

of scale, and the embedded market will 

realize these benefits as well. 


The primary component of InfiniBand 

architecture is the HCA that provides 


transport services over the switch fabric. 

The HCA, or more fundamentally, the HCA 

silicon chip allows the bridge between 

PCI-X/PCI Express and InfiniBand 

architecture. Fabric end nodes are either 

host nodes with HCAs, target nodes with 

Target Channel Adapters (TCAs), or as 

SBCs/nodes with integrated InfiniBand 

ports. As shown in Figure 3, the primary 

component of InfiniBand is the HCA that 

provides transport services over the switch 

fabric. Fabric end nodes are either host 

nodes with HCAs, or target nodes with 

Target Channel Adapters (TCAs). 

Extensive reliability and data integrity 

features are built into InfiniBand. The 

hardware automatically checks for data 

integrity at every step in the transfer of a 

packet which guarantees that a destination 

will reject corrupted data, and that a 

corrupted operation won’t corrupt adjacent 

data. In addition, each device in the fabric 

maintains its own separate clock and power 

domain, ensuring that a failed device 

only affects its own attached hardware 

link and associated queue pairs, and that 

communications between other devices in 

the system are unaffected. 

At the physical level, the InfiniBand 

architecture is implemented as a pointto-point 

packet switched fabric, which 

provides a basic scaling advantage. The 

addressing capabilities of the InfiniBand 

protocol allow as many as 48,000 nodes to 

“InfiniBand technology 

accesses memory 

directly with its Remote 

Direct Memory Access 

(RDMA) feature which 

bypasses the CPU for 

information transfer, and 

this is essential when 

space and computing 

power are critical.” 

be supported in a single subnet, and there are 

no theoretical limits to the size of a system. 

It scales up linearly, and performance 

doesn’t degrade as components are added. 

InfiniBand architecture provides fault 

tolerance through redundant components. 

The HCAs and TCAs are dual-ported to 

provide redundant connections if needed 

for failover. Most of the components are 

hot plugable, so if a component fails, it 

can be swapped out without powering 

down the chassis. InfiniBand architecture 

offers security through partitioning, where 

only members of a partition can see each 

other while others outside the membership 

cannot. The partitions provide security 

transparently while sharing common 

network components. This security scheme 

provides the end-to-end access control and 

authentication services. 

For real-time determinism, the switch 

fabric technology of InfiniBand architecture 

goes a long way to alleviate 

resource contention, which guarantees an 

upper threshold on message latency and 

jitter. InfiniBand architecture is flexible 

enough to handle isochronous traffic such 

as streaming video, while at the same time 

it accommodates more stringent levels 

of determinism. 

And surprisingly, InfiniBand architecture 

is more affordable than the other network 

technologies. It is expected to come in at 

roughly $300/port for Gigabit network 

performance at network/telecom market 

prices. 

Figure 3 

Conclusion 

While InfiniBand architecture has caught 

on with the HPC market in a big way, it 

remains to be seen if it will become the 

switch fabric of choice for embedded 

applications. InfiniBand architecture is 

compatible with PCI Express at the silicon 

level (which is likely to be deployed 

everywhere), not to mention the VXS 

backplane via the VITA 41.1 Specification 

(which couples it with legacy embedded 

applications), as well as AdvancedTCA (the 

new bus for high-speed communication in 

the telecom market). As such, InfiniBand 

technology stands a very good chance to 

succeed as the standard switched fabric 

network architecture for high-performance 

embedded applications. 

InfiniHost is a registered trademark of 

Mellanox. Other brand or product names 

are registered trademarks or trademarks 

of the respective holders. 

For further information, contact Lori and 

Steve at: 

SBS Technologies 

Corporate Headquarters 

2400 Louisiana Blvd. NE Suite 5-600 

Albuquerque, NM 87110 

Tel: 800-727-1553 • Fax: 505-875-0400 

E-mail: ldunbar@sbs.com 

E-mail: scook@sbs.com 

Website: www.sbs.com 



The current landscape 

of 

switch fabrics 

and RapidIO 

As system 

designers strive for higher 

levels of speed, bandwidth, and performance in 

embedded systems, traditional intrasystem interconnect structures 

based on hierarchical buses have begun to fall short in their ability to provide 

the necessary functions. Despite the application of novel techniques to further 

exploit bus-based approaches, the resulting complexity and need to balance 

competing design issues have limited their broad applicability. 

The increasing use of high-bandwidth smart peripherals, as well as the advantages 

of direct communications between various system devices and elements, 

has brought bus-based interconnect technologies under further scrutiny. 

To combat the inadequacies of traditional interconnect structures that have risen 

from the modern requirements of embedded system designers, several switch 

fabric technologies have come into play – each vying for its own foothold in 

the market. 

Although there are over 60 switch fabrics currently documented, with several 

more anticipated to show up on the scene, there are only a few that utilize an 

open architecture platform, thereby making them available to the broadest 

number of users and increasing their chances of utilization in the marketplace. 

Here, we’ll examine some of the most widely adopted open architecture fabrics 

to provide an overview and comparison of each, then we’ll focus on some recent 

developments to RapidIO, one of the leading open architecture switch fabrics. 

By Luc Torres 

The Ethernet legacy 

Because Ethernet is one of the original 

switch fabric technologies, it stands to 

reason that it is one of the most widely 

used. However, because of Ethernet’s 

slower performance, its use has been 

primarily in the field of industrial control 

and medical imaging. Faster versions 

of Ethernet, both gigabit and 10-gigabit 

versions, are in development and will help 

expand its use in different applications. 

However, Ethernet commands a significant 

amount of a system’s processor load, since 

it mandates that data be shared when a 

series of I/O packets are sent. This decreases 

some system functionality, since 

much of the processor’s capacity is used 

to transfer the data packets. 

The InfiniBand factor 

The InfiniBand Trade Association 

(www.infinibandta.org), a membersupported 

organization that heads the 

development of the InfiniBand protocol, 

defines the architecture as a unified 

fabric that takes I/O outside of the 

box and provides a mechanism to share 

I/O interconnects among many servers. 


Because Infiniband can incorporate other fabrics, it can efficiently connect storage and 

communications networks and server clusters together, while delivering an I/O infrastructure 

that will produce the efficiency, reliability, and scalability that data centers demand. 

Unlike Ethernet, Infiniband requires little to no processor load, making it better suited 

for data-intensive applications. Also, it enables the processor to share memory, although 

systems incorporating this fabric still suffer from slower processing speeds. 

The PCI Express approach 

PCI Express, originally introduced by Intel in 2001 as 3GIO (3rd Generation I/O), was 

designed to provide higher bandwidth and faster speed as well as to address chip-to-chip 

connections, out-of-the box connections, and add-on-card connections. It consists of 

multiple, point-to-point serial connections called lanes that can be used to create an I/O 

interconnect with a linearly-scalable bandwidth. 

PCI Express also enables processors to 

share some system resources, such as 

memory, increasing the functionality of 

the overall system. 

The StarFabric standard 

Also an extremely popular switch fabric, 

StarFabric was originally developed by 

StarGen. The organization now tasked 

with the development and promotion 

of this standard is the StarFabric Trade 

Association (www.starfabric.org), also 

a nonprofit, open membership industry 

group. 

StarFabric is an open interconnect standard 

that provides high levels of scalability, 

performance, and availability in a wide 

range of systems. It supports multiple 

classes of traffic for added flexibility and 

enhancements to systems while leveraging 

existing standards-based software and 

hardware investments. 

As with Infiniband and PCI Express, 

StarFabric enables the resources of a 

system to be shared, including memory, 

which enables the load on the processor 

to be greatly reduced. 

RapidIO…the future fabric 

of choice 

RapidIO, the last of the open interconnect 

standards that we’ll discuss, was designed 

to be compatible with the most popular 

integrated communications processors, 

host processors, and networking digital 

signal processors. 

According to the RapidIO Trade 

Association (www.rapidio.org), it is a 

high-performance, packet-switched, 

interconnect technology that addresses the 

embedded industry’s need for reliability, 

increased bandwidth, and faster bus 

speeds in an intrasystem interconnect. The 

RapidIO interconnect allows chip-to-chip 

and board-to-board communications at 

performance levels scaling to ten gigabits 

per second and beyond. 

RapidIO has had some significant advancements 

take place over the past few 

months. In December 2003, the International 

Standards Organization (ISO) 

and the International Electrotechnical 

Committee (IEC) ratified the RapidIO 1.2 

interconnect specification as ISO/IEC DIS 

18372. To date, RapidIO is the only one 

of the over 60 switch fabrics currently 

available to receive this designation. 


The ratification of a standard by ISO 

(www.iso.ch) requires that both vendors 

and end users of the technology develop 

the standard in an open forum that fosters 


input, feedback, and communication from 

all parties involved. 

The ISO’s website states that standards are 

developed when “the need for a standard 

is felt by an industry or business sector, 

which communicates the requirement to 

one of ISO’s national members. In order 

to use resources most efficiently, ISO 

only launches the development of new 

standards for which there is clearly a 

market requirement.” 

The desire for RapidIO’s ISO recognition 

was driven by key original equipment 

manufacturers (OEMs) and by the RapidIO 

Trade Association, which engaged with 

the ECMA, originally called the European 

Computer Manufacturers Association, 

out of Geneva, Switzerland. Through the 

ECMA, a liaison working group, TC42, 

was formed to help facilitate the adoption 

of the standard. 

The other significant development for 

RapidIO was the first peer-to-peer RapidIO 

exchange that recently took place on two 

of Thales Computers’ PowerNode3 cards 

equipped with two RapidIO PMCs (see 

Figure 1). 

RapidIO’s 3-layer hierarchical architecture includes the physical layer at the low end, 

which mediates device-level interfaces and electrical characteristics; the transport layer that 

enables the correct routing of packets from sender to recipient; and the layer that defines 

packet formats and the overall protocol, the logical layer. 

RapidIO has been designed to minimize transaction overhead, which in turn reduces 

latency and maximizes bandwidth. The switched nature of RapidIO enables it to provide 

both multicast routing (sending a packet to multiple connected devices), and source 

routing (sending a packet only to a specific source-defined destination device). Source 

routing means that the transaction is routed according to the destination ID specified by 

the source device. 

Benefits for embedded applications 

Because of its relatively small packet size (maximum data payload of 256 bytes), as well 

as its ability to forward messages prior to complete receipt, a key feature of RapidIO is 

that it maximizes throughput and minimizes latency during message routing. 

With these basic attributes in mind, it is useful to consider how RapidIO can play a role 

in both existing legacy systems and new systems. Legacy systems especially benefit from 

the transparency of RapidIO, since these systems typically utilize one or more generations 

of memory-mapped I/O software. RapidIO’s load/store architecture, which is similar to 

PCI, enables system designers to map a full PCI bus, including interrupts, while using the 

existing software drivers. 

RapidIO’s physical characteristics, such as low power consumption and a limited silicon 

footprint (transistor count), are ideal for harsh environments. Again, both new and legacy 

systems benefit, since low power draw and space efficiency are primary concerns. The low 

pin count of RapidIO also enables designers to preserve user-defined pins for existing or 

new applications. 

Figure 1 

Phase II of Thales’ expansion of RapidIO 

on its processor cards is to build a wider topology 

of four cards, and ultimately expand 

the exchange on up to 12. Additionally, 

the company’s Serial RapidIO cards are 

due out towards the end of Q3 2004. 

With these recent developments, the embedded 

industry will see the expansion of 

RapidIO in even more products to increase 

efficiency and meet today’s embedded 

system requirements. 

A RapidIO overview 

Particularly suited for systems that incorporate 

multiple devices in a tightly 

coupled architecture, such as real-time 

embedded applications, RapidIO provides 

all of the necessary tools to facilitate data 

movement in the control plane. 



Hardware-based error detection and recovery inherent in RapidIO, when appropriately 

configured, enable the fabric to provide redundancy at both the data link and switch levels. 

A high-throughput signal processing application using RapidIO is shown in Figure 2. 

“Minimal hardware and 

software modification are 

required to implement 

RapidIO on existing 

backplanes...” 

Data requiring priority-based delivery can 

be transferred using RapidIO, enabling 

a smooth transition from existing busbased 

approaches. Minimal hardware 

and software modification are required 

to implement RapidIO on existing backplanes, 

so it can be easily added during 

scheduled LRU replacements or upgrades. 

Figure 2 

RapidIO also offers scalability, enabling it to accommodate multiple intrasystem connection 

requirements. RapidIO provides high-speed data links between a single-board computer 

(SBC) and one or more PMC carriers as well as extremely high throughput for onboard 

data pathways between memory and processor units on smaller systems. RapidIO as a 

carrier for PCI Mezzanine extensions is shown in Figure 3. 

Figure 3 

For bigger systems, not only can RapidIO provide distributed packet switching for between 

4 and 10 SBCs and their attached sensors, it can also be used in a more expansive full mesh 

VXS application, as well as an external switch between multiple chassis or racks. 

RapidIO’s ability to accommodate multiple operating frequencies and bandwidths enables 

the optimization of multiple connection modes. The Parallel RapidIO specification 

defines four possible operating frequencies from 250 MHz to 1 GHz, and 8-bit and 16-bit 

bandwidths; the Serial RapidIO specification defines three operating frequencies from 1.25 

to 3.125 GHz, and two widths 1x and 4x. 

In each direction within the RapidIO link, data bandwidths range from a Gbps, in Serial 

1.25 GHz @ 1x, to approximately 60 Gbps, in Parallel 1 GHz @ 16-bits. Embedded VME 

systems benefit from the multiple connections available when implementing RapidIO. 

A configuration of RapidIO-based signal processing network using eight dual processors 

is shown in Figure 4. 

Figure 4 

In its upper performance ranges, RapidIO 

provides bandwidth comparable to 

Infiniband, Fibre Channel, or high-speed 

Ethernet. However, these technologies are 

more appropriately targeted to intersystem, 

rather than intrasystem connections. 

Each fabric has its own unique purpose 

but, in general, they cannot supply the 

compatibility provided by RapidIO’s 

load/store architecture, or the capability 

for supporting deterministic performance 

that would enable them to be useful for 

intrasystem interconnects, especially when 

upgrading or enhancing existing legacy 

systems. At this point, RapidIO provides 

the best combination of high bandwidth, 

low latency, transparency, and adaptability 

required to support the next generation 

of embedded systems and their attached 

devices. 

Luc Torres, 

Marketing Product 

Manager for Thales 

Computers in 

Toulon, France, has 

extensive project and 

product management 

experience. He 

has held various 

managerial positions in the engineering 

and marketing departments of IBM 

Corporation and Hewlett-Packard. Luc 

has a degree in Electrical Engineering. 

For further information, contact Luc at: 

Thales Computers 

3100 Spring Forest Road 

Raleigh, NC 27616 

Tel: 800-848-2330 • Fax: 919-231-8001 

E-mail: lto@thalescomputers.fr 

Website: www.thalescomputers.com 



TIPS 

By Eric Cigan 

In this article, Eric gives an overview of the benefits of using FPGAs in DSP design 

and concludes with a list of recommended design rules. 

Challenges of FPGA-based 

DSP design 

Not long ago, designers of highperformance, 

digital signal processing 

systems (DSPs) had two alternatives for 

implementation – general purpose DSPs 

or ASICs. General-purpose DSPs, such 

as those from TI, Agere, Motorola, and 

Analog Devices are special-purpose 

microprocessors optimized for common 

DSP operations. The benefit of generalpurpose 

DSPs is that they are the fastest 

method to get an algorithm running 

because they offer a comprehensive development 

environment, with tools for 

code analysis, debugging, and rapid 

prototyping. The disadvantage of DSPs is 

that ultimately they execute instructions 

serially, setting an upper limit on the 

chip’s throughput. 

ASICs offer the ability to break through 

these performance limitations. Custom 

ASIC design lets the designer employ the 

optimal mix of resources on a chip and to 

place them in close physical proximity to 

minimize delays. Moreover, ASICs are 

ideal for use in portable electronics since 

the flexibility of ASIC design allows the use 

of processes and architectures optimized 

for lower power consumption. The drawbacks 

of ASICs are considerable: 

■ They need to be fabricated. 

■ They require more time to design. 

■ They require more complex and expensive 

development tools. 

■ A single design flaw could lead to a 

design respin causing additional cost 

and delay. 

In the past, given these two choices, most 

designers avoided ASICs unless absolutely 

necessary. 

Two trends have recently changed 

the landscape. First, the demand for 

high-performance DSPs has increased 

dramatically due in part to the growth in 

multimedia and communications systems. 

Products as diverse as 3G wireless base 

stations, medical diagnostic imaging 

equipment – even driver-assist systems 

that will automatically park a car – would 

be inconceivable without the use of 

advanced DSP algorithms. The throughput 

requirements of these systems has strained 

the abilities of general-purpose DSPs. 

For example, one leading manufacturer 

of advanced echo cancellation systems 

incorporated more than 25 generalpurpose 

DSPs on a single board to meet 

their performance goals. 

A new generation of programmable chips 

has emerged as an alternative to standard 

DSPs. Platform FPGAs such as Altera’s 

Stratix II and Xilinx’s Virtex II, incorporate 

arrays of dedicated multipliers, embedded 

memory, and high-speed I/O that make 

them ideal for DSP applications. The 



silicon resources of an FPGA lead to 

staggering performance gains – while the 

fastest general purpose can deliver up to 

5 billion MAC/s (multiply-accumulate 

per second), leading FPGA devices can 

deliver more than 500 billion MAC/s – 

that’s more than 100x faster. What’s more, 

channelized applications such as those 

common to wireless communications 

naturally lend themselves to parallel implementations 

in FPGAs. Growth rates 

in processing speed requirements versus 

capabilities are shown in Figure 1 1 . A 

comparison of general purpose DSPs 

versus FPGAs is shown in Table 1 2 . 

Tips for DSP design 

Let’s now take a close look at how designers 

navigate the challenges of using FPGAs in 

design to avoid prolonged design cycles 

or reduce the component cost for end 

products. It comes down to the following 

basic rules. 

1 

Figure 1 

Rule #1 

Start at the beginning. 

Complex DSP designs start with an 

algorithm developer who creates the initial 

design based on existing designs and 

experience. According to the DSP market 

research firm Forward Concepts, the leading 

tool for algorithm design is MATLAB 

from MathWorks. Using the MATLAB 

language, algorithm developers can create 

designs in a natural and productive form 

and may tap into an immense wealth of 

designs, scripts, and engineering knowhow 

available only in the MATLAB 

language. Though designers can choose 

from other options including blocklevel 

environments, such as Simulink 

or SPW, or languages based on C/C++, 

these environments are less widely used 

and there may not be as many designs 

available for them. Moreover, many 

constructs used in DSP designs – such as 

looping, repeated structures, and 2- or 3- 

dimensional data arrays – are much easier 

to represent in MATLAB than in blocklevel 

environments. Once the algorithm 

is created in MATLAB, it can be readily 

shared or partitioned across a design team 

and reused over time. 

2 

Rule #2 

Avoid recopying your work 

(or alternatively, “Don’t get 

lost in translation”). 

Once the algorithm is available, the rest 

of the design team, including hardware 

designers, software developers, and system 

designers who integrated the design 

components, swings into motion. In the 

past, the completed algorithm in MATLAB 

became the executable specification, 

which meant that the hardware designer 

and software developers needed to recreate 

the design. 

Many embedded systems developers 

are accustomed to implementing DSP 

algorithms on general purpose DSPs in C 

or assembly language. This puts hardware 

and software engineers into the role of 

translating designs from one language to 

another, creating many opportunities for inserting 

errors with the attendant debugging 

process. To avoid this process altogether, 

companies are looking to architectural 

synthesis tools that use the MATLAB 

M-file as the golden source for downstream 

design, automatically synthesizing the 

design at the Register Transfer Level 

(RTL). Coupled with traditional RTL 

synthesis tools that can synthesize RTL to 

gate-level implementation, this establishes 

an unbroken design flow from algorithmic 

creation to hardware implementation. 

The top-down design process is shown in 

Figure 2. 

Function 

Industry leading, general 

purpose, DSP processor core 

Industry leading 

platform FPGA 

8x8 Multiply Accumulate 4.8 Billion MACps 1 Trillion MACps 

(MAC) f clk = 600 MHz f clk = 300 MHz 

FIR Filter 

– 256 Taps, Linear phase 9.3 Msps 300 Msps 

– 16-bit data/coefficients f clk = 600 MHz f clk = 300 MHz 

Complex FFT 10 µs 1 µs 

– 1024 point, 16-bit data f clk = 600 MHz f clk = 150 MHz 

Viterbi decoding 500 channels at 7.95 Kbps 155 Mbps (OC-3 rates) 

throughput 

for a total of 3.9 Mbps 

Reed-Solomon decoding 4.1 Mbps 10 Gbps (OC-192 rates) 

throughput f clk = 600 MHz f clk = 85 MHz 

Turbo convolutional Six 2 Mbps data streams 5.4 Mbps 

decoder throughput (6 iterations) (6 iterations) 

Table 1 

Figure 2 


3Rule #3 

Always check your work – 

use a verification flow that is 

complete. 

In any design process, it’s essential to be 

able to verify that the design meets the 

higher level specifications. If the design 

starts as a floating-point algorithm in 

MATLAB – also called an M-file – the 

fixed-point M-file should behave within 

an acceptable range of the floating-point 

M-file. The RTL implementation should 

then conform precisely to the fixed-point 

M-file – in other words, the RTL should 

be bit-true to the floating-point M-file. 


But how does the engineer determine that 

the design matches all the way through 

The proven method for verifying designs 

in top-down flows is via a testbench that 

feeds the design under test with its input 

stimulus and monitors whether its outputs 

match the expected results. Designers 

should create testbenches that allow this 

methodology to be employed using HDL 

simulators, but better yet, they should seek 

out tools that automatically generate an 

RTL testbench from the original design 

and use an HDL simulator to simulate and 

functionally verify the design including 

4bit-true operation. 

Rule #4 

Don’t reinvent the wheel. 

DSP systems incorporate a number of 

building blocks that are common to most 

designs – FIR and IIR filters, fast Fourier 

transforms and discrete cosine transforms, 

channel coding, etc. Developing these 

functions from scratch comes at great 

expense; in fact, according to Berkeley 

Design Technology, Inc., developing a 

new FFT in silicon can consume up to six 

months. Designers need to adopt tools and 

techniques that provide access to a large 

and growing variety of DSP intellectual 

property (IP) that is geared towards DSP 

design. While there are many sources for 

IP in hard form (laid out on target silicon) 

or in soft form (delivered in synthesizeable 

RTL), typically there is no corresponding 

simulation model available in MATLAB. 

This breaks the verification flow, making 

it difficult for the algorithm developer 

and the hardware designer to validate that 

the algorithm is faithfully represented 

in silicon. 

5 

Rule #5 

Use your budget wisely. 

DSP algorithms are almost always 

developed using floating-point arithmetic, 

giving the algorithm developer the ability 

to evaluate a design in its best case 

scenario. While general-purpose DSPs are 

typically designed to perform 16- or 32-bit 


arithmetic, implementing algorithms in 

FPGAs or ASICs gives the designer the 

ability to independently control the number 

of bits used to represent each number 

in the algorithm. Using too may bits can 

be costly – a 40% increase in the number 

of bits in a multiplier can double its area 

in silicon – but using too few can lead to 

overflows or instabilities. When choosing 

tools for implementing DSP algorithms 

in silicon, designers should evaluate tools 

that help automate this floating-point to 

fixed-point conversion process. 

6 

Rule #6 

Keep your options open 

with vendor-independent, 

technology-independent flow. 

As designers, we are all increasingly 

under pressure to cut costs, which often 

leads to having to select the supplier who 

can provide the lowest price, the best 

availability, etc. The tools available in the 

market fall into two categories. 

Vendor-supplied tools are available from 

companies offering FPGA devices for 

DSP and provide integrated environments 

spanning graphical design entry, IP 

block libraries, and RTL simulation and 

synthesis tools. But, these tools offer 

libraries of DSP functions that can only 

target a single vendor’s devices. To convert 

a design from one vendor’s tools to another 

is at best a time-consuming and errorprone 

process, leaving the designer at the 

mercy of the vendor in terms of the cost 

and availability. 

Vendor-independent tools provide a more 

flexible alternative. Once the design is 

captured, it can easily be retargeted from 

one device family to another from the 

same vendor, and can even be retargeted to 

an entirely different family of FPGAs. Yet 

another advantage of vendor-independent 

flows involves the need to retarget the same 

design to different silicon technologies. 

Companies find that they can meet their 

need for first silicon using FPGAs, and 

then incorporate structured ASICs or 

ASICs as they become available from 

product lines. While vendor-supplied tools 

provide IP that is only available for FPGA 

devices, vendor-independent tools allow 

designers to retarget the designs without 

changing the golden design source. 

7 

Rule #7 

Given the time, you can 

always make a design better 

– use design exploration. 

Almost invariably, getting the functionality 

of the design correct is just the beginning 

– then begins the pursuit of improving 

performance to make specs and trying 

to shrink to a smaller device or go to a 

slower speed grade to cut costs. Hardware 

engineers have an arsenal of tools and 

tricks at their disposal, but working at 

gate-level – even at RTL level – has its 

limits. Inserting intermediate registers 

can be difficult. Optimizing quantization 

throughout a design is particularly tedious 

and error-prone when changing at the RTL 

level. And, if the algorithm developer 

comes up with a brilliant new idea two 

weeks into the hardware design, chances 

are that the project manager will decide to 

stick with the old design rather than risk 

the entire project schedule. 

“To convert a design from 

one vendor’s tools to 

another is at best a 

time-consuming and 

error-prone process...” 

The greatest benefits can be realized 

by keeping the original floating-point 

MATLAB source file as the golden source 

for all design and using algorithmic 

synthesis tools that synthesize from 

MATLAB to RTL. Using architectural 

synthesis tools such as AccelChip DSP 

Synthesis, the algorithm designer can 

make changes to the design well into 

the flow, resynthesize to RTL, and work 

with the hardware designer to determine 

whether the design performance and 

device utilization has improved. Possible 

trade-offs given different levels of abstraction 

are shown in Figure 3. 

Figure 3 

Wrapping up 

Implementing DSP algorithms in silicon 

used to be a task reserved for only the 

most highly skilled and best equipped 

design teams. The demand for a more 

efficient path from algorithm to an ASIC 

or FPGA has given rise to a new breed of 

EDA companies, such as AccelChip, that 

bridge the gap between DSP algorithm 

development and silicon. Architectural 

synthesis tools such as this accelerate 

design and implementation by automatically 

synthesizing algorithms written 

in floating-point MATLAB model to 

synthesizable VHDL or Verilog models 

suitable for standard ASIC and FPGA 

design flows. AccelChip’s toolset also 

enables rapid design exploration targeting 

fidelity, performance, area, and cost 

tradeoffs for optimal results while using 

MATLAB as a golden source. 

Eric Cigan is the Product Marketing 

Manager for AccelChip Inc., and is 

responsible for product planning and 

promotion for the AccelChip product 

family. He has more than fourteen years’ 

experience in the EDA industry. 

Reference: 

1. Xilinx, June 2003. 

2. Xilinx website. 

For further information, contact Eric at: 

AccelChip Inc. 

1900 McCarthy Blvd., Suite 204 

Milpitas, CA 95035 

Tel: 408-943-0700 • Fax: 408-943-0661 

E-mail: eric.cigan@accelchip.com 

Website: www.accelchip.com 



Tips for designing 

complex FPGAs 

By Salil Raje 

Field Programmable Gate Arrays (FPGAs) are becoming more attractive than 

Application Specific Integrated Circuits (ASICs) to design teams developing nextgeneration 

electronic products. That’s due to a variety of reasons including their 

increased gate counts, versatility, and lower development and manufacturing costs. 

FPGA devices are now being fabricated in advanced, ultra-deep submicron technology 

with multi-million gate capacity, and clock speeds approaching 400 MHz. With these 

larger, more complex FPGAs come new design challenges, including problems associated 

with interconnect delay. In this article, Salil provides tips for FPGA design. 

Interconnect delay 

As witnessed when high gate-count, deep submicron ASIC designs 

first appeared, interconnect delay accounted for as much as 70 to 

90 percent of overall circuit delay as feature sizes shrunk below 

0.18µm. Large designs also impact cycle time because of increased 

place and route runtimes, and an increased number of design 

iterations needed to reach performance goals. Unfortunately, 

Electronics Design Automation (EDA) software used to design 

FPGAs has remained largely unchanged over the years, and is 

unable to adequately address these problems. 

Advanced EDA tools 

What’s needed are advanced ASIC-style EDA software tools and 

methodologies that provide FPGA designers hierarchical, blockbased 

design techniques to identify, analyze, and correct problems 

early in the design cycle. This, in turn, will lead to fewer design 

iterations. Advantages to implementing advanced ASIC-style 

techniques include quicker incremental design changes, improved 

performance, Intellectual Property (IP) reuse, faster place and 

route, and tighter utilization control. Designers perform early 

analysis and planning to maximize performance, and thereby avoid 

lengthy and repeated iterations. 

Hierarchical design 

The latest advancements in FPGA software provide hierarchical 

design capabilities that enable designers to partition their physical 

design into smaller, more manageable pieces. This significantly 

reduces the time to understand, verify, and implement the design. 

Partitioning also provides an incremental design methodology 

that reduces iteration times for implementing Engineering Change 

Orders (ECOs). Breaking a design into smaller pieces can also 

reduce runtimes, and the computer resources necessary to place 

and route the design. 

Place and route 

Using the latest FPGA design tools, designers can improve circuit 

performance by applying advanced floorplanning and static timing 

analysis techniques early in the design process. Designers can use 

early congestion analysis to help them select the appropriate FPGA 

device, and optimally place the logic within it. This results in a 

reduced number of iterations between each phase of the design 

process, and a reduced overall time to reach timing closure. 

Place and route has far greater difficulty with designs that are 

flattened – that is, without hierarchy – yet most FPGA software 


still operates on a flat netlist. With a flat methodology, even a minor 

design change isolated within a single logic block necessitates a 

complete rerouting of the entire netlist. Not only is place and route 

lengthy for a flattened netlist, it may take many iterations before 

the design again reaches the desired performance. 

Using ASIC-style design techniques, designers draw on hierarchy 

to help place and route achieve better results, often using less 

computational resources. By breaking their designs into smaller 

blocks, they don’t need to run place and route on the entire design 

each time they make an incremental design change. Instead, they run 

place and route on the block affected by the design change, while 

they leave the rest of the physical implementation intact. Using 

such a block-based flow, they can also sequentially implement and 

assemble their designs. They can start with the most critical blocks, 

and successively place and route additional blocks as designers 

complete the logic contained within. 

When designing using a flat methodology, a designer often tries 

to reach timing goals by trying multiple routing runs, each with 

different random seed values, hoping that one of them will produce 

a design with adequate performance. A hierarchical methodology 

provides a more deterministic process, by enabling designers to 

define area groups to steer place and route towards acceptable 

timing values. This serves to further stabilize the place and route 

process, which makes the results more reliable and predictable. 

Parameter management 

Designers of large FPGAs iterate their physical implementations 

many times because they are trying to cope with too many 


RSC #3702 @ Embedded www.embedded-computing.com/rsc 

Computing Design Summer 2004 / 37

simultaneous physical parameters such as connectivity, utilization, 

I/O placement, clock regions, power, and timing. Without 

ASIC-style techniques, there is little guidance for designers 

to know which parameters must be manipulated to reach their 

requirements until place and route has already occurred. Worse, 

many requirements are interrelated; manipulating parameters 

to achieve one requirement often causes problems in achieving 

several others. Consequently, designers spend too much time 

iterating their designs. 

Floorplanning 

ASIC-style design tools help designers reach their requirements, 

prior to place and route, through early design analysis 

tightly coupled with floorplanning. With floorplanning and 

analysis, the designer can substantially reduce the number and 

length of place and route iterations by reviewing early feedback 

about the physical design. 

For example, early connectivity analysis may uncover a potential 

area of routing congestion. The designer can then change the 

floorplan to alleviate the problem, rather than wait for lengthy and 

inconclusive place and route results. By adjusting the floorplan, 

place and route algorithms have the necessary partitioning, block 

arrangement, and physical constraints for guiding place and route 

to an early success. More efficient floorplans generally lead to 

improved timing, and reduced place and route time. 

Static timing analysis 

Advanced FPGA design tools also provide physical optimization 

later in the design cycle, to address implementation problems 

that may arise after place and route. For instance, designers can 

run static timing analysis to find all the remaining critical paths 

in their design that do not meet timing requirements. They can 

then grab all the logic in these critical paths, and place them in 

a small block, thereby constraining interconnect and minimizing 

delay. The designer can then run a timing analysis to see if 

performance has benefited. By this process, designers get nearly 

instantaneous feedback, rather than waiting for hours of place and 

route to complete. 

Utilization 

Utilization is an important aspect of FPGA design. In some cases, 

it’s necessary to crowd as much logic into a given device as 

possible to meet production volume requirements. In other cases, 

some amount of spare space is desirable to accommodate bug 

fixes, naturally occurring design changes, ECOs, or even future 

planned field upgrades. 

Using block-based, hierarchical design techniques, it is easier 

to control utilization. Designers trying to maximize utilization 

can set utilization controls to a given level, then run blocklevel 

place and route. If it produces successful results, they 

can change the utilization setting to shrink the block, then rerun 

block-level place and route. This process can continue 

until place and route fails, which means the designer has 

achieved the maximum possible utilization for the given block. 

Designers who need to leave some amount of spare space in 

their designs can use a lower utilization setting for blocks where 

extra space is needed. A wise technique is to leave more space in 

blocks that have yet to be verified to accommodate anticipated bug 

fixes. Designers may need less spare space in blocks that are 



field-proven, since it is unlikely that extra space will be needed 

to fix bugs within them. Designers can also create hierarchical 

blocks that make efficient use of fixed resources such as RAM 

and multipliers. 

Design workflow 

Like ASIC designers, FPGA designers can accelerate design time 

by working as a team, and by reusing intellectual property from 

previous designs. Using ASIC-style design techniques enables 

teamwork and IP reuse. Designers can take a block-based approach 

to divide their work into more manageable pieces, and assign 

responsibilities of designing them to individual team members. 

Designers can also reuse blocks from previous designs, or even 

purchase them from a third party to save design and verification 

time. 

By employing ASIC-style techniques, designers can fully 

characterize their design blocks by freezing the placement within 

them so that power, timing, and other characteristics remain 

constant wherever they are used. They know that these blocks meet 

their physical requirements, and they can connect them to form 

larger designs that also meet their requirements. 

An example 

One challenge when designing with today’s complex FPGAs is that 

they have a limited amount of internal memory, and moving data 

to and from external memory frequently becomes a bottleneck. It 

would save a significant amount of time if FPGA designers could 

reuse standard high-speed memory interface blocks, with consistent 

performance, from one design to another. 

Figure 1 shows how one company designing FPGAs did just that. 

In this case, they used the PlanAhead software from Hier Design, 

to create the memory interface blocks and to reuse them with 

floorplanning. Using the tool they were able to lock down and 

ensure the consistent performance of critical memory interface 

blocks such as PCI and DDR. This ASIC-style flow created and 

managed the physical constraints for all the logic inside of the 

memory interface blocks, which led to a successful place and 

route. Figure 1 shows reused external memory interface blocks 

within a floorplan. 

Figure 1 




The same reuse methodology also comes in handy for internal, 

block-level interface logic. Figure 2 shows module interfaces as IP 

blocks, locked down for reliable performance so they can be reused 

on other designs. 

Figure 2 

In this case, there was a PowerPC core (shown in yellow) that was 

surrounded by IP blocks that interface it to the rest of the design. As 

with the memory interface blocks, the logic blocks that surround 

the PowerPC core were locked down using physical constraints 

created and managed by an ASIC-style methodology. 

Conclusion 

FPGA designers are grappling with long place and route time, too 

many design iterations, and difficulty reaching and maintaining 

physical design requirements. They can overcome these problems 

by adopting ASIC-style techniques that enable them to reach design 

closure faster, improve performance, reuse intellectual property 

with consistent results, and ease incremental design changes. 

Salil Raje is the Chief Technology Officer 

(CTO) and cofounder of Hier Design. 

Previously, he was director of research and 

development at Monterey Design Systems 

where he was responsible for the development 

of physical prototype and analysis software. 

At Monterey, he was awarded four patents, 

with another two that are pending. Prior to 

Monterey, he worked at IBM’s T.J. Watson Research Center. 

Dr. Raje received a Bachelor of Technology degree in Electrical 

Engineering from the Indian Institute of Technology, in Madras, 

India. He completed a Master of Science degree, and a Ph.D. in 

Computer Science at Northwestern University in Chicago. 

For further information, contact Salil at: 

Hier Design, Inc. 

2350 Mission College Boulevard • Suite 850 

Santa Clara, CA 95054 

Tel: 408-982-8240 • Fax: 408-982-3838 

E-mail: salil@hierdesign.com • Website: www.hierdesign.com 



Leveraging FPGA 

coprocessors 

to optimize 

automotive 

infotainment 

and telematics 

systems 

By Paul Ekas 

High-end automotive infotainment systems 

integrating data communications, location 

services, and video entertainment require highperformance 

programmable processing that 

can be optimally delivered by integrating FPGA 

coprocessors into mainstream automotive telematic system 

architectures. This article describes the requirements for an automotive 

entertainment system, discusses a mainstream system architecture, and will identify how 

an FPGA coprocessor can be integrated into both the hardware and software architecture to address 

high-performance processing requirements, flexibility requirements, and cost reduction objectives. 

Entertainment electronics are becoming a primary source 

of differentiation between luxury automobiles, thus 

driving a rapid evolution of features and capabilities 

that challenge designers with performance, cost, and 

flexibility trade-offs. High-end applications can include satellite 

radio, rear-seat entertainment, navigation, all types of audio 

playback, voice synthesis and recognition, as well as other 

new applications. 

The core technology drivers for automotive entertainment 

systems have significant differences from historical automotive 

applications. Unlike any other area of automotive electronics, these 

entertainment applications are highly visible and have rapidly 

changing requirements. In addition, out-of-date entertainment 

systems will be a major weakness in selling new cars and may 

become a key factor in resale value and the cost of leasing. 

Traditional automotive electronics are driven by mass 

standardization with long product life cycles, low cost, and 

extended temperature requirements. These requirements do 

not go away for vehicular based entertainment systems. Instead 

of long product life cycles occurring with minimal evolution, 

however, designers are challenged to design systems that support 

long life cycles that will experience rapid evolutions in system 

capabilities. These new requirements demand flexibility and 

performance not available in traditional Application Specific 

Standard Product (ASSP)-based system architectures. 

The baseline architectures for in-vehicle entertainment systems are 

now designed to be capable of supporting a flat screen monitor 

with a graphical human interface capable of displaying dynamic 

maps and automobile information. These architectures are 

centered around a highly standardized micro-controller, a variety 

of standard interfaces, and simple hardware acceleration to support 

the required low-end graphics processing. This architecture 

addresses the requirements for the mid-range entertainment 

systems of the automotive market at a very low cost, while 

enabling expansion to high-end applications for the top-tier luxury 

automotive market. The top-tier applications include video imaging 

and communications. The various standards supporting these 

applications (Video: MPEG2, MPEG4, H.264; Communications: 

GSM/EDGE, WCDMA, 1xEVDO, satellite radio, satellite TV, 

digital video broadcast, Wi-Fi) are based on multiple, evolving 

signal processing algorithms. These algorithms demand extremely 


high programmable processing performance. There are three 

semiconductor technologies that can be utilized to implement 

these highly complex algorithms. 

These three technologies include programmable Digital Signal 

Processors (DSPs), Application Specific Standard Products 

(ASSPs), and Field Programmable Gate Arrays (FPGAs). The 

DSP provides a high-performance programmable processor 

specifically designed for signal processing applications. DSP 

processors are extremely flexible, low-power, and cost efficient, 

but lack hardware acceleration capabilities and do not provide the 

necessary compute power for today’s leading image processing 

and wireless communications algorithms. ASSPs, which often 

include DSP processors, provide optimized solutions for single 

video or communications standards, but cannot be programmed 

to adapt to different standards. FPGAs, on the other hand, provide 

both very high performance processing and are programmable 

for adaptation to many applications and standards. Unlike the 

other two technologies, FPGAs deliver both the flexibility and 

performance required to cover all the potential algorithms. 

The baseline telematics architecture previously described requires 

additional processing chips to handle the high-end applications. 

These additional chips, generally ASICs and ASSPs integrate with 

the processor through a memory or video processing bus and thus 

become application-specific coprocessors. One of the powerful 

ways to use an FPGA is as a replacement for this applicationspecific 

hardware. Coupling the FPGA to a processor is known 

as FPGA coprocessing. Using the FPGA in this way enables new 

application-specific accelerators to be downloaded on demand 

into the FPGA to assist in any high performance application. 

This concept is being widely used for advanced military multistandard 

radios and is called Software Defined Radio (SDR). In 

SDR, a single radio unit can automatically adapt to different radio 

standards with a push of a button. This not only helps future-proof 

equipment, it also reduces the number of custom processors that 

sit idly by while a different task is being performed. These soft 

radio techniques can be utilized in the automotive market for both 

communications and video applications. 

The flexibility an FPGA provides for video processing and wireless 

connectivity can also save costs and increase system value. Today’s 

baseline architectures require add-on ASSPs for each new video 

codec or wireless standard supported. Substituting one FPGA 

to replace multiple ASSPs reduces the number of architecture 

permutations that must be deployed and maintained over the life of 

a vehicle. Extending the baseline in-vehicle entertainment system 

architecture to include an FPGA enables a single high-end platform 

that can be programmed across a wide range of video and wireless 

standards and features. This approach fits in well with advanced 

automotive entertainment system architectures. 

An example of a leading-edge automotive entertainment system 

architecture 1 has been published by Delphi Delco Electronics 

Systems corporation. The platform leverages a standard SH-4 

microprocessor and a companion ASIC, the Hitachi HD64404 

Amanda peripheral, to deliver the baseline functionality required 

for the middle 80 percent of the automotive market. This system 

provides a common control processor with a standard API layer that 

enables the abstraction of hardware peripherals and coprocessors. 

The companion ASIC provides a baseline set of peripherals and an 

integrated graphics processor. The graphics processor is capable 

of supporting interactive graphics and scaling functions, but does 

not provide video codec functionality or other DSP applications. 

This system provides baseline functionality for all entertainment 

applications, but still requires additional ASICs or ASSPs for 

video codec and wireless communications functionality. 



The Amanda companion chip in the Delphi architecture (see 

Figures 1, 2) uses two processing buses, the Pixel Bus for 

high-performance dataflows such as video processing, and the 

Register Bus for control applications. Each bus connects to the 

SH-4 MPX bus and an external memory interface. This combination 

of buses and memory interfaces provide the perfect interface 

to support a flexible video codec and wireless communications 

platform based on an FPGA coprocessor. 

Figure 1 

Figure 2 

FPGA coprocessing enables tight integration with a control 

or DSP processor to offload major algorithmic processing, while 

keeping a standard programming interface resident on the control 

processor. The integration works best when the primary dataflow 

of an algorithm stays on the FPGA or related memories. The 

algorithm is controlled by a much slower control signal from the 

control processor. 

This type of architecture can be applied to wireless communications 

to support the digital processing in GSM/EDGE, WCDMA, 

1xEVDO, and the different permutations of 802.11 with a single 

FPGA. The alternative is a unique hardware design for each standard 

thus multiplying costs and board area. 

In addition, FPGA coprocessing, applied to image processing, 

can enable support of multiple video codecs including MPEG2, 

MPEG4, and H.264 with a single FPGA. In fact, it can utilize the 

same FPGA as that used for the wireless communications. 

An FPGA coprocessor integrates with a processor based system 

through Direct Memory Access (DMA)-based interfaces. The 

software layer on the embedded processor includes an application 

interface for each coprocessor that includes 

an initialization routine that loads 

the FPGA with the appropriate application 

coprocessor. Once the application 

is initialized, software calls to the coprocessor 

control parameters, timing, 

and the flow of data into and out of the 

coprocessor. Depending on the standard 

being implemented, there may be a high 

level of interaction between the FPGA 

coprocessor and the control processor, or 

the FPGA coprocessor may be completely 

self-contained. In such cases the control 

processor simply loads the algorithm and 

gets out of the way. 

Each program image loaded onto the 

FPGA needs to integrate into the 

surrounding system. Using an FPGA 

for programmable functions requires a 

well defined system interface that each 

FPGA-based accelerator relies on for 

communication. In general, the FPGA 

will have multiple interfaces that connect 

to a control processor, memory, and 

other external peripherals or connectors. 

The FPGA may also contain several 

coprocessors simultaneously that all share 

a single interface to the control processor. 

Each peripheral or coprocessor can have 

additional buses for high-performance 

dataflow processing. 

In the case of a video codec, there will be 

an input source and an output destination. 

The video input interface in the Delphi 

system architecture is part of the Amanda 

companion ASIC and utilizes the ITU-R 

BT.656 interface for streaming video. This 

can be post-scaled and manipulated by 

the ASIC to fit a variety of different display 

panels. The FPGA will likely need to 

connect to two other buses, the memory 

bus on the companion chip and the 

PCI/MPX bus of the host control processor, 

which also connects to the 

companion chip. Through these three connections, the FPGA 

can support video and communications applications with 

high-bandwidth communication through the memory interface 

and control communication through the PCI/MPX bus. 

The FPGA provides a reprogrammable platform for applicationspecific 

processing architectures that complements the host 

processor. The FPGA program, however, is fundamentally 

different from that of a standard processor architecture. An FPGA 

provides a high-performance hardware fabric with programmable 

logic elements, routing, DSP processing blocks, memory, and 

I/O. The system architecture of an FPGA is executed in much the 

same manner as that for a standard ASSP where the dedicated 


functionality of the system is designed and implemented through 

hardware and software development tools. The output of these 

tools is a binary image that when loaded onto the FPGA, defines 

the functionality of all the programmable logic elements, routing, 

DSP processing blocks, etc. This binary image can be loaded by 

the host processor during the run-time of the system. A variety 

of different program images can be created to support MPEG2, 

MPEG4, H.264, GSM/EDGE, WCDMA, 1xEVDO, GPS, 3D 

graphics accelerators, or any other algorithms that may go into 

an automotive telematics system. Depending on the user’s menu 

selection in the entertainment system, the specific application 

program will be downloaded by the host processor into the 

FPGA and will then be under the host processor control. 

“Using an FPGA for 

programmable functions requires 

a well defined system interface 

that each FPGA-based accelerator 

relies on for communication.” 

Controlling a dedicated hardware accelerator from a host processor 

is typically done through a register and memory interface with 

each register controlling some aspect of the hardware accelerator 

operation. This is true for the default companion chip in the 

Delphi system and will be true for each coprocessor architecture 

downloaded into a companion FPGA. Using the FPGA, it is a 

straightforward task to standardize on a register and memory 

interface to control any coprocessor that is programmed into the 

device. This standard interface may define how to read and write 

data to the coprocessor, how to start and stop it, how to reset it, 

and include a set of registers for controlling application specific 

operation. All of these registers will be part of a linear address 

map within the FPGA so that it is easy for the software physical 

device drivers to access the registers. 

The software physical device drivers for a coprocessor provide a 

higher level of abstraction than the register interface implemented 

in the hardware. The software drivers provide a mapping from 

algorithmic parameters of the system to the control registers so 

that the application software is easier to write and maintain. The 

higher layer model device drivers remain 

portable across changes in implementation 

of the underlying hardware. The software 

architecture within the Delphi system 

provides a strong framework for supporting 

algorithm implementation either in 

software or hardware coprocessors, since 

it provides a couple of layers of abstraction 

that separates the algorithmic implementation 

from its physical implementation in 

hardware or software. FPGA coprocessors 

fit very nicely into the Delphi software 

and hardware architecture. 

high-performance processing. The key challenges in implementing 

FPGA coprocessors include designing the various hardware 

accelerators for an FPGA, integrating the hardware accelerator 

with the external control processor, and creating a software 

layer that controls the hardware accelerator. The hardware 

accelerators required include mainstream algorithms for video 

and communications. These applications have a broad market, 

which has evolved to support specialty companies that focus on 

designing standard specific Intellectual Property (IP) hardware 

accelerators. These companies provide off-the-shelf algorithms 

that can be directly implemented in leading, low-cost FPGAs. It 

is possible to buy commercially available IP blocks for MPEG2, 

MPEG4, H.264, Wi-Fi, and many other video and communications 

standards. An example MPEG4 decoder IP block diagram from 

Amphion Corporation is shown in Figure 3 that is available for 

ASIC or FPGA applications. 

The next step is integrating the hardware accelerator in the FPGA 

with the external busses for control, data input, and data output. 

A new category of development tool is available that enable 

designers to easily perform this integration. Using SOPC Builder, 

the system integration tool from Altera, designers select the IP 

blocks from a list of available IP. Upon selection, a parameterized 

menu appears showing different architectural options the user 

has control over prior to implementation. Once the parameters 

are set, the block is included in a list of other peripherals and 

processors being integrated by the engineer. Once each individual 

IP block has been selected and parameterized, they need to be 

integrated into an processing architecture. 

SOPC Builder enables the designer to define a high-performance 

switch architecture that interconnects the various hardware 

accelerators and peripherals to the external host processor. This 

switch architecture is defined through mouse clicking on an 

intuitive matrix representation of the block interconnection. Once 

the architecture is defined, SOPC Builder automatically assembles 

the various IPs together and generates a Hardware Description 

Language description for automatic synthesis to the final FPGA 

program. This final program is then downloaded onto the FPGA 

at run-time to implement a specific algorithm coprocessor. 

After hardware integration is complete, a software physical device 

driver is required that separates high-level software control from 

the detailed register and memory map architecture used to control 

the hardware accelerator. The register and memory fields required 

to control a hardware accelerator are standard components of the 

parameterized IP blocks. The integration of multiple peripherals 

FPGAs are being designed into many 

systems whose basic architecture is similar 

to that of the Delphi system architecture. 

These systems include one or more 

control or DSP processors and utilize 

the FPGA to accelerate tasks that require Figure 3 


and accelerators, 

however, requires 

a register and memory map of all 

programmable features implemented onto the 

FPGA. SOPC Builder automatically creates this register and 

memory map while it assembles the IP into the user defined switch 

architecture. 

Each IP block contains a predefined set of software physical 

device drivers for use on an external host processor to control 

the IP block. SOPC Builder automatically assembles the various 

software physical device drivers and automatically associates 

each driver with the appropriate register and memory map 

associated with the IP block it controls. In this way, SOPC Builder 

automatically creates and integrates the hardware and software 

architecture of the FPGA coprocessor and the control 

processor. SOPC Builder was developed to address the rapidly 

evolving capabilities of FPGAs and their increasing ability to 

absorb complex system implementation. 

Since their introduction 20 years ago, programmable logic 

devices have been rapidly evolving from low-level glue logic to 

the lowest cost, highest performance programmable processing. 

Two key factors have driven this advance in FPGA performance 

and reduction in cost: FPGA architecture evolution and the 

ways in which FPGAs leverage semiconductor technology. The 

architecture of FPGAs provide arrays of programmable logic 

elements that are grouped together with programmable routing. 

In early low-density FPGAs, this enabled the interconnection of 

simple processing elements. As the density of FPGAs increased, 

the arrayed architecture enabled massive parallel processing. 

FPGA architectures have evolved to include memory blocks, 

DSP blocks, and programmable I/O throughout the processing 

array. The resulting processing architectures can easily meet the 

performance requirements of automotive telematics. 

The other key driver of FPGA evolution is process technology 

and its impact on performance and cost. FPGAs utilize the latest 

generations of process technology to increase density, performance, 

and lower costs. At the same time, FPGAs are used to accelerate 

the development of process technologies. FPGAs are valuable in 

the development of semiconductor process technology because 

they utilize a regular structure that goes to high volume production 

early in its lifecycle. The regular structure of FPGAs enables the 

collection of good statistics for measuring production defects, 

which is critical for fine-tuning process technology to achieve 

ultra-high manufacturing yields. The symbiotic relationship 

between FPGAs and process technology has enabled a huge 

increase in FPGA density and a related decrease in component 

price. As a result, today’s low-cost FPGAs such as Altera’s Cyclone 

series of devices are cost competitive with dedicated ASICs 

and ASSPs. 


Automotive entertainment systems are rapidly evolving, both 

technologically and as a point of differentiation among automobiles. 

Leading-edge system architectures are designed to serve 

the majority of the mainstream automotive market, while enabling 

high-end differentiation through additional supporting 

ASSPs and software. FPGAs provide a complementary 

high-performance and flexible coprocessing platform that 

consolidates the functionality of many companion ASSPs into 

one reprogrammable platform. FPGA coprocessors fit nicely 

into mainstream automotive entertainment architectures like the 

Delphi architecture described. By using FPGA coprocessors as 

part of high-end automotive entertainment system architectures, 

automobile companies can provide a multitude of high-end video 


and communication features through software programming that 

cannot be enabled by ASSPs alone. Using FPGAs to facilitate highend 

flexible automotive entertainment architectures can enable the 

ability to upsell new features at the time of the vehicle sale and 

throughout the lifetime of the vehicle. The ability to enhance an 

automotive entertainment system, at the time of sale and thereafter, 

can increase the value of the car when it is initially sold, as well as 

later, when the resale value of a previously leased vehicle remains 

an important component in auto manufacturer’s profitability. 

Reference: 

1 “Mobile Multi Media Open Computing Platform” by Phil Motz, Arch Wills, Jill 

Hersberger, Mike Laur, Delphi Delco Electronics Systems Corp. – SAE 2001 World 

Congress March 5-8, 2001 

Paul Ekas joined Altera in August 2002 

as the Senior DSP Marketing Manager 

in charge of the company’s Code:DSP 

corporate marketing initiative. Ekas has 

more than 17 years of business experience in 

electronic design automation and complex 

semiconductor systems. He holds a BSEE and 

MSEE from the University of Washington. 

For further information, contact Paul at: 

Altera Corporation 

101 Innovation Drive • San Jose, CA 95134 

Tel: 408-544-8388 • Fax: 408-544-7280 

E-mail: pekas@altera.com • Website: www.altera.com 





By Kevin C. Kreitzer, Alan Kasten 

New 

fingerprint 

subsystem 

brings 

biometrics 

to the 

mass market 

Fingerprint sensor 

provider AuthenTec, 

Inc. needed a more powerful 

microprocessor for their 

next generation Embedded 

Developers Kit (EDK) – one 

that could perform ever 

more complicated matching 

algorithms in less than half 

a second, yet was cheap 

enough for use in consumer 

products. Surprisingly, 

the solution came from a 

traditional DSP company. 

Introduction 

The AuthenTec AFS8600 EDK is a reference design that customers may embed directly 

into their products, or customize to their needs. As the latest in a series of EDKs for 

various AuthenTec sensor families, it offers fingerprint biometric solutions for around 

$35, helping to fuel the 60% growth through 2005 predicted by the International 

Biometric Group. 

Sensing the fingerprint 

There are two parts to fingerprint authentication – sensing and match detection. How do 

you sense a fingerprint This reference design uses the AuthenTec FingerLoc ® AFS8600, 

with its patented TruePrint ® technology. Competing solutions are typically optical or 

capacitance-based. Because optical sensors can only see the surface of the skin, their 

images are degraded if the fingerprint is contaminated with dirt or oil. DC Capacitive 

sensors are also surface-based imagers. They detect the fingerprint ridges and valleys, and 

their performance degrades if the finger surface is worn or dry. TruePrint avoids these 

issues by using RF technology to measure below the surface of the skin to the live layer. 

Match accuracies are measured in terms of the False Accept Rate (FAR – the probability 

of matching a non-matching fingerprint), and the False Reject Rate (FRR – the probability 

of incorrectly rejecting a matching finger). The AFS 8600 achieves an industry leading 

FAR < 1/10000, and FRR < 1/1000. 

Matching the fingerprint 

Sensing the fingerprint is only half the battle. A processor must then take the raw sensor 

data, reduce it to a manageable data base, and perform match validation. AuthenTec has 

developed proprietary matching library software to perform this function. The software 

requirements were C source code, to be able to perform a one-to-one fingerprint match in 

less than 500 ms, and to achieve match scores within acceptable tolerances of the library 

reference model. As the matching algorithms become more sophisticated, more processor 

muscle is required to obtain the 500 ms match time. In addition, AuthenTec wanted to 

reduce the cost in order to make consumer grade products viable. 


Building the product 

The EDK hardware consists of the sensor, a processor, a boot Flash, and an SDRAM. The 

sensor can be connected to the processor with any number of serial interfaces. In this case, 

a UART was chosen in order to leave the SPI port open for host communications. A number 

of additional interface configurations are possible using an optional connector interface. 

The AFS8600 EDK block diagram is shown in Figure 3. 

The answer 

The answer came from an unlikely source. 

Analog Devices, Inc., which is traditionally 

known for its DSPs, has introduced the 

ADSP-BF531 as a new low cost member 

of its Blackfin family. The Blackfin 

performs microcontroller functions with 

dexterity comparable to its DSP functions. 

In this application, the ADSP-BF531 was 

essentially an inexpensive 800 MIPS 

microprocessor. The sensor side of the 

AFS8600 is shown in Figure 1, and the 

processor side is shown in Figure 2. 

Figure 3 

Figure 1 

The ADSP-BF531 has 32 Kbytes of internal code SRAM, and 20 Kbytes of internal data 

SRAM. If necessary, 16 Kbytes of internal code SRAM, and 16 Kbytes of internal data 

SRAM may be configured as cache instead. Because of the large size of the fingerprint 

matching library, nearly all of the code and data went into external SDRAM. The caches 

would have to perform extremely well in this circumstance, and they did not disappoint. 

Table 1 lists the average times for a one-to-one match. Note that the times are well below 

the 500 ms requirement. It should be noted that the core clock could be reduced to half of 

its peak rate, and still achieve the required match time. Because the Blackfin can lower its 

core voltage when the clock rate is reduced, this can result in a significant reduction to the 

Blackfin’s already low active power consumption. 

Core Clock Bus Clock Average Match Time 

396 MHz 132 MHz 167 ms 

198 MHz 132 MHz 336 ms 

Figure 2 

Table 1 

Validation 

To validate the match time results, a test was run on the Blackfin to compare its match 

scores to those obtained with the same matcher library running on a PC. This was 

accomplished with canned fingerprint images so that the enroll and verify images are 

identical. If the match scores computed on the embedded platform are identical to those 

on the PC, then there is confidence that there are no compiler bugs or idiosyncrasies in 

the embedded platform that would cause the matcher to malfunction or give incorrect 

results. The test was performed with two sets of five different canned images. The match 

scores from the Blackfin were identical bit-for-bit to those from the PC – a rare occurrence 

for an embedded processor. 


“A number of 

additional interface 

configurations are 

possible using an 

optional connector 

interface.” 

years at Harris Semiconductor in various roles, including device engineering, process 

engineering, yield enhancement, engineering management, and marketing. Kasten holds 

a BSEE degree from the University of California, has three patents to his credit, and is 

fluent in several Asian languages. 

For further information, contact Alan at: 

AuthenTec, Inc. 

709 S. Harbor City Blvd. • Melbourne, FL 32901 

Tel: 321-308-1344 • Fax: 321-308-1430 

E-mail: al.kasten@authentec.com • Website: www.authentec.com 

FingerLoc and TruePrint are registered trademarks of AuthenTec, Inc. Blackfin is a registered trademark 

of Analog Devices, Inc. Other brand or product names are registered trademarks or trademarks of the 

respective holders. 

Conclusion 

The excellent match accuracy of the 

AFS8600 combined with the 800 MIPS 

performance and low-cost of the ADSP- 

BF531 have made fingerprint biometrics 

viable for consumer market adoption. 

Kevin C. Kreitzer is a Senior Field 

Applications Engineer with Analog 

Devices, Inc. in St. Petersburg, Florida 

where he supports DSP and embedded 

processor products. 

He has Bachelor of 

Science and Master 

of Engineering 

degrees in Electrical 

Engineering from the 

University of Florida, 

specializing in DSP 

and Communications. 

Prior to joining 

Analog Devices in 2000, Kreitzer spent 11 

years designing Software-Defined Radios 

with various defense contractors. 

For further information, contact Kevin at: 

Analog Devices, Inc. 

5172 Venetian Blvd. N.E. 

St. Petersburg, FL 33703 

Tel: 727-521-6614 

E-mail: kevin.kreitzer@analog.com 

Website: www.analog.com 

Alan Kasten is an Applications Engineer 

with AuthenTec, Inc. in Melbourne, 

Florida. He helped 

to found AuthenTec 

when it was first 

spun-off from Harris 

Semiconductor 

in 1998, and has 

been with the Company 

ever since. 

Kasten worked 

for more than 20 



Surveillance and control systems for the modern military 

The modern military is becoming more networked. This 

facilitates all forms of communications and can also enhance 

the safety of modern military tactical training programs. 

This article will discuss how Performance Technologies’ MPS800 

Communications Server and Radar Receiver Protocol are being 

used in a Wide Area Network (WAN) designed by Digicomp 

Research for the United States Joint Forces Command’s Joint 

Combat Identification Exercise (JCIDEX). 

JCIDEX 

JCIDEX conducts large-scale tactical training exercises to evaluate 

and assess integration and interoperability of systems to improve 

tactics, techniques, and procedures across all combat mission 

areas. During training exercises, an evaluation or warning area is 

established and monitored to ensure that the military participants 

stay within the designated warning area established for the exercise. 

Additionally, the warning area must also be monitored to ensure 

civilian aircraft do not enter the area. 

By Steve Wigent 

Aircraft radar management 

Digicomp has designed a surveillance and control system that 

utilizes a WAN to manage radar data from multiple sources so that 

aircraft can be tracked, displayed, and monitored. The system is 

the first of its kind used by JCIDEX to manage evaluation airspace. 

The Performance Technologies Radar Protocol and the MPS800 

Communications Server are used to ensure the awareness of 

military participants, and any civilian traffic that may mistakenly 

enter the field of play. During one JCIDEX exercise, the Digicomp 

system monitored more than 350 air events flown within 15,000 

square miles of airspace over a period of 60 hours. 

The Radar Receiver Protocol, running entirely on the MPS800, 

can be configured independently for each of the eight serial ports 

the MPS800 offers and supports a number of different radar 

formats, including CD-2, TPS-43, ASTERIX (RAMP), and 

Thompson-CSF. Performance Technologies provides the ability 

to receive and transmit these formats from remote sites over 

significant distances. 

The network incorporates a number of MPS800s that are connected 

via Ethernet to a central location. Radar data is received on 

a MPS800’s serial line, and the appropriate radar protocol strips 

out the radar particulars (e.g. headers, idle messages), and then 

retransmits the payload over Ethernet to a central server on the 

network for further processing and eventual display/monitoring 

on a radar operator’s console. A example of this type of WAN is 

shown in Figure 1. 

The MPS800 can connect up to eight serial lines of data that can 

carry a number of different protocols (HDLC, Radar, X.25, Frame 

Relay, etc.). Each serial line can be accessed simultaneously by 

multiple clients. The MPS800 is a WAN/LAN data communication 

server that attaches to LANs to provide wide-area connectivity. 

Figure 1 

The MPS800 also provides one 10/100 Ethernet port for connecting 

the LAN to the WAN. This capability makes the MPS800 

ideal for applications that require an intelligent WAN/LAN 

bridge, WAN/LAN gateway device, or a remote WAN connectivity 

server. Through TCP/IP connections and Performance 

Technologies’ MPS-API, virtually all computers and workstations 

on the LAN can access information from this server. 

In the Digicomp system, the MPS800 is being used as a WAN/LAN 

bridge, and the radar protocol is being used to carry the data. This 

surveillance and control system is one example of how the modern 

military is using Commercial Off The Shelf (COTS) products to 

become networked. 

Steve Wigent has served as Product Manager, 

Network Access Products for Performance 

Technologies for the past five years. Prior to 

joining Performance Technologies, he held 

various product management and marketing 

positions. Steve holds a Bachelor of Science 

in Electricity and Electronics Technology with 

a concentrated study in Telecommunications 

and Micro Computer Architecture from 

Central Missouri State University. 

For further information, contact Steve at: 

Performance Technologies 

205 Indigo Creek Drive • Rochester, NY 14626 

Tel: 585-256-0200 • Fax: 585-256-0791 

E-mail: scw@pt.com • Website: www.pt.com 




Blades – Servers – VoIP 

By Chad Lumsden 

Blades 

Company Name/Model No. Description Web Address 

ACT/Technico 

RaidStor 

Adlink Technology 

cPCIS-3100BLS 

Adtron 

Apcon 

IC6C 

IC6HB 

www.acttechnico.com 

A 6U, single-slot, CompactPCI, network-attached storage blade • High-availability and hot-swap capable • PICMG 2.16 packet switched 

backplane compatible • 120 Gbyte per blade capacity • Dual 10/100Base-Tx Ethernet ports • Automatic failover • Compatible with fabric 

switches • RAID 0, 1 • Supports NFS, web server, bootp, and FTP 

www.adlinktech.com 

A CompactPCI blade server • Standard 6U CompactPCI form factor • 9-slot backplane for standlone system board or compute blade 

• Built-in 400W AC-input, dual redundant power supply • One 3.5" and three 5.25" drive bays • Alarm module for monitoring chassis 

temperature and fan status • Switch, drive bays, and redundant power supply are protected by door • Redundant cooling architecture 

• Designed for NEBS Level 3 installation 

www.adtron.com 

The Adtron IC6C is a self-contained storage blade on a single-slot, 6U, CompactPCI plug-in card • PIO mode 4, Multiword DMA mode 

2, Ultra DMA mode 2 compatible • Flexible fixed/removable configurations • No additional software drivers are required for operation 

as an IDE boot and data storage system • HDD storage with one or two hard disk drives • Fixed/removable storage with one hard disk 

drive and one removable device • Removable devices may be either a CD-ROM, CD-RW, or DVD/CD+/-RW unit for software loads and 

data backups • Configurations for either PCI or off-board connection • Rear transition boards available for IDE, SCSI-3, and USB 2.0 

A 6U, CompactPCI storage blade • PIO mode 4, Multiword DMA, and Ultra DMA compatible • Provides up to 160 Gbytes of fixed hard 

disk storage or up to 8 Gbytes of solid-state Flash storage • IPMI support • Rear Transition Boards available for IDE and USB 2.0 

www.apcon.com 

A modular, single-blade, physical layer switch • Supports APCON’s entire technology range, including 1-, 2-, and 10-Gbit/sec Fibre 

Intellapatch 16 Channel, 10/100/1000Base-T and SONET OC-3, OC-12, and OC-48 • Uses either SFP or XFP transceivers • Part of the APCON family of 

physical layer switches that are available in 16- and 32-port fixed models, and 64- and 144-port multi-blade switches 

Artesyn Communication 

www.artesyncp.com 

Katana 3750 

Katana 750i 

Katana750v 

SpiderWareSG 

SpiderWareSS7 

A CompactPCI real-time processing blade • Three IBM PowerPC PPC750FX processor complexes running at 800 MHz • Fully compliant 

with PICMG 2.16 PSB specification • Managed Gigabit Ethernet switch • System management bus (PICMG 2.9) with IPMI controller 

• Up to 512 Mbytes DDR ECC SDRAM in SODIMM package per processor • Up to 64 Mbytes linear Flash per processor • 10/100Base-T 

with front access • Console serial I/O, EEPROM, and real-time clock per processor • VxWorks and Linux support 

A real-time processing blade in a standard, single-slot CompactPCI packet switched backplane (cPSB) form factor • PowerPC 750FX 

processor at 800 MHz • PICMG 2.16, dual 1000Base-T cPSB node • Dual PMC expansion sites • System management bus (PICMG 2.9) 

with IPMI peripheral controller • Up to 1 Gbyte of DDR SDRAM with ECC in SODIMM package • Up to 128 Mbytes of linear Flash • 

Real-time clock with supercap backup • 10/100Base-T with front access • 64 Kbytes serial EEPROM for nonvolatile storage • VxWorks 

board support package • TimeSys real-time Linux SDK 

A CompactPCI Packet Switching Backplane (cPSB) blade • IBM PowerPC 750FX processor at 800 MHz • Marvell MV64360 system 

controller • Up to 1 GB of SDRAM and 128 MB of Flash memory • Two Gigabit Ethernet channels and one 10/100Base-T channel • 

Dual PTMC sites support 32-bit PCI data transfers at 33 or 66 MHz and are equipped with dedicated CTBus and RMII interfaces that 

facilitate collaborative processing and provide direct access to external TDM and packet data sources • Fully compliant with PICMG 

2.16 • Supports PICMG 2.9 system management bus • Available with turnkey software for a variety of signaling, network interface, 

gateway, and network processing applications • Supports TimeSys real-time Linux, VxWorks 5.5/Tornado 2.2, a reference kernel port 

for GPL Linux, and a PowerPC boot loader (PPCBoot) with power-on self test • Complies with all major safety, EMC, and environmental 

standards 

An off-the-shelf, plug-and-play SIGTRAN blade for SS7 signaling over IP • Supports an M2UA signaling gateway (SG) • Optional 

off-the-shelf Media Gateway Controller (MGC) signalling functionality • Eight SS7-M2UA signalling channels per blade • Standard 

higher level APIs • Professional services available • A selection of SS7 upper layer country variants are available off-the-shelf 

A signaling blade for SS7 applications • 64 to 128 SS7 channels per blade • Standardized STREAMS-based API • Eight or 16 E1/T1 

spans per blade • MTP1 and MTP2 SS7 layers • Optional MTP3 layer support on host processor board • Option for blade-based host 

processor with Linux support • STREAMS-based interlayer protocol and application communications • 10/100Base-Tx Ethernet 

• Available in cPSB, CompactPCI, or PMC form factors 


Blades 


Diversified Technology 

cPB-4305 

www.dtims.com 

A PICMG 2.16-compliant CompactPCI PSB compute blade • Optimized for use as a system master or peripheral processor in Ethernet 

PSB CompactPCI platforms • Uses a low power, 1.2 GHz Mobile Intel Pentium 4 processor-M with 512 Kbytes L2 cache • Intel 845E 

chipset with 400 MHz front-side bus • Up to 2 Gbytes ECC DDR200/266 SDRAM • Two 10/100/1000Base-T Ethernet auto-negotiating 

controllers onboard • Ultra DMA/100 IDE 2.5" hard drive or 32-bit/33 MHz PMC site • PS/2 keyboard and mouse interfaces • USB and 

serial ports • Floppy interface • SVGA controller • Forsakes a CompactPCI bridge to reduce cost 

cPB-4321 

cPB-4610 

A PICMG 2.16 compliant CompactPCI processor blade • Low power Intel 1 GHz Pentium III processor with 256 Kbytes L2 cache • Intel 

440GX chipset, with 100 MHz front side bus • 512 Mbytes or 1 Gbyte ECC SDRAM • Two 10/100 Base-T Ethernet controllers • Ultra 

DMA/33 IDE hard drive • 32-bit/33-MHz PMC site • PS/2 keyboard and mouse interfaces • USB and serial ports • Floppy interface 

• SVGA CRT controller • Optional CD-ROM drive mezzanine card • Optional IDE-compatible CompactFlash carrier card 

A PICMG 2.16-compliant, Pentium M-based processor blade • Intel Pentium M processor with 1-Mbyte L2 cache • Intel 855PM 

chipset with 400-MHz FSB • 256 Mbytes to 1 Gbyte of ECC DDR SDRAM • Onboard SCSI controller • 10/100Base-T Ethernet interface 

• Onboard mini IDE Flash drive and two 32-bit/33-MHz PMC sites; one PIM connection • 6U x 4HP, system processor • PICMG 2.16 and 

2.1 R2.0 compliant 

cPC-4325 

Extreme Engineering 

XCalibur1000 

Interactive Circuits and Systems Ltd. 

PCI Software Radio 

Memory Blade 

A system/peripheral processor blade • One or two Intel Pentium III processors at 933 MHz with 512 Kbytes L2 cache • ServerWorks 

LE-T chipset with 133 MHz front-side bus • Up to 1 Gbyte ECC SDRAM • PCI video with 2 Mbytes SDRAM • Two Gigabit and one Fast 

Ethernet interfaces • Optional onboard 2.5" Ultra DMA/33 EIDE drive or CompactFlash drive carrier • 6U x 4HP, operates as system or 

peripheral processor • Optional mezzanine I/O expansion card with dual PMC and dual Fibre Channel interfaces and backplane bridge 

• PICMG 2.16, 2.1 R2.0, and 2.9 R1.0 compliant 

www.xes-inc.com 

A 6U CompactPCI blade • Single or dual IBM 750FX processors • Supports Broadcom’s Super E-Commerce Processor, (BCM5821) 

with encryption performance of 4000 1024-bit RSA transactions per second and 3000 IKE negotiations per second • 300-Mbit/sec bulk 

SSL encryption • 470Mbit/sec IPsec performance • Front panel serial ports and dual Gigabit Ethernet ports • Dual PCI-X PMC module 

sites • PrPMCs can be added • Runs in system or non-system mode • Dual SODIMM SDRAM sockets support 128 Mbytes to 2 Gbytes 

of DDR memory at 266 MHz • VxWorks software support 

www.ics-ltd.com 

A software radio blade • ICS-554, ICS-564, or ICS-572 integrated with up to a 4-Gbyte memory PMC module for onboard data storage 

• Over 300 Mbytes/sec sustained data storage rate • Single-slot solution • 64-bit, 66-MHz PCI host interface on the PMC modules 

• Software support for Windows, Solaris, and Linux 


PowerPC DSP Blade 


TI C64 DSP Blade 

A software radio blade • ICS-554, ICS-564, or ICS-572 integrated with quad 7410 PowerPC DSP • Up to two PMC modules per card 

• Single-slot solution • Large onboard memory for each DSP • Direct data transfer to VME P2 user I/O from each PMC site • 64-bit, 

66 MHz PCI host interface on the PMC modules • Software support for VxWorks, Linux, and Solaris • Custom coding of baseband 

processing 

A software radio blade • ICS-554, ICS-564, or ICS-572 integrated with quad C64 DSP module • Single-slot solution • Large onboard 

memory • Direct data transfer to processor via P4 user I/O • 64-bit, 66-MHz PCI host interface on the PMC modules • Software support 

for Windows, Linux, and Solaris • Custom coding of baseband processing in Xilinx FPGA 


XILINX FPGA Blade 

Interphase 

iNAV Series 

Motorola Computer Group 

CPIP5365 

NEXCOM International 

NexBlade HS318A 

A software radio blade • ICS-554, ICS-564, or ICS-572 integrated with Virtex-II based FPGA PMC module to supplement the onboard 

FPGA • Single-slot solution • Large onboard memory • Direct data transfer to processor via P4 user I/O • 64-bit, 66 MHz PCI host 

interface on the PMC modules • Software support for Windows, Linux, and Solaris • Custom coding of baseband processing in Xilinx 

FPGA 

www.interphase.com 

A series of communications blades that enable datacom gateway-on-a-slot functionality • Includes the iNAV 4000 and the iNAV 3000 

• The iNAV 4000 Network Processor Blade is an application-ready module with lower-layer network protocol stacks and a variety 

of the protocol interworking functions needed for broadband applications • Offers simultaneous IP routing, ATM switching, and 

interworking capabilities for an array of other network protocols including PPP, Packets over SONET (POS), Inverse Multiplexing for 

ATM (IMA), and more • Enables bridging of non-congruent networks • Powered by the Wintegra Winpath Packet Processor • The iNAV 

3000 Telecom Carrier Blade is equipped with dual PMC/PTMC expansion sites for maximized per-slot density • Includes an eight-port 

Fast Ethernet switch, a 2048 DS-0 TDM switch, and an H.110 interface 

mcg.motorola.com 

A peripheral slot controller • Can be customized with PMC modules to create an application-specific network blade • 850 MHz Pentium 

III BGA2 processor • Intel 440GX chipset • 100 MHz FSB frequency • Up to 1 Gbyte PC100 SDRAM • Dual 10/100 Mbit Ethernet • PICMG 

2.16 node-slot compliant • PICMG 2.9 support • Two USB channels • Two asynchronous serial ports • PS/2 keyboard/mouse • Real-time 

clock • Watchdog timer • One bi-directional IEEE-1284 compliant parallel port • Two 32/64-bit PMC expansion slots • Optional on-board 

2.5” EIDE hard drive • Software support includes Windows 2000, Linux, and VxWorks 

www.nexcom.com 

A series of blades • 3U, 19" rack chassis built with 9/10 or 18/20 blades • Pentium III Celeron or Pentium III; Socket 370 • Patent-pending 

intelligent CF-KVM switch for CD-ROM, FDD, keyboard, VGA, mouse • Four different blades for different applications: 1-slot blade 

for high density, 2-slot blade for I/O expandability, or mixed blades in the same chassis • Expandable to P4 blades • NEXCARE 

server management for health monitoring and remote control through serial port or LAN • 100Base-T LANx3 or 1000Base-Tx 

LANx2+100BaseTx-LANx1 per blade • CPU blades, power modules, cooling fans, and other modules are hot swappable 




CPC5702 

www.pt.com 

A PICMG 2.16-compliant single board computer • 1.6 GHz Pentium M processor • 400 MHz front-side bus • Single-slot, 6U CompactPCI 

board • Supports CompactPCI bus • PCI-to-PCI bridge interfaces to 32-bit or 64-bit CompactPCI bus operating at 33 or 66 MHz 

• Supports up to 2 Gbytes of DDR SDRAM with ECC at 3.2 Gbytes/sec peak bandwidth • 1 Mbyte firmware hub • Battery-backed 

real-time clock • Support for Performance Technologies’ NexusWare Linux-based development environment • Supports Windows 

2000/XP, Linux, and VxWorks operating systems • 0°C to 55°C operating temperature 

CPC7301 

SG5600 Signaling 

Gateway Blade 

ZT 5541 

ZT 4804 

ZT 4805 

ZT 4806 

ZT 4807e 

ZT 7102 

RadiSys Corp 

EPC-3311 

EPC-3412 

SBS Technologies 

HDTBlade 

VoABlade 

Voiceboard 

TDM to Packet 

Processor 

An intelligent CompactPCI shelf manager • Dedicated 600MHz processor manages all IPMI-based components • Fault-tolerant 

operation with active/standby dual-ISM redundancy • Star topology provides enhanced reliability • Synchronization between 

active/standby ISMs • Out-of-band management with dedicated Ethernet interface • Secure, fail-safe, and remote ISM firmware 

updates via network • Hot-swap support for field-replaceable components • Compatible with IPnexus packet-based, IPMI-compliant 

products • PICMG 2.1, PICMG 2.9, and PICMG 2.16 compatible • Manages via IPMI protocol • Multiple management standards: SNMP, 

IPMI, RMCP, Telnet, and SSH • Command Line Interface (CLI) integrates scripts with ISM • CLI access through SSH or Telnet • ISM 

API allows integration with third-party applications • Web-based interface 

A PICMG 2.16-compliant signaling gateway blade • Carrier-grade system-in-a-slot • Standards-based IETF SIGTRAN IP/SS7 protocols 

• Reliable and robust software and hardware • H.110 bus support 

A peripheral master CPU board with a 500 MHz Pentium III processor • Processor is a new high-density, ball grid array (BGA) device 

that combines high density and high performance in a low profile package for mobile and communications applications • 100 MHz 

system bus • Dual 10/100Base-T Ethernet network interfaces • Two PMC mezzanine sites • Hard drive • 512 Mbytes of memory • AGP 

Video • Operating systems support includes WindowsNT, Linux, and VxWorks 

A rear-panel transition board with alarm outputs • SMBus interface for alarm control • Six jumper-selectable relay outputs • Two 

jumper-selectable user inputs • Host Hot-Swap activation through bottom ejector latch circuitry • Internal floppy and IDE interfaces 

• Rear-panel switches for alarming, reset, and Hot-Swap initiate 

A rear-panel transition board • Internal CompactFlash-selectable as master or slave • Two internal IDE interfaces • External rear-panel 

interface connectors for the host CPU include two Ethernet connectors, two serial ports, keyboard/mouse, VGA, and USB • Reset 

request • Four-pin power connector for external media • Internal connectors for legacy interfaces (floppy, LPT) • Unique Serial ID 

provided by a DS2401 

A 6U, single-slot, rear-panel transition board • Designed to function in the 80mm rear-panel slot of a CompactPCI system that accepts 

6U boards • Rear-panel I/O interfaces • Internal floppy and IDE interfaces • Rear-panel reset switch • Rear-panel LEDs 

A rear-panel transition board • PICMG 2.16 compliant • Rear-panel interfaces include: Ethernet link and activity status LEDs, two serial 

ports, keyboard/mouse-combination PS/2 connector, VGA, and 2 USB connectors • Internal floppy and IDE interfaces • Rear-panel 

reset and NMI switches • Rear-panel LEDs (hot-swap and IDE activity) • Internal CompactFlash interface 

A chassis management module • High-density 3U CompactPCI form factor • Works within PICMG 2.16- and 2.9-compliant components 

• Utilizes IPMI in a star topology • Provides isolated I2C signals for each slot • 10/100Base-T Ethernet available at the front or rear 

panel • RS-232 (command-line interface) available at the front or rear panel • DB15 telco alarm interface at the front panel • Supports 

multiple management standards including SNMP, IPMI, and Telnet comprehensive monitoring for health, status, and component 

presence • Out-of-band, network-accessible management interface • XScale processor design • Hot-add/hot-swap support for all 

IPMI-based field-replaceable components • Individual slot power control for power-on sequencing supports 21 slots when integrated 

into a custom backplane or chassis 

www.radisys.com 

A high-throughput CPU blade • 1 GHz Pentium III processor • Gigabit Ethernet • 2 Gbytes SDRAM • Single-slot PICMG 2.16 processor 

• 133 MHz processor system bus • Two PMC sites • Two tri-mode (10/100/1000) Ethernet links • DMA access 

A PICMG 2.16-compliant CPU blade • Full PICMG 2.16 and 2.9 compliance • 1.2 GHz Mobile Intel Pentium 4 Processor-M • Intel 845E 

with ICH4 chipset • 400 MHz front-side bus • One 184-pin DIMM socket for up to 2 Gbytes of DDR200 ECC SDRAM • One 32-bit PMC 

expansion site • Optional IDE hard drive (occupies the PMC site) • Intelligent Platform Management Interface (IPMI) • Front-panel 

reset switch and COM1 port • 6U CompactPCI form factor 

www.sbs.com 

A high-density CompactPCI T1/E1 blade for edge and enterprise-level communications systems • Designed for applications requiring 

high-performance monitoring of multiple T1/E1 ports • 32 T1/E1 ports supporting 1024 HDLC channels • 6U CompactPCI board compliant 

to PICMG 2.16 R1.0 • IPMI subsystem monitors system status • Includes a PowerPC-based PMC card running Linux for control I/O • 

Includes a Linux support package 

A 6U, single-slot CompactPCI blade for transmitting voice and data over an integrated ATM network • 66 MHz/64-bit CompactPCI 

interface • Capable of sending and receiving a total of 2048 simultaneous voice and data virtual circuits over a single fiber-optic 

connection at speeds up to 155 Mbytes/sec • ATM AAL1, AAL2, and AAL5 support on intelligent ATM interface card • Bidirectional 

voice channel capacity • Onboard OC-3/STM-1 optical physical interface (PHY) • Two 10/100Base-T Ethernet MAC/PHYs accessed 

through front I/O • Supports up to 2048 full-duplex AAL1 VCs without Channel Associated Signaling (CAS) or up to 1023 full-duplex 

AAL1 or AAL2 with CAS • High-bandwidth intersystem communication interfaces include H.110 TDM bus • High-level host processor 

APIs • Driver development kits available 

www.voiceboard.com 

A processor blade for converting TDM data to IP packets • HDLC frame extraction, insertion, and CRC checking • 56K or 64K data handling 

• Programmable ring buffer sizes for real-time and data capture modules • Generation of user-specified data patterns • Selection 

of any 1024 time slots (512 bidirectional channels) from the H.110 TDM backplane • IP data streaming via dual 10/100Base-T Ethernet 

ports • RTP or AAL packetizing of data streams • Data time stamping • Independent control of each channel’s real-time streaming and 

buffered memory data capture modes • PICMG 2.16 PSB compliant • Selectable data capture termination modes with snapshot data 

capture mode • May be optionally equipped with eight software selectable T1/E1/J1 span network interfaces 


Servers – VoIP 

Company Name Model No. Web Address 

Adlink Technology 

www.adlinktech.com 

cPCIS-3300BLS series 

cPCIS-6125 

Advantech 

www.advantech.com 

RS-100 

RS-200-RF 

SPC-200 

SPC-201 

ZA-101S 

American Megatrends 

www.ami.com 

Indium 

Anatel 

www.anatel.com 

TAP-804N 

TAP-806 

TAP-810 

Appliance-Lab 

www.app-lab.com 

ICurBox CyberNode 

CyberNode Lite 

Arbor Technology 

www.arborsolution.com 

HiCORE-i6311 

Arista 

www.aristaipc.com 

HiServer 310 

Power Racer 201 



Power Racer RS-100 

AudioCodes 

www.audiocodes.com 

MGCP 

MP-100 

MP-104 

MP-108 

TP-400 

TP-610 

VoicePacketizer 

Avocent Corporation 

www.avocent.com 

AutoView 1000R 

AutoView 2000R 

Broadax 

www.bsicomputer.com 

PServer R9 

PServer V9 

Celestix 

www.celestix.com 

Taurus 

Centura 

www.centurasoft.com 

eSNAPP 2.0 

Cepoint 

www.cepoint.com 

RAMBO 2200-IT 

Crystal Group 

www.crystalpc.com 

CS200 

Diversified Technology 

www.dtims.com 

CRM120A 

CRM220A 

FieldServer 

www.fieldserver.com 

FS-B2010 

Force Computers 

www.forcecomputers.com 

Centellis CO 28000-10U 

CPCI-735/736 

CPSB-560 

FES-4203/533 

FES-4204 

PowerServer 4204-1U 

GAO Research 

www.gaoresearch.com 

VolP ‘C54x 

GE Fanuc Automation www.gefanuc.com/embedded 

CP721 

CP723 

GNP 

www.gnp.com 

cNode 

ComputeNode 

cServer 

I-BUS 

www.ibus.com 

Continuon 8U/CHP 


Servers 

VoIP 

Company Name Model No. Web Address 

I-BUS (continued) 

www.ibus.com 

Continuon 8U/CHS 

Continuon 8U/CP 

Iskratel 

www.iskratel.ru 

Calidia 

ITOX 

www.itox.com 

Baby Cobra 

King Cobra 

Little Dragon Series 

Kallastra Inc. 

www.kallastra.com 

KeyTrunk500 Series 

Kane Computing 

www.kanecomputing.com 

Voice + Fax over IP 

Lanner Electronics 

www.lannerinc.com 

SB-162 

SB-262 

Lantronix 

www.lantronix.com 

USNET IAP 

USNET Web Server 

Marathon 

www.marathon-int.com 

Ultra Tokay 

Mediatrix 

www.mediatrix.com 

Softphone 


mcg.motorola.com 

WTRB500 

NetCentrex 

www.netcentrex.net 

SVI 

NETsilicon 

www.netsilicon.com 

NET+Lx 

NEXCOM International 

www.nexcom.com 

NexBlade Servers 

Octasic 

www.octastic.com 

OCT9600 Series 

One Stop Systems 

www.onestopsystems.com 

OSS-ENCL-3U-SERVER 


www.pt.com 

MTN4100 

Portwell 

www.portwell.com 

NAR-7060 

Rauch Medien 

www.rauchmedien.com 

Prolinium 1850 

Sealevel Systems 

www.sealevel.com 

SeaLINK 

Sequoia 

www.sequoia.co.uk 

Axiom AX6113 

Siliconrax Sliger 

www.siliconrax-sliger.com 

DEMI 

CTI-400D 

SKY Computers 

www.skycomputers.com 

SMARTpac 600 

SSV Software Systems 

www.ssv-embedded.de 

ADNP/1486 

Sun Microsystems 

www.sun.com 

Netra ct 400 

Netra ct 800 

Ultra AXe 

Synergetic Micro Systems 

www.synergetic.com 

EmbeddedComm EC-1 

Telco Systems 

www.telco.com 

EdgeGate CPE 

Themis Computer 

www.themis.com 

RES-22XE 

RES-31i4 

T-210 

Trenton Technology 

www.trentontechnology.com 

ULE 

Tundo Corporation 

www.tundo.com 

NTS Release 3.3 

UVNetworks 

www.uvnetworks.com 

UV30 WebBox 

WebBox 1000 

VoicePump 

www.voicepump.com 

VoicePump-6000 

Servers 

VoIP






By Eli Shapiro 

TABLE OF CONTENTS 

ARINC ............................................................. 61 

Blades ............................................................ 61 

Board Accessories ............................................ 61 

Bridge: PCI-to-PCI ........................................... 62 

Chips & Cores: FPGA ........................................ 62 

Datacom: Serial Controller ............................... 62 

Datacom: WLAN .............................................. 62 

Development Platform .................................... 62 

DSP Resource Boards ...................................... 62 

Gateways ........................................................ 63 

Mass Storage: Serial ........................................ 63 

Memory: General Purpose .............................. 63 

Power Supply .................................................. 63 

Processor: Pentium .......................................... 63 

Processor: PowerPC ......................................... 63 

Prototyping and Debugging Aids ..................... 65 

Prototyping and Debugging: JTAG ................... 65 

Radar/Sonar .................................................. 65 

Software: Development Tool ............................ 65 

System Boards ................................................ 66 

System Monitoring .......................................... 66 

Telecom: T1/E1 ............................................... 66 

Thermal Management ..................................... 66 

Turnkey System .............................................. 66 

Wireless: Bluetooth ......................................... 66 

10/100/1000 Gigabit Ethernet copper egress ports 

located on the front panel and three copper 10/100/1000 

ports on the rear panel of the board. Aggregation, 

Quality of Service (QoS), and mirroring are supported 

on the switch board • System management of 

temperatures and voltages monitored via the IPMI 

(Intelligent Platform Management Interface) supporting 

the 1.5 protocols • Two serial management ports, 

reset switch, and status LEDs for all ports integrated 

into the front bracket 

SBS Technologies, Inc. 

Website: www.sbs.com 

Model: HDTBlade RSC No: 17450 

A high-density CompactPCI T1/E1 blade for edge 

and enterprise-level communications systems • 

Designed for applications requiring high-performance 

monitoring of multiple T1/E1 ports • 32 T1/E1 ports 

supporting 1024 HDLC channels • 6U CompactPCI 

board compliant to PICMG 2.16 R1.0 • IPMI subsystem 

monitors system status • Includes a PowerPC-based 

PMC card running Linux for control I/O • Includes a 

Linux support package 

BOARD ACCESSORIES 

SMA Computers 

Website: www.SMAcomputers.com 

Model: CPU1.2RIO RSC No: 17495 

A rear I/O extension board for use with all versions 

of the SMA CompactMAX CPU1.2 host computer 

• Provides access to the interfaces on the rear I/O 

J2 connector of the host • Available with a 4HP front 

panel (CPU1.2RIO-41) with one USB port, two 

Fast Ethernet ports, one PS/2 port, and one serial 

interface, or 8HP front panel that also includes one 

extra serial and one extra USB interface, as well as a 

DVI connector 

ARINC 

Condor Engineering 

Website: www.condoreng.com 

Model: CEI-830 RSC No: 17472 

A high-density ARINC 429 PMC module • Up to 16 

transmit and 16 receive channels in a single slot • Highperformance, 

high-density interface with large buffers 

• 66-MHz PCI bus • Optional ruggedized, extended 

operating temperature configurations • Conductioncooled 

versions available • High-level software API 

for VxWorks, Windows 95/98/Me/NT/2000/XP • Fully 

independent channel operation • Supports maximum 

data throughput on all channels simultaneously • 

Independent, software-programmable bit rates for all 

channels • Optional IRIG B receiver/generator 

BLADES 

Diversified Technology, Inc. 

Website: www.dtims.com 

Model: ATS-1136 RSC No: 17487 

An AdvancedTCA switch blade • Supports the fabric 

through the AdvancedTCA 3.1 Ethernet specification 

option • Switches both the base and the fabric at 

Gigabyte Ethernet wire-speed • 36 Gigabit Ethernet 

ports in the 8U mechanical specification defined by 

industry standards • AdvancedTCA Base Interface 

supports 16 AdvancedTCA payload slots • Two 



BRIDGE: PCI-TO-PCI 

Pericom Semiconductor 

Website: www.pericom.com 

Model: PI7C815xA/B RSC No: 17434 

Performance-enhanced 32-bit, two-port PCI-to-PCI 

bridge devices that support both 33- and 66-MHz 

frequencies • Asynchronous mode support • Intel 

compatible • Supports nine secondary bus masters 

(four secondary bus masters with 8152x) • 5V and 3.3V 

signaling • Extended commercial temperature range 

CHIPS & CORES: FPGA 

Acromag, Inc. 

Website: www.acromag.com 

Model: PMC-DX500/DX2000 RSC No: 17410 

A line of reconfigurable FPGA PMC I/O modules 

• Cost/performance mix suitable for mid-level computing 

functions • Xilinx Virtex-II FPGAs with 500K 

(PMC-DX500) and 2M (PMC-DX2000) system gates 

• Up to 1 Mb of on-chip memory and 9 Mb of onboard 

SRAM • I/O configurations available to process TTL, 

differential RS-422, and LVDS digital I/O signals • 

Fast PCI interface with 32-bit/66-MHz bus mastering 

• Supports dual DMA channel data transfer to the 

CPU • Available with either 64 bidirectional TTL I/O 

lines, 32 RS-422 differential I/O lines, or 32 LVDS I/O 

lines • Extended temperature (-40˚ to +85˚C) models 

available • Software support for Windows, QNX, 

VxWorks, and other operating systems 

Pentek, Inc. 

Website: www.pentek.com 

Model: 6251 RSC No: 17473 

A configurable logic FPGA VIM-2 module • Supports 

high-performance custom signal processing • Up to 

two FPDP or LVDS I/O front-panel interfaces • Xilinx 

Virtex-II Pro series FPGAs • FPGA configuration 

package includes VHDL source code and design 

examples • FPGA configuration code can be downloaded 

from processor nodes or stored in non-volatile 

EEPROM • Onboard auxiliary SDRAM and Flash 

memory • Factory-installed cores available 

DATACOM: SERIAL CONTROLLER 

Tews Technologies LLC 

Website: www.tews.com 

Model: TIP115 RSC No: 17406 

A five-channel synchronous serial interface (SSI) 

interface • Single-size IP module; interface according 

to the IndustryPack specification • Operates in 

standard SSI interface controller mode and in listenonly 

mode • SSI data word length programmable from 1 

bit to 32 bits • Binary or Gray-Code data word encoding 

• Parity: odd, even, or without • 1s to 15s SSI clock 

rate • EIA-422 encoder inputs galvanically isolated 

by high-speed optocouplers • 0˚C to +70˚C operating 

temperature range 

DATACOM: WLAN 

SMC Networks 

Website: www.smc.com 

Model: SMC2512W-B/AG RSC No: 17477 

A set of two high-power wireless PCI cards for 

802.11b (SMC2512W-B) and universal 2.4/5 GHz 

(SMC2512W-AG) applications • The SMC2512W-B 

provides 802.11b connectivity with up to 200mW of 

transmit power, operating range of up to 2,700 feet, and 

seamless operation on any 802.11b or 802.11g network 

• The SMC2512W-AG provides universal connectivity 

to any 802.11a, b, or g network, 100mW of transmit 

power, and an operating range of up to 2,145 feet 

• Includes an EZ Installation wizard • Fully compliant 

to IEEE 802.11 standards • Both models support WPA 

and user authentication via RADIUS 802.1x, EAP, LEAP, 

and PEAP 

DEVELOPMENT PLATFORM 

Kane Computing 

Website: www.kanecomputing.com 

Model: VSIP RSC No: 17749 

A Video Security over Internet Protocol (VSIP) 

development platform • Includes a ready-to-use 

TMS320DM642 digital media processor-based 

development board, including relevant peripherals 

and accessories • Embedded software, including 

audio/video compression libraries, applicationoriented 

algorithms and application samples in 

source code • PC supervision application including 

decode and embedded platform control • Complete 

set of documentation • Comprehensive development 

environment including DSP development tools, 

programmable logic development tools, and emulator 

for DSP 

Schroff 

Website: www.schroff.us 

Model: 5-slot Integrated System RSC No: 17455 

5U, 5-slot integrated AdvancedTCA system for 

deployment or development applications • 5-slot fullmesh 

backplane with two hub slots • Cooling scheme 

supports up to 200W per slot • Optional dual-redundant 

hot-swap shelf managers • Suitable for deployment in 

NEBS applications • Independent fan controller • Dual 

48V inputs on the rear • Access to the top board for 

debug • Shielding • 19-inch rackmount capability 


DSP RESOURCE BOARDS 

Innovative Integration 

Website: www.innovative-dsp.com 

Model: Delfin RSC No: 17458 

A 64-bit PCI DSP card • 150-MHz TMS320C6711 DSP 

(floating point) • 32 simultaneous channels, up to 192 

KHz, 24-bit input • 8 or 16 input channel configurations 

available • Six channels, 192-KHz, 24-bit output • 64 bits 

digital I/O • 32 MB of SDRAM • 32/64-bit PCI, 33 MHz, 

5V/3.3V 


GATEWAYS 

FieldServer 

Website: www.fieldserver.com 

Model: EtherNet/IP Gateway RSC No: 17446 

A gateway that enables interfacing between Ethernet/ 

IP devices and a wide range of devices found in the 

process control and building automation industries 

• Device driver library supports more than 70 different 

protocols, including DF1, DH+, DNP, ControlNet, SNMP, 

Profibus, and Modbus • Companion drivers available 

for fire alarm panels, HVAC equipment, chillers, boilers, 

and other equipment • Available in the single-port 

FS-B20 Series version or the multiport FS-B40 Series 

model • True protocol translator 

HMS Industrial Networks, Inc. 

Website: www.anybus.com 

Model: AnyBus-x RSC No: 17409 

A family of gateway products for connecting any two 

industrial networks • Supports 15 different Fieldbus 

networks, such as PROFIBUS, DeviceNet, CANopen, 

and CC-Link, as well as an Ethernet version with 

Modbus/TCP, EtherNet/IP protocol, e-mail client, 

and embedded Web server • Designed for use in 

automated industrial plants where different Fieldbus 

networks are used • Rugged metal housing is usable 

in harsh industrial environments with standard DIN 

rail mounting, IP 20 rating, and 24V power supplies 

• Supports fanless operation in the industrial 

temperature range • Modular design based on two 

embedded AnyBus communication modules and one 

additional gateway processor • 10 diagnostic LEDs 

indicate communication status and gateway status 

• Incorporates both master and slave interfaces and 

is capable of creating more than 120 combinations 

with no programming necessary • Configurable via 

auto-baudrate, DIP switches, terminal emulators 

(RS-232 interface), firmware download, setting of 

I/O sizes, status, version handling, and EDS and GDS 

configuration files 

MASS STORAGE: SERIAL 

Dynatem, Inc. 

Website: www.dynatem.com 

Model: PMCX-SATA RSC No: 17445 

A high-performance, quad-channel, Serial ATA 

(SATA) interface PMC-X mezzanine • Four channels 

of Serial ATA accessible from the front panel • Each 

channel has a maximum transfer rate of 1.5 Gbps 

• Uses Intel’s 31244 Serial ATA controller • 64-bit/ 

133-MHz PCI-X interface • Backward compatible 

with 32- and 64-bit PMCs from 33 MHz • Compliant 

with SATA 1.0 and SATA II (extensions to SATA 1.0) 

• Windows NT/2000/XP and Linux drivers available 

MEMORY: GENERAL PURPOSE 

Chrislin Industries, Inc. 

Website: www.chrislin.com 

Model: CI-PCI-FC RSC No: 16643 

A high-speed SDRAM memory buffer that interfaces 

to the PCI bus • Bursts up to 528 MBps on the 

PCI bus • 256 MB to over 2 GB on one full PCI card 

• 64-bit/66-MHz PCI 2.2 compliant • Four ports of VITA 

17.1 duplex Fiber ports • Four ports of local pointto-point 

ports • Programmable serial transfer rates 

of 1 GBps and up to 3.7 GBps • Pluggable SFP optic 

tranceivers • Upgradeable memory options available 

• Dual independent memory arrays • Block and 

scatter/gather DMA transfers • LED indicators: PCI, 

FC, ALU, CHA, CHB, CHD, CHK, and ERR 

• Available as 150W (ZWS150PAF) and 240W 

(ZWS240PAF) models • Suitable for powering motors 

and printers where a peak current demand is needed 

for a short duration • 85 to 265VAC input voltage range 

• Power Factor Correction (PFC) circuitry to meet 

EN61000-3-2 standards • Available with 24V, 36V, or 

48V outputs • Available in open-frame, L-bracket, or 

fully enclosed configurations • Molex, JST, or screwterminal 

connections • Meets Class B EMI standards 

• Safety approved to UL60950, CSA60950, EN60950, 

and EN50178 specifications • CE marked • Meets 

EN61000-4-X immunity standards 

PROCESSOR: PENTIUM 

Inova Computers, Inc. 

Website: www.inova-computers.de 

Model: ICP-PM RSC No: 17411 

A hot-swappable, 3U, single-slot (4HP) CompactPCI 

processor board • Accommodates a 1.6-GHz Pentium 

M processor which can be clocked from 600 MHz 

to 1.8 GHz in 200-MHz steps using BIOS selection • SiS 

chipset supports up to 1.5 GB of 33-MHz DDR RAM 

• Automatically configured as either a system master 

or system slave • Intelligent I/O configuration utility 

and a backup BIOS • Two USB interfaces • VGA port 

on the front panel • One combination Fast/Gigabit 

Ethernet interface and one Fast Ethernet interface 

• Rear-panel I/O includes an LPT/floppy interface, ATA 

133 interface, COM 1 and COM 2 ports, VGA graphics, 

and interfaces to a keyboard, mouse, and beeper 

• Optional dual-slot (8HP) front panel with additional 

I/O • CompactFlash socket with a standard IDE 

interface • Configurable for 64-bit CompactPCI • Fully 

x86 compatible • Supports popular operating systems, 

including Linux, QNX, VxWorks, and Windows • Also 

available in Pentium 4-M and extended-temperature 

models 

PROCESSOR: POWERPC 


Website: mcg.motorola.com 

Model: ATCA Blade RSC No: 17736 

An AdvancedTCA system controller and switching 

blade • Motorola MPC7447 1 GHz PowerPC 

POWER SUPPLY 

Lambda Electronics 

Website: www.lambdapower.com 

Model: ZWSxxxPAF Series RSC No: 17453 

Power supply series that can deliver 200 percent of 

the nominal current rating for up to 10 seconds 




microprocessor • 512 MB to 1 GB SDRAM • PMC-based, 

40-GB hard disk drive standard • Fully compliant with 

AdvancedTCA (PICMG 3.X) standards • Combines 

system control and fabric switching on a single blade 

• PICMG 3.0 base fabric switching, PICMG 3.1 data 

fabric switching 

PROTOTYPING AND DEBUGGING AIDS 

Lyrtech 

Website: www.lyrtech.com 

Model: SignalWAVe RSC No: 17436 

An entry-level DSP/FPGA development board, 

optimized for audio, video, and wireless applications 

• TMS3206713 DSP from Texas Instruments • Xilinx 

XC2V3000 Virtex-II FPGA • High-speed ADC and DAC 

up to 65 MHz • Video encoder and decoder • Audio 

codec • Supports co-simulation, real-time processing, 

and hardware-in-the-loop 

PROTOTYPING AND DEBUGGING: JTAG 

JTAG Technologies B.V. 

Website: www.jtag.com 

Model: JT 37x7/TSI DataBlaster RSC No: 17435 

A boundary controller with auto-select of Ethernet, 

FireWire, and USB 2.0/1.1 interfaces • Scalable 

architecture allows smooth expansion to match testing 

and Flash ISP application requirements • Modular 

hardware and software for easy integration and customized 

configurations • Connects to a wide variety 

of computing platforms • Supports local and network 

interfaces via Ethernet port • Gang operation for highvolume 

parallel programming and testing using a single 

controller • Multiple controllers support high production 

throughput • Automatic matching of TCK speed 

to maximize chain performance, up to guaranteed 

40-MHz continuous data rate • Programmable TCK 

speed • Unlimited target memory width (1 bit to more 

than 64 Kbit) for Flash programming • Enhanced 

Throughput Technology (ETT) • Independent control 

of four TAPs per controller • Fully applicationcompatible 

with JT 3710 DataBlaster (no recompilation 

needed) • Supplied with JT 2147QuadPOD system 

with programmable signal drivers/sensors, highperformance 

signal integrity, and long-distance 

capability • Fully hardware compatible with existing 

POD configurations 


RADAR/SONAR 

Primagraphics 

Website: www.primag.co.uk 

Model: Advantage Xi RSC No: 17407 

A COTS radar scan converter card in half-size PCI 

form factor • Designed for applications including 

command and control consoles, vessel traffic display 

systems, and radar head monitors • Uses 

Primagraphics’ White-Powell algorithm • Scan conversion 

rates of more than 3M pixels per second 

for plan position indicator (PPI) and B-scan display 

formats • Accepts digital video (DVI) from a graphics 

card • Radar picture is combined with the graphics 

using a digital keying technique that allows graphics 

to be displayed as an overlay to the radar video or 

as an underlay that is semi-transparently mixed 

with the radar • Outputs both analog RGB and digital 

DVI-D video at programmable screen resolutions up to 

1600 x 1280 

SOFTWARE: DEVELOPMENT TOOL 

Agilent Technologies 

Website: www.agilent.com 

Model: VEE Pro 7.0 RSC No: 17454 

A standards-based graphical programming environment 

• Uses a graphical environment to handle 

all common measurement tasks in design and 

manufacturing, including connecting instruments, 



measurement, analysis, and reporting • Enhancements 

to version 7.0 include: quick and simple access 

within the Microsoft .NET framework, undo and redo, 

property editing, expanded panel editing such as visible 

grid, rubberband, and object alignment • Supports 

direct LAN and USB-connected instrumentation using 

industry-standard protocols • Supports industrystandard 

IVI-COM instrument drivers 

SYSTEM BOARDS 

Adlink Technology America, Inc. 

Website: www.adlinktech.com 

Model: M815E RSC No: 17449 

A long-life, industrial Micro-ATX motherboard with 

onboard 10/100Base-T LAN, AGP 4X 2D/3D VGA, 

and AC97 audio • Supports Pentium III processors 

at up to 1.4 GHz • Up to 512 MB of PC-133 SDRAM 

• CompactFlash socket • Two available ISA slots and 

three available PCI slots • 4 MB video RAM cache 

• Supports low-wattage VIA C3 processors 

SYSTEM MONITORING 

Dawn VME Products, Inc. 

Website: www.dawnvme.com 

Model: Model 426 RSC No: 17496 

A bus-independent system health monitor/controller 

board that uses Dawn’s RuSH µP technology • Optimized 

for deployment in a commercial or COTS chassis 

with a VME, VME64x, or CompactPCI backplane 

• Connects to thermocouples, fans, and power supply 

input and output voltages • Onboard microprocessor, 

RS-232, and Ethernet ports • Accessible via Web 

browser or terminal emulator over the Internet • Does 

not use a backplane slot 

TELECOM: T1/E1 

N.A.T. GmbH 

Website: www.nateurope.com 

Model: NPMC-8280-4E1/T1/J1 RSC No: 17408 

A quad E1/T1/J1 PMC telecommunication interface 

board • Based on the MPC8280 PowerQUICC II 

processor at 300 or 450 MHz • Four E1/T1/J1 ports 

with RJ-45 connectors, an RS-232 port, and a 

10/100Base-T Ethernet interface on the front panel 

• H.110 TDM bus controller • Up to 256 MB of DRAM 

and either 16 or 32 MB of onboard erasable Flash 

memory • BSPs available for VxWorks and Linux 

THERMAL MANAGEMENT 

Acromag, Inc. 

Website: www.acromag.com 

Model: BusWorks 900EN Series RSC No: 17448 

Six-channel input modules for interfacing thermocouple 

and millivolt signals directly to an Ethernet 

Modbus/TCP 10/100 network • Operates independently 

of any bus coupler or I/O rack • No special 

system power supply required; operates on 15VDC 

to 36VDC power supplies • Configurable using a standard 

Web browser • Accepts thermocouple/millivolt 

inputs with user-selectable ranges for Type J, K, T, 

R, S, E, B, or N sensors and bipolar ±100mV or ±1VDC 

signals • 16-bit Sigma-Delta A/D converters and built-in 

CJC sensors • Three-way 1,500VAC isolation between 

the input, network, and power circuits • Each module 

supports up to 10 sockets, allowing communication 

with multiple masters • Built-in watchdog timers 

• Internal microcontroller with integrated nonvolatile 

memory for configuration parameters 

TURNKEY SYSTEM 

Advantech Technologies 

Website: www.advantech.com 

Model: PPC-174T RSC No: 17475 

A Pentium 4 processor-based panel PC with a 17" LCD 

display • Intel 845GV chipset with integrated graphics 

controller • Supports Intel HyperThreading technology 

• Intel Pentium 4 processor at up to 3.06 GHz • AC97 

audio with Dolby Digital 5.1 surround sound • Up to 2 

GB of DDR SDRAM • Onboard PCI Ethernet controller 

• Two PCI sockets for expansion • Built-in CD-ROM 

and floppy disk drives • CompactFlash socket • Two 

PCMCIA Type II slots • Four USB 2.0 ports • Removable 

3.5" HDD bay • Resistive, capacitive, or surface 

acoustic wave touchscreen options • Follows the 

VESA mounting standard • Suitable for industrial and 

HMI applications 

WIRELESS: BLUETOOTH 

AVX Corporation 

Website: www.avxcorp.com 

Model: RB06 RSC No: 17437 

A Bluetooth RF module for Code Division Multiple 

Access (CDMA) mobile phones • Developed and 

manufactured by Kyocera Corporation • Incorporates 

the Broadcom BCM2004 Bluetooth radio chip to 

optimize the function of the module for QUALCOMM’s 

MSM solutions • 5.0mm x 4.0mm x 1.4mm • Certified 

compliant with Bluetooth version 1.1 and 1.2 • Low 

power consumption during sending (36mA to 70mA) 

and receiving (38mA) RF signals • Embedded 2.4-GHz 

band pass filter in the LTCC substrate • Reception 

sensitivity to -88dBm or below • Standby power 

consumption of less than 50µA

Embedded Computing Design - OpenSystems Media

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