VITA 46.9: Ensuring mezzanine I/O pinout interoperability for VPX ...

More documents

Recommendations

Info

VPX ... Almost REDIHardwarepinout mapping would be symmetrical,for example, work on either a 6U VPXP3/4 set or on a P5/6 set. In addition, theworking group also defined differentialpinout usage for 3U VPX cards and theirP1/2 set. The result is that VITA 46.9solves XMC/PMC I/O mapping on VPXand ensures and greatly simplifies theinteroperability of basecards and mezzanineI/O cards from different vendors.“VITA 46.9 ensuresinteroperability whileproviding flexibility byoffering a number ofstandard combinations.”Innerworkings of VITA 46.9The objective of the VITA 46.9 standard isto supplement the VITA 46.0 base standardto fully define the user I/O signal mappingbetween the pins of PMC and/or XMC cardsites provided on a VPX compliant carrierfor both 3U and 6U modules. In addition,it defines the fabric mapping for a 3Umodule and placement for two channelsof GbE 1000BASE-T. VITA 46.9 ensuresinteroperability while providing flexibilityby offering a number of standard combinations.The following combinations weredetermined the most likely to be actuallyimplemented in practice: PMC Jn4 assigned to 3U V46-P2differential and single-endedconnector XMC Jn6 assigned to 3U V46-P2differential connector PMC Jn4 assigned to 6U V46-P3,5 differential connector XMC Jn6 assigned to 6U V46-P3/4,5/6 differential connectorTo accommodate this, various mappingpatterns have been defined: P64s – Maps all 64 contacts ofPMC-Jn4 to VPX differential wafers. X12d – Maps 12 selected differentialpairs of XMC-Jn6 to VPX differentialwafers. X20d24s – Maps all 20 differentialpairs of XMC-Jn6 and 24 single-endedpairs to VPX differential wafers. Thispattern fits within one VPX connector. X20d38s – Maps the entire XMCconnector to VPX differential wafers.This consists of all 20 differential pairsof XMC-Jn6 and all 38 single-endedsignals.For 6U cards, several overall configurationscan be accommodated by selectingfrom the previously defined mappingpatterns (see Figure 1): VPX P3/P5 mapped to PMCJn4 using the P64s and P4/P6 mappedto the XMC Jn6 using the X12dpattern VPX P3/4, P5/6 mapped to XMCJn6 using the X20d38s pattern6U VPX ModuleXMC/PMC ModuleJn5 Jn1 Jn2Jn6Jn3X20d38sJn4X12dJn5 Jn1 Jn2X20d38sJn6 Jn3 Jn4X12dP64sP64sFigure 1keyP0P1P2keyP3P4P5P6keyFor 3U cards, the following configurationsare supported, as shown in Figure 2: VPX P2 mapped to PMC Jn4 usingthe P64s and P1 mapped to the XMCJn6 using the X12d pattern VPX P2 mapped to X20d24s3U VPX ModuleXMC/PMC ModuleJ15 J11 J12J16J13X12dJ14X20d24sP64sFigure 2keyP0P1P2keyFigures 1 and 2 both show all configurationsmapped on a carrier card. However,in practice, only one configuration willbe mapped at a time. For example, a VPXcarrier card that supports only a PMCmezzanine will only use the P64s mappingas it will only have Jn4 installed.For a VPX carrier card that supportsonly XMC Jn6, then the X20d38s mappingwill be used in the 6U case and theX20d24s mapping will be used in the3U case. For a VPX carrier card that supportsboth XMC Jn6 and Jn4, then P64sand X12d would be mapped.ForSinglePrintOnlyVME and Critical Systems ©2007 OpenSystems Publishing. Not for Distribution.VITA 46.9 mapping patternsexploredThe mapping pattern P64s is relativelystraightforward. The P64s maps the 64 Jn4I/O pins on a PMC mezzanine to the VPXRT2 connector. The 64 pins are arrangedas two rows of 32 pins each. One columnis labeled odd and the other even. Inselecting the differential pairs, the workinggroup selected pins next to each otheras differential pairs. That is, pins 1-3are considered a differential pair and pins2-4 are considered a differential pair.This approach was taken to ease matchedlength routing on the PMC module and thecarrier card. These pins are then mappedto the VPX RT2 connector.
HardwareVPX ... Almost REDIThe mapping pattern X12d was a morecomplex challenge. The X12d maps12 differential pairs of the XMC Jn6connector to the RT2 connector. Theworking group chose 12 differential pairsas a good tradeoff between the amount ofXMC I/O mapped to the MultiGig RT-2connector versus the number of I/O linesleft over for use by the host card itself. Theworking group spent much time debatingthis mapping. The main issue was which12 pairs should be mapped? The XMCJn6 connector is an open field connectorarranged as 6 columns (A to G) and19 rows of pins, for a total of 114 pins.Much signal integrity work was done inthe XMC working group. It showed that20 differential pairs can be obtained byplacing them on the odd rows on columnsAB, DE with grounds on the even rows ofthose same columns. The XMC workinggroup further defined that rows 1,3,5,7were to be transmit lines and 11,13,15,17were to be receive lines. This approachprovides an XMC mezzanine card with theability to support up to eight lanes of serialtx/rx traffic. The working group decidedto stay with this pattern and allowed8 differential pairs for a fabric port onrows 1,3 and 11,13 and assigned theremaining 12 pairs for the X12d backplaneI/O pattern.The patterns X20d24s and X20d38s hencefell out from this effort once the X12dpattern was defined. The X20d24s patternmaps 20 pairs and 24 single-ended pinsfrom columns C and F to a single RT-2connector. The X20d38s pattern maps20 pairs and 38 single-ended pins fromcolumns C and F over two RT-2 connectors.Note that the X20d38s pattern maps78 pins to the RT-2 connector. This is thefull complement of pins on the 114 pinXMC connector as the rest are dedicatedto grounds.VITA 46.9 speeds futuredevelopmentBy ensuring that mezzanine I/O differentialpair mapping was defined in theVPX specification – and particularlyVITA 46.9 – the VPX working group hasensured that mezzanine, basecard, andbackplane/chassis designers will have theproper information to enable them to designinteroperable PMC and XMC I/O mezzaninecards. This will help ease the adoptionof new high-speed VPX and VPX-REDIapplications, paving a smoother pathto the future for the end users of today’schallenging applications. CSJing Kwok isprincipal engineerin the TechnologyGroup at Curtiss-Wright ControlsEmbeddedComputing. Hehas been involvedwith VMEbus standards work for thepast 15 years. He is editor of one ofthe VITA 46 “dot” specifications nowin working group ballot and was oneof the chapter editors for the VME64specification. Jing is a graduate ofthe British Columbia Institute ofTechnology.For more information, contact Jing at:Curtiss-Wright ControlsEmbedded Computing333 Palladium Drive, m/s 385Kanata, ON, Canada K2V-1A6613-599-9199, Ext. 5825jing.kwok@curtisswright.comwww.cwcembedded.comForSinglePrintOnlyVME and Critical Systems ©2007 OpenSystems Publishing. Not for Distribution.
Page 1: HardwareVPX ... Almost REDIVITA 46.

VITA 46.9: Ensuring mezzanine I/O pinout interoperability for VPX ...

Create successful ePaper yourself

Delete template?

Save as template?