AN369: Si4010 Antenna Interface and Matching Network ... - wless.ru

AN369Si4010 ANTENNA I NTERFACE AND MATCHING NETWORKG UIDE1. IntroductionThis document provides guidelines and design examples for the high impedance matching networks and loopantennas necessary for the proper usage of the Si4010 transmitter.Section “2. High Impedance Differential Power Amplifier” gives a brief overview of the differential high impedancePA used in this chip. It also describes the method for determining the optimum termination impedance necessary toacquire the maximum power.Section “3. Inductively Tapped Loop Antenna Design Example” describes basic design steps, simulation, andmeasurement results for an inductively tapped printed loop antenna working at 434 MHz with the Si4010 chip andwith the SOIC package.Section “3.1. Antenna Dimensions and Measured Data with Si4010-A0-GS Engineering Version” shows therealized loop antenna with dimensions and the test results. This section is devoted to readers who are not greatlyinterested in the design details of the antenna; rather, they are concerned with quickly obtaining dimension, layout,and measurement data. The measured results shown in this document use the Si4010-A0-GS engineeringsamples. Measured results with the B1 chip will be provided in future versions of this document.Section “3.2. Detailed Antenna Design Steps Using a Planar EM Simulator (Sonnet)” briefly summarizes the designsteps of the antenna, again with the Si4010 preliminary engineering samples.Section “4. Matching Balun Design for Si4010 with 50 Single-Ended Output” describes the design steps for thematching balun, which matches the high impedance differential outputs of the Si4010 chip to a 50 single-endedtermination or antenna such as monopole, spiral, ILA, etc.Section “4.1. Matching Baluns for Si4010_B1 with SOIC and MSOP Package” gives the matching networkschematic and measured results for both the SOIC and MSOP packages. These sections are useful for readerswho are not greatly interested in the theoretical development of the matching network but who are concerned withquickly obtaining a set of component values for a given desired frequency of operation.Section “4.2. High Q Discrete Matching Baluns” describes the design procedure and operation of the matching.2. High Impedance Differential Power AmplifierThis section discusses the operation of the high impedance class A power amplifier used in the Si4010 chips. Intheory the delivered power to the load is maximum if the RF generator is terminated by the complex conjugate of itsgenerator impedance. This is called optimum conjugate matching. However, it is true only if no constraints forvoltage swing are given.Operation of the high impedance PA is illustrated in Figure 1. High impedance PAs usually have open drain outputsand behave like a RF current generator. The TX generator impedance is represented by its parallel RC equivalentwhile the termination by its parallel RL equivalent. The L AP and C TX work in high impedance parallel resonance atthe operation frequency and thus the voltage swing is determined by the residual equivalent resistance of thetermination (R AP ) and the TX internal loss (R TX ).The drain voltage is limited by the CMOS technology. With a fixed current magnitude I RF , if the generatorimpedance is too high, the voltage swing would exceed the limit with complex conjugate termination.Rev. 0.1 7/10 Copyright © 2010 by Silicon Laboratories AN369

AN369Figure 1. Operation of the High Impedance PAIn this case lower termination impedance has to be used (i.e. RAP

AN369A second important operation mode is when the current magnitude is reduced (e.g. to reduce the power) and thusthe maximum allowed voltage swing is not achieved even if the conjugate complex termination is applied. In thiscase the PA is "current limited". This is the typical case when the Si4010 chip works in a strongly reduced powerstate or when the internal capacitance bank state is high (close to maximum at low bands and above ~100 in highbands). In this operation mode the optimum termination is the complex conjugate.A third, non-optimum mode is when the current is maximum, but the termination impedance is so low that themaximum swing is not achieved. In this case the termination is not the optimum, and the power and efficiency islower than the possible maximum.Table 1. SOIC Maximum Power OperationFreq [MHz]SOICOpt. loadimp. []Opt. loadadm.[mSie]Parallel Eqv.R AP[]Parallel Eqv.L AP[nH]Cap. bankstate & TXequivalentcapacitance(CTX)Power to thedifferentialload [dBm]315 TBD TBD TBD TBD TBD TBD434 34.13+j123.36 2.08–j7.53 480 48.7 19; 2.76pF 10.7868 8.07+j57.64 2.38–j17.02 420 10.8 17; 3.12pF 9.4915 TBD TBD TBD TBD TBD TBDTable 2. MSOP Maximum Power OperationFreq [MHz]MSOPOpt. loadimp. []Opt. loadadm.[mSie]Parallel Eqv.R AP[]Parallel Eqv.L AP[nH]Cap. bankstate & TXequivalentcapacitancePower to thedifferentialload [dBm]315 TBD TBD TBD TBD TBD TBD434 33.8+j126.8 1.96–j7.36 510 49.8 19; 2.70pF 10.8868 8.9+j68.1 1.89–j14.44 530 12.7 9; 2.65pF 9.85915 TBD TBD TBD TBD TBD TBD3. Inductively Tapped Loop Antenna Design Example3.1. Antenna Dimensions and Measured Data with Si4010-A0-GS Engineering VersionThis antenna design uses the Si4010-A0-GS version of the Si4010 chip. The designed antenna top layout with finalouter dimensions is shown in Figure 2. The bottom layout is shown in Figure 3. The schematic is shown inFigure 4. The manufacturing pack (including CAM/CAD/PDF files and the BOM) is available at www.silabs.com.The whole unit is encapsulated by the Polycase FB-20 plastic enclosure as shown in Figures 5–7.Rev. 0.1 3

AN369Figure 2. Antenna Top Layout with Final Outer DimensionsFigure 3. Antenna Bottom Layout with Final Outer Dimensions4 Rev. 0.1

AN369Figure 4. 4010-DAPB434 SchematicThe maximum of the radiated fundamental second and third harmonic power with hand effect (the unit was held)both in the 7 mA and 10 mA (PA boost function) tail current state are given in Table 3. During the measurementsthe direction and the orientation of the unit are turned until the maximum is found.The third row of the table shows the maximum without hand effect. In these measurements the maximum at threecuts and with different receiver antenna polarizations is given.Rev. 0.1 5

AN369Table 3. Maximum of the Radiated Fundamental,Second and Third Harmonic Power with Hand EffectEIRP [dBm]H-pol receiver, 10mAPlaneXY ZY ZX Handheld434 MHz TBD TBD TBD –7,5868 MHz TBD TBD TBD –32,71302 MHz TBD TBD TBD –22,7V-pol receiver, 10mAPlaneXY ZY ZX Handheld434 MHz TBD TBD TBD –11,8868 MHz TBD TBD TBD –36,71302 MHz TBD TBD TBD –24,21H-pol receiver, 7mAPlaneXY ZY ZX Handheld434 MHz –18,13 –14,8 –20 –8,8868 MHz –47,76 –38,7 –40,7 –33,71302 MHz –41,7 –30,7 –31,5 –27,7V-pol receiver, 7mAPlaneXY ZY ZX Handheld434 MHz –21,8 –27,8 –21,13 –15,3868 MHz –37,7 –53,4 –43,7 –35,71302 MHz –29,5 –45,7 –37,51 –30,76 Rev. 0.1

AN369Figure 5. Si4010-DAPB434 Key FobFigure 6. Si4010-DAPB434 in the Plastic Enclosure (Bottom)Rev. 0.1 7

AN369Figure 7. Si4010-DAPB434 in the Plastic Enclosure (Top)3.2. Detailed Antenna Design Steps Using a Planar EM Simulator (Sonnet)For the antenna design the Sonnet 2.5D EM simulator is used. The goal is to design the optimum antennaimpedance for the PA which results in the maximum power delivery to the antenna at cap bank state 128. Thereactance of this optimum antenna impedance is resonating with the PA output capacitance at internal capacitancebank state of 128. That is close to the lower edge of the output capacitance tuning range of the 4010 (0...511) inorder to increase the Q factor of the PA and thus decrease the internal losses. A basic EM simulated planarstructure is shown in Figures 8–10.8 Rev. 0.1

AN369Figure 8. Antenna Simulation (Bottom)Figure 9. Antenna Simulation (Top)Rev. 0.1 9

AN369Figure 10. Antenna Simulation in 3DThe antenna is fed from the left side through a differential transmission line. This transmission line is de-embeddedfrom the simulation by port extension. The reference plane of the simulation is shown by the black arrows. Theground planes on both side of the transmission line represent the PCB area of the unit’s circuitry. The antenna is aninductively tapped loop with the series capacitance in the main loop realized by a printed interdigital capacitor.The usage of an interdigital printed capacitor has many advantages:• Fine-tuning possible• No need for an extra component• Reduced value spreading due to the interdigital techniqueIn this design concept the Si4010 and the whole circuitry is outside of the antenna area. With this structure, outsideconnection to the circuitry is easier. In theory, the whole circuit could be placed inside the antenna area.Unfortunately, the increase of the useful antenna area due to this would be negligible but the interfacing of thecircuitry would be much more difficult.The unit is working from a CR2032 battery. The battery is placed at the bottom side beneath the printed capacitor(see the round shape battery’s pad at the bottom layer in Figure 3.) In this way:• The interdigital capacitor does not occupy additional space from the antenna area.• The battery and the metallization around it give some shielding and thus reduce the detuning of the printedcapacitor in the vicinity of a hand.The simulation box size is: 180 mm due to 128 Mb memory restrictions of the applied Sonnet level version. Withthis box size, the boundaries are far enough to avoid the disturbance of the antenna near field and thus the reactiveimpedance part (ie., the antenna inductance) estimation is quite accurate. Unfortunately, the distance is not big10 Rev. 0.1

AN369enough to accurately estimate the far field radiation of the antenna. Due to this, the antenna gain and the radiationresistance is not accurately simulated. With a bigger boundary box, which consumes more memory and requires ahigher level Sonnet V11 EM license, accurate far field simulation is possible. Also the structure can have amaximum of 2 metal layers and 6 ports with this Sonnet level. Despite this, the real part of the antenna impedanceis estimated relatively well as the ohmic and dielectric loss is usually dominant compared to the radiated loss incase of small loop antennas. During the simulation, the antenna is terminated by an ideal capacitance whichmodels the Si4010 output capacitance at cap bank state 128. Its typical value is ~4.90pF. The antenna and the PAcapacitance together form a parallel resonant circuit and with proper antenna design the resonance occurs at thetargeted operation frequency.Table 4 shows the used impedance parameters derived by the Si4010 optimum antenna impedance calculator(pa_impedance.xls). According to this, the optimum values in the parallel RL equivalent of the antenna are:Rp=480 , BL= 74.8 at 434MHz. It corresponds to 27.4 nH antenna inductance which is in resonance with the4010 output capacitance (4.90pF) at 434 MHz.Rev. 0.1 11

AN369Table 4. 128 Tuning Cap Used Impedance ParametersFreq[MHz]Attn max_drv 1434 0.93 ChipMaximum Output Voltage(Vpp/2)*095Tail Current(2*RF current magnitude) [mA]Parallel RC ModelComponent ValuesParallel TX Model AdmittanceTX Quality FactorParallel Load Resistance forMax Voltage SwingOptimal Load ImpedanceParallel ModelCapword DrvLvl Umax [V] Imax[mA]Rcp [Ohm] Ccp [F] Gcp [S] Bcp [S] QTX Rlpm [Ohm] Rlp[Ohm]Xlp[Ohm]0 0 4 1.090 2.89E+04 2.7E–12 3.46E–05 7.28E–03 211 3201 3201 –1370 43 4 2.800 2.86E+04 2.7E–12 3.50E–05 7.28E–03 208 1168 1168 –1370 77 4 10.000 2.79E+04 2.7E–12 3.59E–05 7.28E–03 203 318 318 –13732 0 4 1.090 1.18E+04 3.3E–12 8.44E–05 8.91E–03 105 3809 3809 –11232 43 4 2.800 1.18E+04 3.3E–12 8.49E–05 8.91E–03 105 1240 1240 –11232 77 4 10.000 1.16E+04 3.3E–12 8.58E–05 8.91E–03 104 323 323 –11264 0 4 1.090 7.52E+03 3.9E–12 1.33E–04 1.06E–02 80 4675 4675 –9564 43 4 2.800 7.49E+03 3.9E–12 1.33E–04 1.06E–02 79 1320 1320 –9564 77 4 10.000 7.44E+03 3.9E–12 1.34E–04 1.06E–02 79 328 328 –9596 0 4 1.090 5.24E+03 4.5E–12 1.91E–04 1.23E–02 64 6398 5245 –8196 43 4 2.800 5.23E+03 4.5E–12 1.91E–04 1.23E–02 64 1428 1428 –8196 77 4 10.000 5.21E+03 4.5E–12 1.92E–04 1.23E-02 64 334 334 –81128 0 4 1.090 3.82E+03 5.1E–12 2.62E–04 1.40E–02 54 11731 3821 –71128 43 4 2.800 3.81E+03 5.1E–12 2.62E–04 1.40E–02 54 1590 1590 –71128 77 4 10.000 3.80E+03 5.1E–12 2.63E–04 1.40E–02 53 342 342 –71160 0 4 1.090 3.04E+03 5.8E–12 3.28E–04 1.58E–02 48 54119 3044 –63Notes:1. The second-to-last row describes the case of cap. bank state 128 with boosted maximum power setting which is the targetedoperation setting with this 434 MHz antenna.2. The optimal load impedance parallel model columns show the calculated element values of the parallel equivalent of theoptimum differential termination impedance for the Si4010 output pins.12 Rev. 0.1

AN369Simulated impedance:The simulated antenna impedance with 4.90 pF at the input is shown in Figure 11. The resonance is near 434 MHz(the slight detuning will be compensated by the automatic tuning).Also the real part of the antenna impedance together with the 5.1 pF cap at the input is shown in Figure 12. Theresidual impedance at resonance is ~425 .Note: Accurate tuning of the real impedance part is difficult due to the strong tapping ratio.Figure 11. S11 Real/Img Resonance at 434 MHz, Cload=5.2 pFRev. 0.1 13

AN369Figure 12. Real Impedance of the Antenna @ 434 MHz4. Matching Balun Design for Si4010 with 50 Single-Ended OutputThe Si4010 transmitter can be used with single-ended 50 antennas (monopole, spiral, ILA, IFA etc.) as well if anexternal matching balun is used between the high impedance differential output of the chip and the 50 singleendedload. The matching balun performs four important tasks with minimal insertion loss:• Provides the optimum termination impedance (see Section “2. High Impedance Differential Power Amplifier” ) tothe differential output of the chip if the single-ended port of the balun is terminated by 50 . As in this case thedifferential output is not terminated in the complex conjugate way. (See the "voltage limited" operation mode inSection “2. High Impedance Differential Power Amplifier” ; the S11 parameter will not provide good return lossat the 50 port, but the matching will provide the possible highest power.)• Makes the balun function, i.e. adds the two differential outputs in-phase, with equal magnitudes.• Suppresses the common mode even-order harmonics.• Makes an additional suppression on the 2nd harmonic by using a 2nd harmonic trap.Unfortunately, as the Si4010 outputs are working with the termination (here, the differential port of the balun) withhigh Q parallel resonance, optimum wideband solution is very difficult or even impossible to design.If the power requirement is significantly relaxed, a possible wideband solution can be to use a coil-type balun. Inthis case, however, the termination impedance is far from optimum and the power is lower (i.e, this is acompromise).In this application note narrowband, nearly optimum matching baluns are described, which use 0402SMDelements with different element values at the different bands.In the design the losses and parasitic of the SMD elements and the pcb traces are compensated, and due to this itis strongly recommended to use the pcb layout proposed by Silicon Labs.Also to comply with regulatory standards (ETSI, FCC etc.), additional 3rd order filtering is necessary at the singleendedside.14 Rev. 0.1

AN3694.1. Matching Baluns for Si4010_B1 with SOIC and MSOP PackageThis section is useful for readers who do not intend to deeply understand the fundamental operation of the high Qmatching balun, but rather are concerned with quickly obtaining a set of component values for a given desiredfrequency of operation.The presented baluns shows nearly the optimum impedances listed in Table 1 and Table 2 on page 3 for theSi4010 outputs if the single-ended port is terminated by 50 .Also in the balun function the magnitude mismatch is lower than 6% (typically 2-3%) and the phase error is lowerthan 5 degrees (typically 2 degrees). Fortunately, these levels of residual losses have minimal effect (~0.1 dB) onthe operation of the matching balun. The main sources of these mismatches are the discrete steps of the availableSMD components.In the design, the losses and parasitic of the SMD elements and the pcb traces are compensated. Due to this it isstrongly recommended to use the pcb layout designs proposed by Silicon Labs around the Si4010 outputs, V DD ,grounding, etc.The loss of the matching is ~0.5 dB at low bands and ~1 dB at high bands. The loss values of the filters aretypically 0.2 dB at the operation frequency. These loss values are achieved by using high Q wirewound inductor(Coicraft 0402HP series) and capacitor (Murata GRM155 series) types. Usage of lower Q elements (e.g.,multilayer inductors) can cause 0.5…1dB additional loss.The presented baluns comply with regulatory standards, and for this they comprise the filters at their 50 side.4.1.1. 434 MHz SOIC Matching BalunThe schematic of the 434 MHz balun with element values for the SOIC packaged Si4010 is shown in Figure 12.This matching is ETSI-compliant. The Si4010 tunes the internal cap. bank to state 19 automatically with thismatching.Figure 13. Si4010 SOIC Matching Network for 434 MHzThe top layer of the Silicon Labs testcard is shown in Figure 13. It is recommended to copy and use the RF layoutaround the chip as it is. The gerbers of the board can be found on the Silicon Labs website.Rev. 0.1 15

AN369Unfortunately, around the 5th harmonic frequency the 50 balun core output (at the C1 capacitor, before the filter)has a very low impedance and thus the filter could not attenuate properly. To avoid this, a 8.5 mm long50 coplanar transmission line is introduced between the C1 capacitor and the filter. This line transforms theimpedance at the 5th harmonic to higher values. In this way, significant reduction of the 5th harmonic level isachieved.Figure 14. Top Layout of the SI Testcard with SOIC Packaged Si4010The measured spectrum by a 50 spectrum analyzer up to 3.6 GHz is shown in Figure 15. The realized matchinghas ETSI compliance in this conductive measurement. Assuming 0 dB gain antenna, the compliance will beobserved in radiated measurements as well.The fundamental power is ~+9.6 dBm. Assuming 1.0 dB loss for the balun and 0.1 dB loss for the filter, the powerdelivered to the differential port of the balun is ~+10.7 dBm. That is, the power goes into a properly designeddifferential antenna input without external matching elements.Figure 15. Measure Output Spectrum Up to 3.6 GHz16 Rev. 0.1

AN3694.1.2. 868MHz SOIC Matching BalunThe schematic of the 868MHz balun with element values for the SOIC packaged Si4010 is shown in Figure 16.This matching is ETSI-compliant. The Si4010 tunes the internal cap. bank to state 17 automatically with thismatching.Figure 16. Si4010 Rev B SOIC Matching Network for 868 MHzThe top layer of the Silicon Labs testcard is shown in Figure 17. It is recommended to copy and use the RF layoutaround the chip as it is. The gerbers of the board can be found on the Silicon Labs website.Unfortunately, around the 3th harmonic frequency the 50 balun core output (at the C1 capacitor, before the filter)has a very low impedance and thus the filter could not attenuate properly. To avoid this a 8.5 mm long50 coplanar transmission line is introduced between the C1 capacitor and the filter. This line transforms theimpedance at the 3th harmonic to higher values. In this way, significant reduction of the 3rd harmonic level isachieved.Rev. 0.1 17

AN369Figure 17. Top Layout of the SI Testcard with SOIC Packaged Si4010The measured spectrum by a 50 spectrum analyzer up to 3.6 GHz is shown in Figure 18. The realized matchinghas ETSI compliance in this conductive measurement. Assuming 0 dB gain antenna the compliance reserved inradiated measurements as well.The fundamental power is ~+8.4 dBm. Assuming .08 dB loss for the balun and 0.15 dB loss for the filter, the powerdelivered to the differential port of the balun is ~+9.4 dBm. That is, the power goes into a properly designeddifferential antenna input without external matching elements.Figure 18. Measured Spectrum Up to 3.6 GHz18 Rev. 0.1

AN3694.1.3. 434 MHz MSOP Matching BalunThe schematic of the 434 MHz balun with element values for the MSOP packaged Si4010 is shown in Figure 19.This matching is ETSI-compliant. The Si4010 tunes the internal cap. bank to state 19 automatically with thismatching.The top layer of the Silicon Labs testcard is shown in Figure 20. It is recommended to copy and use the RF layoutaround the chip as it is. The gerbers of the board can be found on the Silicon Labs website.Figure 19. Si4010 MSOP Matching Network for 434 MHzRev. 0.1 19

AN369Figure 20. Top Layout of the SL Testcard with MSOP Packaged Si4010The measured spectrum by a 50 spectrum analyzer up to 3.6 GHz is shown in Figure 21. The realized matchinghas ETSI compliance in this conductive measurement. Assuming 0 dB gain antenna the compliance reserved inradiated measurements as well.The fundamental power is ~+9.7 dBm. Assuming 1.0 dB loss for the balun and 0.1 dB loss for the filter, the powerdelivered to the differential port of the balun is ~+10.8 dBm. That is, the power goes into a properly designeddifferential antenna input without external matching elements.20 Rev. 0.1

AN369Figure 21. Measured Spectrum Up to 3.6 GHz4.1.4. 868 MHz MSOP Matching BalunThe schematic of the 868 MHz balun with element values for the MSOP-packaged Si4010 is shown in Figure 22.This matching is ETSI-compliant. The Si4010 tunes the internal cap. bank to state 9 automatically with thismatching.The top layer of the Silicon Labs testcard is shown in Figure 23. It is recommended to copy and use theRF layout around the chip as it is. The gerbers of the board can be found on the Silicon Labs website.Rev. 0.1 21

AN369Figure 22. Si4010 MSOP Matching Network for 868 MHzFigure 23. Top Layout of the SI Testcard with MSOP Packaged Si4010The measured spectrum by a 50 spectrum analyzer up to 3.6 GHz is shown in Figure 24. The realized matchinghas ETSI compliance in this conductive measurement. Assuming 0 dB gain antenna the compliance reserved inradiated measurements as well.The fundamental power is ~+8.9 dBm. Assuming 0.8 dB loss for the balun and 0.15 dB loss for the filter, the powerdelivered to the differential port of the balun is ~+9.85 dBm. That is, the power goes into a properly designeddifferential antenna input without external matching elements.22 Rev. 0.1

AN3694.2. High Q Discrete Matching BalunsFigure 24. Measured Spectrum Up to 3.6 GHzThis section is useful for readers who intend to understand the fundamental operation of the high Q discretematching baluns.The designed baluns shows nearly the optimum impedances listed in Table 1 and Table 2 on page 3 for the Si4010outputs if the single-ended port is terminated by 50 .As mentioned previously, the two main tasks the matching balun performs with minimal insertion loss are:• Shows the optimum termination impedance (see Section “2. High Impedance Differential Power Amplifier” ) tothe differential output of the chip if the single-ended port of the balun is terminated by 50 .• Makes the balun function, i.e., adds the two differential outputs in-phase, with equal magnitudes.Also it should suppress the even harmonics, and it has an additional function to trap and remove the 2nd harmonic.The first two functions can be satisfied with optimum solution in narrowband only. This section shows the designhints of narrowband discrete baluns.4.2.1. Design ProcedureThe basic structure which theoretically satisfies the two main matching balun function has four external elementsas shown in Figure 25. C_TX in the figure is the same equivalent capacitance which is denoted by C TX in Figure 1on page 2.Rev. 0.1 23

AN369Figure 25. 4-Element Matching Circuit SchematicIn loss free, in the ideal scenario, the element values of the 4 element matching can be derived analytically. Adetailed discussion of this analytical solution can be found in Silicon Labs Application Note “AN427: EZRadioPROSi433x & Si443x RX LNA Matching.” Although that applies to the results for a high impedance Rx matching withparasitic capacitance, the method is applicable to high impedance transmitters as well. The only difference is thatin the formulas the parallel equivalent resistance of the optimum termination impedance (R AP in Table 1 and Table2 in Section “2. High Impedance Differential Power Amplifier” ) and the transmitter equivalent capacitance (C_TX inFigure 25, which is also given in the 6th column of Tables 1 and 2) has to be used.As a result, the following equations are introduced here without proof or further discussion:50 RL R2 = -------------------------------- PA RFEquation 3.1C R1 = -----------------------------2 RF L R2Equation 4.C R2 = 2C R2Equation 5.1L PA = ----------------------------- 2 C RF TXEquation 6.L M = 2L R2Equation 7.LL PA L MR1 = -----------------------L PA + L MEquation 8.24 Rev. 0.1

AN3691. Calculate the values e.g. for the 434MHz MSOP case where R AP =530 and the CTX=2.7 pF at internal cap.bank state of 19 (Table 1 in Section “2. High Impedance Differential Power Amplifier” ). The ideal matchingelement values are: LR1=35.4 nH, CR1=2.25 pF, LR2=58.5 nH, CR2=4.5 pF.Note: 1.5 nH was added for the through-hole via inductance and LR1 was reduced accordingly.2. Split LR1 into two halves to make connection for the Vdd supply choke inductor and the 2nd harmonic trapcapacitor. The schematic of the matching with split LR1 (LR11 & LR12) and with choke inductor is shown inFigure 26.Figure 26. 6-Element Matching Circuit SchematicThe value of LCHOKE should be chosen such that it provides high impedance not only at the fundamentaloperating frequency but also at the first few harmonic frequencies as well. The inductance value should not be solarge as to already be at (or past) parallel self-resonance at the desired operating frequency. The exactinductance value is not critical; however, Silicon Labs recommends the following range of inductance values(assuming 0402-size or 0603-size inductors) as a function of the desired operating frequency:•315 & 434 MHz: approximately 220..270 nH•868 & 915 MHz: approximately 120 nHThe value of the 2nd harmonic trap capacitor (Ctr_2nd) is chosen such that it is resonating in series with LR11and LR12 at the 2nd harmonic frequency. As LR11 and LR12 are parallel connected for the common mode 2ndharmonic, the resulting inductance for the 2nd harmonic is LR11/2=LR12/2=LR1/4. This has to be in resonancewith Ctr_2nd at the 2nd harmonic. However, the exact values are strongly influenced by the parasitic and thus itis always tuned at the bench.3. The parasitics and losses of the SMD components and the pcb are included into a simulation where the abovelistedmain balun functions can be checked. Going back to the 434 MHz SOIC example, Figures 27 and 28show the simulated S11 and the balun function (voltage transfer function from the 50 single-ended port to thetwo differential ports) when the R AP and C TX (Table 1) is used as a differential port termination). As one can seeif the differential port of the balun is terminated by the conjugate of the optimum termination impedance, both itsbalun function and matching are very good.4. The balun function is checked when the RAP is replaced by the much higher EPR, i.e., the internal loss of theTX (TX_EPR). That is shown in Figure 29 assuming 20K EPR at cap. bank state 19. The balun functionremained good, only the voltage magnitude increased in the same way at both differential nodes. The S11becomes bad (Figure 30), but this is normal as described in Section “2. High Impedance Differential PowerAmplifier” , in "voltage limited" mode when complex conjugate matching is not used for achieving the maximumpower.Rev. 0.1 25

AN3690.00-10.00-20.00-30.00-40.00300.00M 375.00M 450.00M 525.00M 600.00MmagdB(S(1,1))Fi 28Figure 27. Simulated S11 of the SOIC Example2.50180.0PHASE1.8890.001.250.000.63-90.000.00-180.0300.00M 375.00M 450.00M 525.00M 600.00MMag(vac(o1))Mag(vac(o2))Pha(vac(o1))Pha(vac(o2))Fi 29Figure 28. Voltage Transfer Function26 Rev. 0.1

AN3694.00180.0PHASE3.0090.002.000.001.00-90.000.00-180.0300.00M 375.00M 450.00M 525.00M 600.00MMag(vac(o1))Mag(vac(o2))Pha(vac(o1))Pha(vac(o2))Figure 30Figure 29. Voltage Transfer Function with Higher EPR0.00-1.00-2.00-3.00-4.00300.00M 375.00M 450.00M 525.00M 600.00MmagdB(S(1,1))Figure 31Figure 30. S11 with Higher EPRRev. 0.1 27

AN369CONTACT INFORMATIONSilicon Laboratories Inc.400 West Cesar ChavezAustin, TX 78701Please visit the Silicon Labs Technical Support web page:https://www.silabs.com/support/pages/contacttechnicalsupport.aspxand register to submit a technical support request.The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting fromthe use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed featuresor parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representationor guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequentialor incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended tosupport or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personalinjury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application,Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.28 Rev. 0.1