XN12L612 32-bit MCU Family ARM Cortex-M0 Core, 88K Flash and ...

XN12L61232-bit MCU FamilyARM Cortex-M0 Core, 88K Flash and 16K RAMUSER MANUAL1 Introduction ........................................................................................................................................................ 181.1 General ...................................................................................................................................................... 181.2 Features .................................................................................................................................................... 182 Package and Pin Assignment ............................................................................................................................ 202.1 General Description ................................................................................................................................... 202.2 LQFP 64 Package ..................................................................................................................................... 202.3 Pin Description .......................................................................................................................................... 212.4 Peripheral Pin Group ................................................................................................................................. 263 System Block Diagram ....................................................................................................................................... 294 System Description ............................................................................................................................................ 304.1 ARM Cortex-M0 Core ............................................................................................................................ 304.2 Memory Map .............................................................................................................................................. 314.3 Cortex-M0 Core System Control Block .................................................................................................. 364.3.1 General Description ................................................................................................................. 364.3.2 CPUID Register........................................................................................................................ 364.3.3 Interrupt Control and State Register ........................................................................................ 364.3.4 Application Interrupt and Reset Control Register .................................................................... 384.3.5 System Control Register .......................................................................................................... 384.3.6 Configuration and Control Register.......................................................................................... 394.3.7 System Handle Priority Registers ............................................................................................ 394.4 Nested Vectored Interrupt Controller (NVIC) ............................................................................................ 404.4.1 NVIC Description...................................................................................................................... 40© 2010 Xinnova Technology Ltd. All rights reserved. The Xinnova logo is registered trademarks of Xinnova Technology Ltd. This Datasheet may berevised by subsequent versions or modifications without prior notice.

XN12L6124.4.2 Nested Vectored Interrupt Controller Register List .................................................................. 424.4.3 Interrupt Set-enable Register ................................................................................................... 434.4.4 Interrupt Clear-enable Register ................................................................................................ 434.4.5 Interrupt Set-pending Register ................................................................................................. 434.4.6 Interrupt Clear-pending Register.............................................................................................. 444.4.7 Interrupt Priority Registers ....................................................................................................... 444.4.7.1 NMI Interrupt Source Configuration Register .................................................................. 454.5 System Tick Timer ..................................................................................................................................... 464.5.1 System Timer Control and Status Register ............................................................................. 464.5.2 System Timer Reload Value Register ...................................................................................... 474.5.3 System Timer Current Value Register ..................................................................................... 474.5.4 Usage of System Tick Timer .................................................................................................... 474.6 System Control .......................................................................................................................................... 484.6.1 System Reset ........................................................................................................................... 504.6.1.1 System Memory Remap Register ................................................................................... 514.6.1.2 System Reset Status Register ........................................................................................ 514.6.1.3 PIO State at System Reset ............................................................................................. 524.6.1.4 Software Reset ................................................................................................................ 524.6.1.5 POR ................................................................................................................................. 524.6.1.6 BOD ................................................................................................................................. 524.6.2 Clock control ............................................................................................................................ 534.6.2.1 General description ......................................................................................................... 534.6.2.2 System Oscillator Control ................................................................................................ 544.6.2.3 Watchdog Oscillator Control ........................................................................................... 542 www.xinnovatech.com

XN12L6124.6.2.4 Internal Resonant Crystal Control ................................................................................... 554.6.2.5 System PLL ..................................................................................................................... 554.6.2.6 Main Clock ....................................................................................................................... 584.6.2.7 System AHB Clock Control ............................................................................................. 594.6.2.8 UART Clock Control ........................................................................................................ 624.6.2.9 CLKOUT Clock Control ................................................................................................... 624.6.2.10 IOCONFIG Filter Clock Control ....................................................................................... 634.6.3 Power Management ................................................................................................................. 634.6.3.1 Power Control Register ................................................................................................... 644.6.3.2 General Data Registers 0 to 3 ......................................................................................... 654.6.3.3 WAKEUP and RTC Configuration Register .................................................................... 654.6.3.4 Deep-sleep Configuration Register ................................................................................. 664.6.3.5 Wake-up Configuration Register ..................................................................................... 664.6.3.6 Power-down Configuration Register ............................................................................... 674.6.3.7 Active Mode ..................................................................................................................... 694.6.3.8 Sleep Mode ..................................................................................................................... 694.6.3.9 Deep-sleep Mode ............................................................................................................ 704.6.3.10 Power-down Mode .......................................................................................................... 714.6.4 Deep-sleep Wake Up Control .................................................................................................. 734.6.4.1 Deep-sleep Wake Up Control Register ........................................................................... 734.6.4.2 Deep-sleep Wake Up Signal Enable Register ................................................................ 754.6.4.3 Deep-sleep Wake Up Signal Reset Register .................................................................. 764.6.4.4 Deep-sleep Wake Up Signal Status Register ................................................................. 774.6.5 Miscellaneous .......................................................................................................................... 78www.xinnovatech.com 3

XN12L6124.6.5.1 Peripheral Reset Control Register .................................................................................. 784.7 I/O configuration ........................................................................................................................................ 794.7.1 General Description of IOCON Register .................................................................................. 804.7.1.1 Pin Function .................................................................................................................... 814.7.1.2 Pin Mode ......................................................................................................................... 814.7.1.3 Pin Drive .......................................................................................................................... 814.7.1.4 Open-drain Mode ............................................................................................................ 814.7.1.5 A/D-mode ........................................................................................................................ 814.7.1.6 TWS Mode (I2C Compatible) .......................................................................................... 824.7.1.7 Programmable Glitch Filter.............................................................................................. 824.7.2 IOCON Register List ................................................................................................................ 824.7.2.1 PIO0_0 IOCON Register ................................................................................................. 854.7.2.2 PIO0_1 IOCON Register ................................................................................................. 854.7.2.3 PIO0_2 IOCON Register ................................................................................................. 864.7.2.4 PIO0_3 IOCON Register ................................................................................................. 874.7.2.5 PIO0_4 IOCON Register ................................................................................................. 884.7.2.6 PIO0_5 IOCON Register ................................................................................................. 894.7.2.7 PIO0_6 IOCON Register ................................................................................................. 904.7.2.8 PIO0_7 IOCON Register ................................................................................................. 914.7.2.9 PIO0_8 IOCON Register ................................................................................................. 924.7.2.10 PIO0_9 IOCON Register ................................................................................................. 934.7.2.11 PIO0_10 IOCON Register ............................................................................................... 944.7.2.12 PIO0_11 IOCON Register ............................................................................................... 954.7.2.13 PIO0_12 IOCON Register ............................................................................................... 964 www.xinnovatech.com

XN12L6124.7.2.14 PIO0_13 IOCON Register ............................................................................................... 984.7.2.15 PIO0_14 IOCON Register ............................................................................................... 994.7.2.16 PIO0_15 IOCON Register ............................................................................................. 1004.7.2.17 PIO0_16 IOCON Register ............................................................................................. 1014.7.2.18 PIO0_17 IOCON Register ............................................................................................. 1024.7.2.19 PIO0_18 IOCON Register ............................................................................................. 1034.7.2.20 PIO0_19 IOCON Register ............................................................................................. 1044.7.2.21 PIO0_20 IOCON Register ............................................................................................. 1054.7.2.22 PIO0_21 IOCON Register ............................................................................................. 1064.7.2.23 PIO0_22 IOCON Register ............................................................................................. 1074.7.2.24 PIO0_23 IOCON Register ............................................................................................. 1084.7.2.25 PIO0_24 IOCON Register ............................................................................................. 1094.7.2.26 PIO0_25 IOCON Register ............................................................................................. 1104.7.2.27 PIO0_26 IOCON Register ............................................................................................. 1114.7.2.28 PIO0_27 IOCON Register ............................................................................................. 1124.7.2.29 PIO0_28 IOCON Register ............................................................................................. 1134.7.2.30 PIO0_29 IOCON Register ............................................................................................. 1144.7.2.31 PIO0_30 IOCON Register ............................................................................................. 1154.7.2.32 PIO0_31 IOCON Register ............................................................................................. 1164.7.2.33 PIO1_0 IOCON Register ............................................................................................... 1174.7.2.34 PIO1_1 IOCON Register ............................................................................................... 1184.7.2.35 PIO1_2 IOCON Register ............................................................................................... 1194.7.2.36 PIO1_3 IOCON Register ............................................................................................... 1204.7.2.37 PIO1_4 IOCON Register ............................................................................................... 121www.xinnovatech.com 5

XN12L6124.7.2.38 PIO1_5 IOCON Register ............................................................................................... 1224.7.2.39 PIO1_6 IOCON Register ............................................................................................... 1234.7.2.40 PIO2_0 IOCON Register ............................................................................................... 1244.7.2.41 PIO2_1 IOCON Register ............................................................................................... 1254.7.2.42 PIO2_2 IOCON Register ............................................................................................... 1264.7.2.43 PIO2_3 IOCON Register ............................................................................................... 1274.7.2.44 PIO2_4 IOCON Register ............................................................................................... 1284.7.2.45 PIO2_5 IOCON Register ............................................................................................... 1294.7.2.46 PIO2_6 IOCON Register ............................................................................................... 1304.7.2.47 PIO2_7 IOCON Register ............................................................................................... 1314.7.2.48 PIO2_8 IOCON Register ............................................................................................... 1324.7.2.49 PIO2_9 IOCON Register .............................................................................................. 1334.7.2.50 PIO2_10 IOCON Register ............................................................................................ 1344.7.2.51 PIO2_11 IOCON Register ............................................................................................ 1354.7.2.52 PIO2_12 IOCON Register ............................................................................................. 1364.7.2.53 PIO2_13 IOCON Register ............................................................................................. 1374.7.2.54 PIO2_14 IOCON Register ............................................................................................. 1384.7.2.55 PIO2_15 IOCON Register ............................................................................................. 1395 GPIO ................................................................................................................................................................ 1415.1 General Description ................................................................................................................................. 1415.2 Pin Description ........................................................................................................................................ 1415.3 Control Register Description ................................................................................................................... 1415.3.1 GPIO Mask Register .............................................................................................................. 1425.3.2 GPIO Pin Value Register ....................................................................................................... 1426 www.xinnovatech.com

XN12L6125.3.3 GPIO Pin Output Register ...................................................................................................... 1435.3.4 GPIO Pin Output Set Register ............................................................................................... 1435.3.5 GPIO Pin Output Clear Register ............................................................................................ 1435.3.6 GPIO NOT Register ............................................................................................................... 1445.3.7 GPIO Data Direction Register ................................................................................................ 1445.3.8 GPIO Interrupt Sense Register .............................................................................................. 1445.3.9 GPIO Interrupt Both Edges Sense Register .......................................................................... 1445.3.10 GPIO Interrupt Event Register ............................................................................................... 1455.3.11 GPIO Interrupt Mask Register ................................................................................................ 1455.3.12 GPIO Raw Interrupt Status Register ...................................................................................... 1455.3.13 GPIO Masked Interrupt Status Register ................................................................................ 1455.3.14 GPIO Interrupt Clear Register ................................................................................................ 1466 16-Bit Timer/Counter ........................................................................................................................................ 1476.1 General Description ................................................................................................................................. 1476.2 Pin Description ........................................................................................................................................ 1496.3 Register Description ................................................................................................................................ 1496.3.1 Interrupt Register ................................................................................................................... 1506.3.2 Timer Control Register ........................................................................................................... 1516.3.3 Timer Counter Register .......................................................................................................... 1516.3.4 Prescale Register ................................................................................................................... 1516.3.5 Prescale Counter Register ..................................................................................................... 1516.3.6 Match Control Register .......................................................................................................... 1526.3.7 Match Registers ..................................................................................................................... 1536.3.8 Capture Control Register ....................................................................................................... 153www.xinnovatech.com 7

XN12L6126.3.9 Capture Registers .................................................................................................................. 1556.3.10 External Match Register ......................................................................................................... 1556.3.11 Count Control Register .......................................................................................................... 1576.3.11.1 Edge Count Mode ......................................................................................................... 1596.3.11.2 Quadrature Count Mode................................................................................................ 1596.3.11.3 Triggered Count Mode .................................................................................................. 1596.3.11.4 Signed Count Mode ....................................................................................................... 1596.3.11.5 Gated Count Mode ........................................................................................................ 1606.3.12 Timer PWM Control register .................................................................................................. 1606.3.12.1 Rules for Single Edge Controlled PWM Outputs .......................................................... 1607 32-Bit Timer/Counter ........................................................................................................................................ 1627.1 General Description ................................................................................................................................. 1627.2 Pin Description ........................................................................................................................................ 1637.3 Register Description ................................................................................................................................ 1647.3.1 Interrupt Register ................................................................................................................... 1657.3.2 Timer Control Register ........................................................................................................... 1657.3.3 Timer Counter Register .......................................................................................................... 1667.3.4 Prescale Register ................................................................................................................... 1667.3.5 Prescale Counter Register ..................................................................................................... 1667.3.6 Match Control Register .......................................................................................................... 1667.3.7 Match Registers ..................................................................................................................... 1687.3.8 Capture Control Register ....................................................................................................... 1687.3.9 Capture Register .................................................................................................................... 1697.3.10 External Match Register ......................................................................................................... 1698 www.xinnovatech.com

XN12L6127.3.11 Count Control Register .......................................................................................................... 1717.3.12 PWM Control Register ........................................................................................................... 1737.3.13 Rules for Single Edge Controlled PWM Outputs ................................................................... 1748 Watchdog Timer (WDT) ................................................................................................................................... 1768.1 General Description ................................................................................................................................. 1768.2 Register Description ................................................................................................................................ 1778.3 Watchdog Mode Register ........................................................................................................................ 1778.3.1 Watchdog Timer Constant Register ....................................................................................... 1798.3.2 Watchdog Feed Register ....................................................................................................... 1798.3.3 Watchdog Timer Value Register ............................................................................................ 1808.3.4 Watchdog Timer Clock Source Selection Register ................................................................ 1808.3.5 Watchdog Timer Warning Interrupt Register ......................................................................... 1818.3.6 Watchdog Timer Window Register ........................................................................................ 1818.4 Watchdog Timer Clock and Power Control ............................................................................................. 1818.5 Watchdog Lock Feature .......................................................................................................................... 1828.6 Watchdog Timing Examples .................................................................................................................... 1829 xDSP ................................................................................................................................................................ 1849.1 General Description ................................................................................................................................. 1849.2 xDSP Interface Register Description ....................................................................................................... 18415.1.1 CRC Mode Register ............................................................................................................... 18515.1.2 CRC Seed Register ............................................................................................................... 18515.1.3 CRC Checksum Register ....................................................................................................... 18515.1.4 CRC Data Register ................................................................................................................ 18615.1.5 Dividend Register ................................................................................................................... 186www.xinnovatech.com 9

XN12L61215.1.6 Divisor Register ...................................................................................................................... 18615.1.7 Quotient Register ................................................................................................................... 18615.1.8 CORDIC Control Register ...................................................................................................... 18615.1.9 CORDIC X Register ............................................................................................................... 18615.1.10 CORDIC Y Register ............................................................................................................... 18715.1.11 CORDIC Phase Register ....................................................................................................... 18715.1.12 CORDIC Operation X Result Register ................................................................................... 18715.1.13 CORDIC Operation Y Result Register ................................................................................... 18715.1.14 CORDIC Operation Phase Result Register ........................................................................... 1879.3 Functions Description .............................................................................................................................. 18715.1.15 CRC Calculation..................................................................................................................... 18715.1.16 32-Bit Divider .......................................................................................................................... 18915.1.17 Sin/Cos/Arctan ....................................................................................................................... 18910 UART................................................................................................................................................................ 19110.1 General Description ........................................................................................................................ 19110.2 Pin Description ................................................................................................................................ 19210.3 UART Register Description............................................................................................................. 19210.3.1 UART Receiver Buffer Register ............................................................................................. 19210.3.2 UART Transmitter Holding Register ...................................................................................... 19310.3.3 UART State Register ............................................................................................................. 19310.3.4 UART Control Register .......................................................................................................... 19310.3.5 UART Interrupt Status Register ............................................................................................. 19410.3.6 UART Baudrate Divider Register ........................................................................................... 19510.4 Operation Description ..................................................................................................................... 19510 www.xinnovatech.com

XN12L61210.4.1 UART Communication Convention ........................................................................................ 19510.4.2 IrDA Function ......................................................................................................................... 19611 SPI .................................................................................................................................................................... 19711.1 General Description ........................................................................................................................ 19711.2 Pin Description ................................................................................................................................ 19711.3 Register Description ....................................................................................................................... 19811.3.1 SPI Control Register 0 ........................................................................................................... 19811.3.2 SPI Control Register 1 ........................................................................................................... 19911.3.3 SPI Data Register .................................................................................................................. 20011.3.4 SPI Status Register ................................................................................................................ 20011.3.5 SPI Clock Prescale Register .................................................................................................. 20111.3.6 SPI Interrupt Mask Set/Clear Register ................................................................................... 20111.3.7 SPI Raw Interrupt Status Register ......................................................................................... 20111.3.8 SPI Masked Interrupt Status Register ................................................................................... 20211.3.9 SPI Interrupt Clear Register ................................................................................................... 20211.3.10 SPI DMA Control Register ..................................................................................................... 20211.4 Operation ........................................................................................................................................ 20311.4.1 SPI Frame Format.................................................................................................................. 20311.4.2 SSI Frame Format.................................................................................................................. 20712 TWS ................................................................................................................................................................. 20912.1 General Description ........................................................................................................................ 20912.2 Pin Description ................................................................................................................................ 20912.3 Register Description ....................................................................................................................... 21012.3.1 TWS Control Set register ....................................................................................................... 211www.xinnovatech.com 11

XN12L61212.3.2 TWS Status Register ............................................................................................................. 21212.3.3 TWS Data Register ................................................................................................................ 21312.3.4 TWS Slave Address Register 0 ............................................................................................. 21312.3.5 TWS HIGH Duty Cycle register .............................................................................................. 21312.3.6 TWS Low Duty Cycle register ................................................................................................ 21312.3.7 TWS Control Clear Register .................................................................................................. 21412.3.8 TWS Slave Address Registers ............................................................................................... 21412.3.9 TWS Data Buffer Register ..................................................................................................... 21512.3.10 TWS Mask Registers ............................................................................................................. 21512.4 TWS Operation ............................................................................................................................... 21512.4.1 Master Transmitter Mode ....................................................................................................... 21512.4.2 Master Receiver Mode ........................................................................................................... 21712.4.3 Slave Receiver Mode ............................................................................................................. 21912.4.4 Slave Transmitter Mode ......................................................................................................... 22112.4.5 Detailed State Tables ............................................................................................................. 22212.4.6 TWS State Service Routines ................................................................................................. 22512.4.6.1 Initialization Routine ...................................................................................................... 22512.4.6.2 Start Master Transmit Function ..................................................................................... 22512.4.6.3 Start Master Receive Function ...................................................................................... 22612.4.6.4 TWS Interrupt Routine ................................................................................................... 22612.4.6.5 Non Mode Specific States ............................................................................................. 22612.4.6.6 Master Transmitter States ............................................................................................. 22712.4.6.7 Master Receive States .................................................................................................. 22812.4.6.8 Slave Receiver States ................................................................................................... 22912 www.xinnovatech.com

XN12L61212.4.6.9 Slave Transmitter States ............................................................................................... 23013 RTC .................................................................................................................................................................. 23113.1 General Description ........................................................................................................................ 23113.2 Pin Description ................................................................................................................................ 23113.3 RTC Register Description ............................................................................................................... 23113.3.1 RTC Data Register ................................................................................................................. 23113.3.2 RTC Match Register .............................................................................................................. 23113.3.3 RTC Load Register ................................................................................................................ 23213.3.4 RTC Control Register ............................................................................................................. 23213.3.5 RTC Interrupt Control Set/Clear Register .............................................................................. 23213.3.6 RTC Interrupt Status Register ................................................................................................ 23213.3.7 RTC Masked Interrupt Status Register .................................................................................. 23313.3.8 RTC Interrupt Clear Register ................................................................................................. 23313.4 Functional Description .................................................................................................................... 23314 ADC/DAC and On-chip Temperature Sensor .................................................................................................. 23414.1 General Description ........................................................................................................................ 23414.2 Pin description ................................................................................................................................ 23414.3 Register Description ....................................................................................................................... 23414.3.1 ADC Control Register ............................................................................................................ 23514.3.2 ADC Global Data Register ..................................................................................................... 23614.3.3 ADC Interrupt Enable Register .............................................................................................. 23714.3.4 ADC Data Registers ............................................................................................................... 23714.3.5 ADC Interrupt Status Register ............................................................................................... 23814.3.6 High Limit Control Register .................................................................................................... 238www.xinnovatech.com 13

XN12L61214.3.7 Low Limit Control Register ..................................................................................................... 23914.3.8 Software Sample Control Register......................................................................................... 23914.3.9 D/A Control Register .............................................................................................................. 24014.3.10 D/A Data Register .................................................................................................................. 24014.4 Operation ........................................................................................................................................ 24114.4.1 Select ADC Converter for Each AD Input Channel ................................................................ 24114.4.2 ADC Hardware-Triggered Conversion ................................................................................... 24114.4.3 Interrupts ................................................................................................................................ 24114.4.4 ADC DMA Control .................................................................................................................. 24114.4.5 DAC DMA Control .................................................................................................................. 24114.4.6 On-chip Temperature Sensor ................................................................................................ 24215 Comparator ...................................................................................................................................................... 24415.1 General Description ........................................................................................................................ 24415.2 Pin Description ................................................................................................................................ 24515.3 Register Description ....................................................................................................................... 24515.3.1 Comparator Control Register ................................................................................................. 24515.3.2 Voltage Ladder Register ........................................................................................................ 24715.3.3 Interrupt Status Register ........................................................................................................ 24715.4 Functional Description .................................................................................................................... 24815.4.1 Input Multiplexer ..................................................................................................................... 24815.4.2 Interrupts ................................................................................................................................ 24915.4.3 Comparator Outputs .............................................................................................................. 24916 DMA ................................................................................................................................................................. 25016.1 General Description ........................................................................................................................ 25014 www.xinnovatech.com

XN12L61216.2 Operations ...................................................................................................................................... 25016.3 Memory Regions Accessible By the Micro DMA Controller ........................................................... 25116.3.1 DMA System Connections ..................................................................................................... 25116.4 Clocking and Power Control ........................................................................................................... 25216.4.1 DMA Status Register ............................................................................................................. 25316.4.2 DMA Configuration Register .................................................................................................. 25316.4.3 Channel Control Base Pointer Register ................................................................................. 25416.4.4 Channel Wait on Request Status Register ............................................................................ 25416.4.5 Channel Software Request Register...................................................................................... 25416.4.6 Channel Useburst Set Register ............................................................................................. 25416.4.7 Channel Useburst Clear Register .......................................................................................... 25516.4.8 Channel Request Mask Set Register ..................................................................................... 25516.4.9 Channel Request Mask Clear Register ................................................................................. 25616.5 Channel Enable Set Register ......................................................................................................... 25616.5.1 Channel Enable Clear Register ............................................................................................. 25716.5.2 Channel Priority Set Register ................................................................................................. 25716.5.3 Channel Priority Clear Register ............................................................................................. 25816.5.4 Channel DMA Interrupt Status Register ................................................................................ 25816.5.5 Channel DMA Interrupt Enable Register ............................................................................... 25816.6 Functional Description .................................................................................................................... 25916.6.1 DMA Control Signals .............................................................................................................. 25916.6.2 DMA Arbitration ...................................................................................................................... 25916.6.3 DMA Priority ........................................................................................................................... 25916.6.4 DMA Cycle Types .................................................................................................................. 260www.xinnovatech.com 15

XN12L61217.4.3.8 Run Specific Address Code .......................................................................................... 27317.4.3.9 Password Verification .................................................................................................... 27317.4.3.10 Set New Password ........................................................................................................ 27417.4.3.11 Set B Boundary ............................................................................................................. 27417.4.3.12 Password Status ........................................................................................................... 27417.5 IAP Command and Entry Address .................................................................................................. 27518 SWD ................................................................................................................................................................. 27818.1 General Description ........................................................................................................................ 27818.2 Pin Description ................................................................................................................................ 27818.3 Debug Operation ............................................................................................................................ 27819 Revision History ............................................................................................................................................... 279www.xinnovatech.com 17

XN12L6121 Introduction1.1 GeneralThe XN12L612 is Xinnova’s 32-bit ARM Cortex-M0 core plus xDSP coprocessor high performance microcontroller. Itfocus on high end application in industrial and home automation.XN12L612 integrates the rich peripheral and features for user’s options:Three 12-bit ADC converters support up 8 channels AD input; two comparators ; on-chip temperature sensor; four UARTs;one SPI interface; one TWS-bus interface which is compatible I 2 C; a Windowed Watchdog Timer; four general purposetimers; a 32-bit RTC; a 1 % internal oscillator for baud rate generation; and up to 55 General Purpose I/O (GPIO) pins.1.2 Features• High performance ARM + xDSP CPU structure– Integrated ARM Cortex-M0 processor, running at frequencies of up to 100 MHz– Integrated xDSP coprocessor support configurable 32-bit divider, CRC, Sin, Cos and Arctan operations– 88KB on-chip flash memory and 16KB SRAM– DMA controller– Support Serial Wire Debug (SWD)• High security mechanism– Two 128 bits password for two user memory areas– Support application multi-user development without code unveiling– Support user application code protection and security• Built in bootloader– Support flash memory In-System-Program (ISP) and In-Application-Program (IAP)– Support user application code protection and security• Flexible clock generation unit– Crystal oscillator with an operating range of 0.5 MHz to 16 MHz– 20 MHz Internal Resonant Crystal (IRC) oscillator trimmed to 1% accuracy– Integrated Phase Locked Loop (PLL) allows CPU operation up to the maximum CPU rate– Support 32K Real-Time Clock (RTC) timer• Enhanced Timer/Counter– Two 16-bit and two 32-bit timers/counters– Each timer/counter support four match/capture functions– Support Edge count, Gated count, Quadrature count, Trigger count and Signed count mode18 www.xinnovatech.com

XN12L612• Analog peripherals– Two 12-bit ADC support up to 8 channel with 1MHz sample rate– One channel 10-bit DAC, 1MHz converting speed– Two highly flexible analog comparators– On-chip temperature sensor support -40°C to +120°C detection• Rich communication interface and GPIO– Four UARTs with baudrate detection and IrDA supporting– SPI controller with FIFO and multi-protocol capabilities– Two Wire Serial (TWS) interface– Up to 55 General Purpose I/O (GPIO) pins• Power management– Three reduced power modes: Sleep, Deep-sleep, and Power-down– Processor wake-up from Deep-sleep mode via using 12 port pins– Processor wake-up from Deep-power down and Deep-sleep modes via the RTC– Brownout detection(BOD) with two separate thresholds for interrupt and forced reset.– Power-On Reset (POR)– Integrated Power Management Unit (PMU)• Operating Temperature– Industrial (-40°C to +85°C)• Unique device serial number for identification• 3.3 V power supply• 64-pin LQFP packagewww.xinnovatech.com 19

VSSIOVDD(IO)PIO2_11/CT32B1_CAP3/CT32B1_MAT3/RXD1PIO2_10/CT32B1_CAP2/CT32B1_MAT2/TXD1PIO2_9/CT32B1_CAP1/CT32B1_MAT1PIO2_8/CT32B1_CAP0/CT32B1_MAT0RTCXINOUTRTCXINVDD(3V3)VSSPIO1_6/CT16B1_CAP1/CT16B1_MAT1PIO1_5/AD7/CT16B1_CAP0/CT16B1_MAT0PIO1_4/AD6PIO1_3/AD5/WAKEUPPIO1_2/SWDIO/AD4R/PIO1_1/AD3XN12L6122 Package and Pin Assignment2.1 General DescriptionXN12L612 comes in LQFP 64 package. To save package pin, all pins have more than one function except power supply pin.And the pin function is configurable by IOCON register. The default function will be set after system reset.2.2 LQFP 64 PackageXTALINXTALOUTVREF_ADCPIO0_19/ACMP0_I0/CT32B0_CAP1/CT32B0_MAT1PIO0_20/ACMP0_I1/CT32B0_CAP2/CT32B0_MAT2PIO0_21/ACMP0_I2/CT32B0_CAP3/CT32B0_MAT3PIO0_22/ACMP0_I3PIO0_23/ACMP1_I0/CT32B1_CAP0/CT32B1_MAT0PIO0_24/ACMP1_I1/CT32B1_CAP1/CT32B1_MAT1SWDIO/ACMP1_I2/CT32B1_CAP2/CT32B1_MAT2/PIO0_25SWCLK/ACMP1_I3/CT32B1_CAP3/CT32B1_MAT3/PIO0_26PIO0_27/ACMP0_O/DA0PIO2_12/RXD1PIO2_13/TXD1PIO2_14/RXD3PIO2_15/TXD364 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49148247346445544643742841QFP64940103911381237133614351534163317 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32R/PIO1_0/AD2R/PIO0_31/AD1R/PIO0_30/AD0PIO0_18/SWCLK/CT32B0_CAP0/CT32B0_MAT0PIO0_17/MOSI/TXD3PIO0_16/MISO/CT16B1_CAP1/CT16B1_MAT1/RXD3PIO0_15/SSEL/CT16B1_CAP0/CT16B1_MAT0/TXD2PIO0_14/SCK/RXD2RESET/PIO0_13PIO0_12/CLKOUT/CT16B0_CAP1/CT16B0_MAT1PIO0_11/SDA/CT16B0_CAP0/CT16B0_MAT0PIO0_10/SCLPIO2_7/CT32B0_CAP3/CT32B0_MAT3/TXD2PIO2_6/CT32B0_CAP2/CT32B0_MAT2/RXD2PIO2_5/CT32B0_CAP1/CT32B0_MAT1PIO2_4/CT32B0_CAP0/CT32B0_MAT0PIO0_28/ACMP1_O/CT16B0_CAP0/CT16B0_MAT0PIO0_29/CT16B0_CAP1/CT16B0_MAT1PIO0_0PIO0_1/RXD0/CT32B0_CAP0/CT32B0_MAT0PIO0_2/TXD0/CT32B0_CAP1/CT32B0_MAT1PIO0_3/CT32B0_CAP2/CT32B0_MAT2PIO0_4/CT32B0_CAP3/CT32B0_MAT3PIO0_5PIO0_6/CT32B1_CAP0/CT32B1_MAT0PIO0_7/CT32B1_CAP1/CT32B1_MAT1PIO0_8/RXD1/CT32B1_CAP2/CT32B1_MAT2PIO0_9/TXD1/CT32B1_CAP3/CT32B1_MAT3PIO2_0/CT16B0_CAP0/CT16B0_MAT0PIO2_1/CT16B0_CAP1/CT16B0_MAT1/RXD0PIO2_2/CT16B1_CAP0/CT16B1_MAT0/TXD0PIO2_3/CT16B1_CAP1/CT16B1_MAT120 www.xinnovatech.com

XN12L6122.3 Pin DescriptionTable 2-1: Pin assignment and descriptionSymbol Pin Wake UpType Default DescriptioninputPIO0_0 19 yes I/O I; PU PIO0_0 — General purpose digital input/output pinPIO0_1/RXD0/CT32B0_CAP0/CT32B0_MAT0PIO0_2/TXD0/CT32B0_CAP1/CT32B0_MAT1PIO0_3/CT32B0_CAP2/CT32B0_MAT2PIO0_4/CT32B0_CAP3/CT32B0_MAT320 yes I/O I; PU PIO0_1 — General purpose digital input/output pin- I - RXD0 — Receiver input for UART0- I - CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0- O - CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 021 yes I/O I; PU PIO0_2 — General purpose digital input/output pin- O - TXD0 — Transmitter output for UART0- I - CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0- O - CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 022 yes I/O I; PU PIO0_3 — General purpose digital input/output pin.- I - CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0- O - CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 023 yes I/O I; PU PIO0_4 — General purpose digital input/output pin- I - CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0- O - CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 0PIO0_5 24 yes I/O I; PU PIO0_5 — General purpose digital input/output pinPIO0_6/CT32B1_CAP0/CT32B1_MAT0PIO0_7/CT32B1_CAP1/CT32B1_MAT1PIO0_8/RXD1/CT32B1_CAP2/CT32B1_MAT2PIO0_9/TXD1/CT32B1_CAP3/CT32B1_MAT3PIO0_10/SCLPIO0_11/SDA/CT16B0_CAP0/25 yes I/O I; PU PIO0_6 — General purpose digital input/output pin- I - CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1- O - CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 126 yes I/O I; PU PIO0_7 — General purpose digital input/output pin- I - CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1- O - CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 127 yes I/O I; PU PIO0_8 — General purpose digital input/output pin- I - RXD1 — Receiver input for UART1- I - CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1- O - CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 128 yes I/O I; PU PIO0_9 — General purpose digital input/output pin- O - TXD1 — Transmitter output for UART1- I - CT32B1_CAP3 — Capture input, channel 3 for 32-bit timer 1- O - CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 137 yes I/O I; IA PIO0_10 — General purpose digital input/output pin- I/O - SCL — TWS-bus clock input/output38 yes I/O I; IA PIO0_11 — General purpose digital input/output pin- I/O - SDA — TWS-bus data input/output- I - CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0www.xinnovatech.com 21

XN12L612Symbol Pin Wake UpType Default DescriptioninputCT16B0_MAT0 - O - CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 0PIO0_12/39 - I/O I; PU PIO0_12 — General purpose digital input/output pin. High-currentoutput driverCLKOUT/CT16B0_CAP1/CT16B0_MAT1RESET/PIO0_13PIO0_14/SCK/RXD2PIO0_15/SSEL/CT16B1_CAP0/CT16B1_MAT0/TXD2PIO0_16/MISO/CT16B1_CAP1/CT16B1_MAT1/RXD3PIO0_17/MOSI/TXD3PIO0_18/SWCLK/CT32B0_CAP0/CT32B0_MAT0PIO0_19/ACMP0_I0/CT32B0_CAP1/CT32B0_MAT1PIO0_20/ACMP0_I1/CT32B0_CAP2/CT32B0_MAT2PIO0_21/ACMP0_I2/- O - CLKOUT — Clock out pin- I - CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0- O - CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 040 - I I; PU RESET — External reset input- I/O - PIO0_13 — General purpose digital input/output pin41 - I/O I; PU PIO0_14 — General purpose digital input/output pin- I/O - SCK — Serial clock for SPI- I - RXD2 — Receiver input for UART242 - I/O I; PU PIO0_15 — General purpose digital input/output pin- I/O - SSEL — Slave select for SPI- I - CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1- O - CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 1- O - TXD2 — Transmitter output for UART243 - I/O I; PU PIO0_16 — General purpose digital input/output pin- I/O - MISO — Master In Slave Out for SPI- I - CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1- O - CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1- I - RXD3 — Receiver input for UART344 - I/O I; PU PIO0_17 — General purpose digital input/output pin- I/O - MOSI — Master Out Slave In for SPI- O - TXD3 — Transmitter output for UART345 - I/O I; PU PIO0_18 — General purpose digital input/output pin- I - SWCLK — Serial wire clock, alternate location- I - CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0- O - CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 04 - I/O I; PU PIO0_19 — General purpose digital input/output pin- I - ACMP0_I0 — Input 0 for comparator 0- I - CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0- O - CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 05 - I/O I; PU PIO0_20 — General purpose digital input/output pin- I - ACMP0_I1 — Input 1 for comparator 0- I - CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0- O - CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 06 - I/O I; PU PIO0_21 — General purpose digital input/output pin- I - ACMP0_I2 — Input 2 for comparator 022 www.xinnovatech.com

XN12L612Symbol Pin Wake UpType Default DescriptioninputCT32B0_CAP3/CT32B0_MAT3PIO0_22/ACMP0_I3PIO0_23/ACMP1_I0/CT32B1_CAP0/CT32B1_MAT0PIO0_24/ACMP1_I1/CT32B1_CAP1/CT32B1_MAT1SWDIO/ACMP1_I2/CT32B1_CAP2/CT32B1_MAT2/PIO0_25SWCLK/ACMP1_I3/CT32B1_CAP3/CT32B1_MAT3/PIO0_26PIO0_27/- I - CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0- O - CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 07 - I/O I; PU PIO0_22 — General purpose digital input/output pin- I - ACMP0_I3 — Input 3 for comparator 08 - I/O I; PU PIO0_23 — General purpose digital input/output pin- I - ACMP1_I0 — Input 0 for comparator 1- I - CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1- O - CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 19 - I/O I; PU PIO0_24 — General purpose digital input/output pin- I - ACMP1_I1 — Input 1 for comparator 1- I - CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1- O - CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 110 - I/O I; PU SWDIO — Serial wire debugs input/output, default location- I - ACMP1_I2 — Input 2 for comparator 1- I - CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1- O - CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1- I/O - PIO0_25 — General purpose digital input/output pin11 - I I; PU SWCLK — Serial wire clock, default location- I - ACMP1_I3 — Input 3 for comparator 1- I - CT32B1_CAP3 — Capture input, channel 3 or 32-bit timer 1- O - CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1- I/O PIO0_26 — General purpose digital input/output pin12 - I/O I; PU PIO0_27 — General purpose digital input/output pin. High-currentoutput driverACMP0_O/DA0PIO0_28/- O - ACMP0_O — Output for comparator 0- O - DA0 — DA Output17 - I/O I; PU PIO0_28 — General purpose digital input/output pin. High-currentoutput driverACMP1_O/CT16B0_CAP0/CT16B0_MAT0PIO0_29/- O - ACMP1_O — Output for comparator 1- I - CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0- O - CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 018 - I/O I; PU PIO0_29 — General purpose digital input/output pin. High-currentoutput driverCT16B0_CAP1/CT16B0_MAT1R/- I - CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0- O - CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 046 - I I; PU R — Reserved. Configure for an alternate function in the IOCONFIGblock. TEST purpose pin 0PIO0_30/- I/O - PIO0_30 — General purpose digital input/output pinwww.xinnovatech.com 23

XN12L612Symbol Pin Wake UpType Default DescriptioninputAD0 - I - AD0 — A/D converter, input 0R/47 - I I; PU R — Reserved. Configure for an alternate function in the IOCONFIGblock. TEST purpose pin 1PIO0_31/AD1R/- I/O - PIO0_31 — General purpose digital input/output pin- I - AD1 — A/D converter, input 148 - I I; PU R — Reserved. Configure for an alternate function in the IOCONFIGblock. TEST purpose pin 2PIO1_0/AD2R/- I/O - PIO1_0 — General purpose digital input/output pin- I - AD2 — A/D converter, input 249 - I I; PU R — Reserved. Configure for an alternate function in the IOCONFIGblock. TEST purpose pin 3PIO1_1/AD3PIO1_2/SWDIO/AD4PIO1_3/AD5/WAKEUPPIO1_4/AD6PIO1_5/AD7/CT16B1_CAP0/CT16B1_MAT0PIO1_6/CT16B1_CAP1/CT16B1_MAT1PIO2_0/CT16B0_CAP0/CT16B0_MAT0PIO2_1/CT16B0_CAP1/CT16B0_MAT1/RXD0PIO2_2/CT16B1_CAP0/CT16B1_MAT0/- I/O - PIO1_1 — General purpose digital input/output pin- I - AD3 — A/D converter, input 350 - I/O I; PU PIO1_2 — General purpose digital input/output pin- I/O - SWDIO — Serial wire debug input/output, alternate location- I - AD4 — A/D converter, input 451 - I/O I; PU PIO1_3 — General purpose digital input/output pin- I - AD5 — A/D converter, input 5- I - WAKEUP — Power-down mode wake-up pin52 - I/O I; PU PIO1_4 — General purpose digital input/output pin- I - AD6 — A/D converter, input 653 - I/O I; PU PIO1_5 — General purpose digital input/output pin- I - AD7 — A/D converter, input 7- I - CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1- O - CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 154 - I/O I; PU PIO1_6 — General purpose digital input/output pin- I - CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1- O - CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 129 - I/O I; PU PIO2_0 — General purpose digital input/output pin- I - CT16B0_CAP0 — Capture input, channel 0 for 16-bit timer 0- O - CT16B0_MAT0 — Match output, channel 0 for 16-bit timer 030 - I/O I; PU PIO2_1 — General purpose digital input/output pin- I - CT16B0_CAP1 — Capture input, channel 1 for 16-bit timer 0- O - CT16B0_MAT1 — Match output, channel 1 for 16-bit timer 0- I - RXD0 — Receiver input for UART031 - I/O I; PU PIO2_2 — General purpose digital input/output pin- I - CT16B1_CAP0 — Capture input, channel 0 for 16-bit timer 1- O - CT16B1_MAT0 — Match output, channel 0 for 16-bit timer 124 www.xinnovatech.com

XN12L612Symbol Pin Wake UpType Default DescriptioninputTXD0 - O - TXD0 — Transmitter output for UART0PIO2_3/CT16B1_CAP1/CT16B1_MAT1/PIO2_4/CT32B0_CAP0/CT32B0_MAT0/PIO2_5/CT32B0_CAP1/CT32B0_MAT1/PIO2_6/CT32B0_CAP2/CT32B0_MAT2/RXD2PIO2_7/CT32B0_CAP3/CT32B0_MAT3/TXD2PIO2_8/CT32B1_CAP0/CT32B1_MAT0PIO2_9/CT32B1_CAP1/CT32B1_MAT1PIO2_10/CT32B1_CAP2/CT32B1_MAT2/TXD1PIO2_11/CT32B1_CAP3/CT32B1_MAT3/RXD1PIO2_12/RXD1PIO2_13/TXD1PIO2_14/RXD332 - I/O I; PU PIO2_3 — General purpose digital input/output pin- I - CT16B1_CAP1 — Capture input, channel 1 for 16-bit timer 1- O - CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 133 - I/O I; PU PIO2_4 — General purpose digital input/output pin- I - CT32B0_CAP0 — Capture input, channel 0 for 32-bit timer 0- O - CT32B0_MAT0 — Match output, channel 0 for 32-bit timer 034 - I/O I; PU PIO2_5 — General purpose digital input/output pin- I - CT32B0_CAP1 — Capture input, channel 1 for 32-bit timer 0- O - CT32B0_MAT1 — Match output, channel 1 for 32-bit timer 035 - I/O I; PU PIO2_6 — General purpose digital input/output pin- I - CT32B0_CAP2 — Capture input, channel 2 for 32-bit timer 0- O - CT32B0_MAT2 — Match output, channel 2 for 32-bit timer 0- I - RXD2 — Receiver input for UART236 - I/O I; PU PIO2_7 — General purpose digital input/output pin- I - CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer 0- O - CT32B0_MAT3 — Match output, channel 3 for 32-bit timer 0- O - TXD2 — Transmitter output for UART259 - I/O I; PU PIO2_8 — General purpose digital input/output pin- I - CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1- O - CT32B1_MAT0 — Match output, channel 0 for 32-bit timer 160 - I/O I; PU PIO2_9 — General purpose digital input/output pin- I - CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer 1- O - CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 161 - I/O I; PU PIO2_10 — General purpose digital input/output pin- I - CT32B1_CAP2 — Capture input, channel 2 for 32-bit timer 1- O - CT32B1_MAT2 — Match output, channel 2 for 32-bit timer 1- O - TXD1 — Transmitter output for UART162 - I/O I; PU PIO2_11 — General purpose digital input/output pin- I - CT32B1_CAP3 — Capture input, channel 3 for 32-bit timer 1- O - CT32B1_MAT3 — Match output, channel 3 for 32-bit timer 1- I - RXD1 — Receiver input for UART113 - I/O I; PU PIO2_12 — General purpose digital input/output pin- I - RXD1 — Receiver input for UART114 - I/O I; PU PIO2_13 — General purpose digital input/output pin- O - TXD1 — Transmitter output for UART115 - I/O I; PU PIO2_14 — General purpose digital input/output pin- I - RXD3 — Receiver input for UART3www.xinnovatech.com 25

XN12L612Symbol Pin Wake UpType Default DescriptioninputPIO2_15/TXD316 - I/O I; PU PIO2_15 — General purpose digital input/output pin- O - TXD3 — Transmitter output for UART3RTCXOUT 58 - O - Output from the 32 KHz oscillator circuitRTCXIN 57 - I - Input to the 32 KHz oscillator amplifierXTALIN 1 - I - Input to the system oscillator circuit and internal clock generatorcircuitsXTALOUT 2 - O - Output from the system oscillator amplifierV REF_ADC 3 - I - Used as the ADC reference voltageV DD(IO) 63 - I - Input/output supply voltageV DD(3V3) 56 - I - 3.3 V supply voltage to the internal regulator and the ADCV SSIO 64 - I - GroundV SS 55 - I - Ground2.4 Peripheral Pin GroupTo enable a peripheral function on a pin, find the corresponding port pin, or select a port pin if the function is multiplexed, andprogram the port pin’s IOCONFIG register to enable that function. The primary SWD functions and RESET are the defaultfunctions on their pins after reset, all other digital pins default to GPIO.Table 2-2: Pin multiplexingPeripheral Function Type Available on portsAnalog Comparators ACMP0_I0 I PIO0_19ACMP0_I1 I PIO0_20ACMP0_I2 I PIO0_21ACMP0_I3 I PIO0_22ACMP0_O O PIO0_27ACMP1_I0 I PIO0_23ACMP1_I1 I PIO0_24ACMP1_I2 I PIO0_25ACMP1_I3 I PIO0_26ACMP1_O O PIO0_28ADC AD0 I PIO0_30AD1 I PIO0_31AD2 I PIO1_0AD3 I PIO1_1AD4 I PIO1_2AD5 I PIO1_3AD6 I PIO1_4AD7 I PIO1_526 www.xinnovatech.com

XN12L612Peripheral Function Type Available on portsDAC DA0 O PIO0_27CT16B0 CT16B0_CAP0 I PIO0_11 PIO0_28 PIO2_0CT16B0_CAP1 I PIO0_12 PIO0_29 PIO2_1CT16B0_MAT0 O PIO0_11 PIO0_28 PIO2_0CT16B0_MAT1 O PIO0_12 PIO0_29 PIO2_1CT16B1 CT16B1_CAP0 I PIO0_15 PIO1_5 PIO2_2CT16B1_CAP1 I PIO0_16 PIO1_6 PIO2_3CT16B1_MAT0 O PIO0_15 PIO1_5 PIO2_2CT16B1_MAT1 O PIO0_16 PIO1_6 PIO2_3CT32B0 CT32B0_CAP0 I PIO0_1 PIO0_18 PIO2_4CT32B0_CAP1 I PIO0_2 PIO0_19 PIO2_5CT32B0_CAP2 I PIO0_3 PIO0_20 PIO2_6CT32B0_CAP3 I PIO0_4 PIO0_21 PIO2_7CT32B0_MAT0 O PIO0_1 PIO0_18 PIO2_4CT32B0_MAT1 O PIO0_2 PIO0_19 PIO2_5CT32B0_MAT2 O PIO0_3 PIO0_20 PIO2_6CT32B0_MAT3 O PIO0_4 PIO0_21 PIO2_7CT32B1 CT32B1_CAP0 I PIO0_6 PIO0_23 PIO2_8CT32B1_CAP1 I PIO0_7 PIO0_24 PIO2_9CT32B1_CAP2 I PIO0_8 PIO0_25 PIO2_10CT32B1_CAP3 I PIO0_9 PIO0_26 PIO2_11CT32B1_MAT0 O PIO0_6 PIO0_23 PIO2_8CT32B1_MAT1 O PIO0_7 PIO0_24 PIO2_9CT32B1_MAT2 O PIO0_8 PIO0_25 PIO2_10CT32B1_MAT3 O PIO0_9 PIO0_26 PIO2_11UART0 RXD0 I PIO0_1 PIO2_1TXD0 O PIO0_2 PIO2_2UART1 RXD1 I PIO0_8 PIO2_11 PIO2_12TXD1 O PIO0_9 PIO2_10 PIO2_13UART2 RXD0 I PIO0_14 PIO2_6TXD0 O PIO0_15 PIO2_7UART3 RXD1 I PIO0_16 PIO2_14TXD1 O PIO0_17 PIO2_15SPI SCK I/O PIO0_14MISO I/O PIO0_16MOSI I/O PIO0_17SSEL I/O PIO0_15TWS SCL I/O PIO0_10SDA I/O PIO0_11www.xinnovatech.com 27

XN12L612Peripheral Function Type Available on portsSWD SWCLK I PIO0_26 PIO0_18SWDIO I/O PIO0_25 PIO1_228 www.xinnovatech.com

XN12L6123 System Block DiagramSWDXTALINXTALOUT RESETTEST/DEBUGINTERFACEIRC, OSILLATORSBODPORCLOCKGENERATION,POWER CONTROLSYSTEMFUNCTIONCLKOUTARMCortex-M0DMACONTROLLER88K APP. FLASH8KBOOT16K SRAMAHB-LITE BUSxDSP(CRC/Sin/Cos/Arctan/32-bit Divider)AHB-APBBRIDGETemperatureSensorHIGH speedGPIOGPIO_portSPI12-bit ADC112-bit ADC0AD[7:0]UART012-bit ADC2UART110-bit DACDAUART2UART3TWSCOMPARATOR0/1ACMP0_I[3:0]ACMP1_I[3:0]ACMP0_OACMP1_OWATCHDOG32-bitCOUNTER/TIMER4xMAT4xCAPRTCLKINRTCLKOUT32KHzOSCILLATORRTC32-bitCOUNTER/TIMER4xMAT4xCAPSYSTEM CONTROL16-bitCOUNTER/TIMER2xMAT2xCAP16-bitCOUNTER/TIMER2xMAT2xCAPFigure 3-1: XN12L612 block diagramwww.xinnovatech.com 29

XN12L6124 System Description4.1 ARM Cortex-M0 CoreThe Cortex-M0 processor is 32-bit Reduced Instruction Set Computing (RISC) processor introduced by ARM. It has anAMBA AHB-Lite interface and includes a Nested Vector Interrupt Controller (NVIC) component. It also has optional hardwaredebug functionality. The processor uses Thumb instruction set and is compatible with other ARM Cortex-M profileprocessor. It supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. Anexception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result ofan exception return.Figure shows the functional controller of processor.PowerManagementInterfaceConnection toDebuggerWakeup InterruptControllerSWD DebugInterfaceInterruptRequest andNMINested VectorInterrupt Controller(NVIC)Cortex-M0Processor CoreDebug SubsystemInternal Bus SystemAHB LITE BusInterfaceCortex-M0Memory andPeripheralsFigure 4-1: Cortex M0 Core block diagramARM Cortex-M0 processor provides the following functions and features:• The ARMv6-M Thumb ® instruction set• Thumb-2 technology• ARMv6-M compliant 24-bit System Tick (SysTick) timer• A 32-bit hardware multiplier30 www.xinnovatech.com

XN12L612• The system interface supports little-endian data accesses• The ability to have deterministic, fixed-latency, interrupt handling• Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling• C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI)compliant exception model that enables the use of pure C functions as interrupt handlers• Low power sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return frominterrupt sleep-on-exit feature• NVIC that features:– 32 external interrupt inputs, each with four levels of priority– Dedicated Non-Maskable Interrupt (NMI) input.– Support for both level-sensitive and pulse-sensitive interrupt lines– Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.• Debug support– Four hardware breakpoints.– Two watch points.– Program Counter Sampling Register (PCSR) for non-intrusive code profiling.– Single step and vector catch capabilities.• Bus interfaces:– Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals andmemory.– Single 32-bit slave port that supports the Debug Access Port (DAP).4.2 Memory MapXN12L612 memory address space supports up to 4GB size. It’s divided into a few memory segments: boot area, flashmemory area, SRAM area, private peripheral area, APB peripheral area and AHB peripheral area.The private peripheral area is reserved for M0 core.The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The GPIO ports, the xDSP, and theDMA controller are AHB peripherals.The APB peripheral area is 512 KB in size and each peripheral of either type is allocated with 16 KB. This allows thesimplified address decoding for each peripheral. All peripheral register addresses are 32-bit word aligned regardless of theirsize. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possibleto read or write the upper byte of a word register separately.www.xinnovatech.com 31

XN12L612The boot area is 8 KB size and used to store MCU bootloader, ISP and IAP function. The user is able to take 88 KB flashmemory and 16 KB SRAM for application usage. The flash and SRAM apply 32-bit data bus.The following diagram shows XN12L612 memory allocation:32 www.xinnovatech.com

XN12L612Private peripheralReserved0xE010 00004GBReservedPrivate peripheralReservedAHB peripheral0xFFFF FFFF0xE010 00000xE000 00000x5008 00000x5000 0000SCBNVICSystem TickReservedAHB peripheralxDSPFlashReservedGPIO PIO2GPIO PIO1GPIO PIO0APB peripheral0xE000 EE000xE000 ED000xE000 E1000xE000 E0000xE000 00000x5008 00000x5007 00000x5006 00000x5003 00000x5002 00000x5001 00000x5000 0000ReservedAPB peripheralReserved8KB Boot romReserved0x4008 00000x4000 00000x1FFF 20000x1FFF 00000x1FFE 0000ReservedUART3UART2DAC0ADC2ADC1Reserved0x4008 00000x4007 80000x4007 40000x4007 00000x4006 C1800x4006 80000x4006 4000Reserved16KB SRAMReserved88KB On-chip0x1000 40000x1000 00000x0001 60000x0000 0000Interrupt vectors0x0000 00C00x0000 0000Comparator 0/1RTCDMASystem controlIO configSPIReservedPMUReserved0x4005 80000x4005 40000x4005 00000x4004 C0000x4004 80000x4004 40000x4004 00000x4003 C0000x4003 8000ADC032-bit timer/counter32-bit timer/counter16-bit timer/counter16-bit timer/counterUART1UART0WDTTWS0x4002 40000x4002 00000x4001 C0000x4001 80000x4001 40000x4001 00000x4000 C0000x4000 80000x4000 40000x4000 0000Figure 4-2: Memory allocation diagramwww.xinnovatech.com 33

XN12L612Table 4-1: Memory map summaryAddress Function Description0x00000000 ~ 0x00015FFF0x10000000 ~ 0x10003FFF0x10002000 ~ 0x1FFEFFFF0x1FFF0000 ~ 0x1FFF1FFF0x40000000 ~ 0x40003FFF0x40004000 ~ 0x40007FFFFlash memorySRAM memoryReserved RAM spaceBoot LoaderTWSWatchdog0x40008000 ~ 0x4000BFFF UART 00x4000C000 ~ 0x4000FFFF UART 10x40010000 ~ 0x40013FFF 16-Bit Timer 00x40014000 ~ 0x40017FFF 16-Bit Timer 10x40018000 ~ 0x4001BFFF 32-Bit Timer 00x4001C000 ~ 0x4001FFFF 32-Bit Timer 10x40020000 ~ 0x40023FFF0x40024000 ~ 0x40037FFF0x40038000 ~ 0x4003BFFF0x4003C000 ~ 0x4003FFFF0x40040000 ~ 0x40043FFF0x40044000 ~ 0x40047FFF0x40048000 ~ 0x4004BFFF0x4004C000 ~ 0x4004FFFF0x40050000 ~ 0x40053FFF0x40054000 ~ 0x40057FFF0x40058000 ~ 0x40063FFFF0x40064000 ~ 0x40067FFFF0x40068000 ~ 0x4006BFFFF0x4006C180 ~ 0x4006FFFFF0x40070000 ~ 0x40073FFFF0x40074000 ~ 0x40077FFFF0x40080000 ~ 0x4FFFFFFFADC0ReservedPMUReservedSPIIOCONFIGSystem ControlDMA registerReal Timer ClockComparator0,1Reserved SpaceADC1ADC2DACUART2UART3Reserved Space0x50000000 ~ 0x5000FFFF GPIO 00x50010000 ~ 0x5001FFFF GPIO 10x50020000 ~ 0x5002FFFF GPIO 20x50030000 ~ 0x5005FFFF0x50060000 ~ 0x5006FFFF0x50070000 ~ 0x5007FFFF0x50080000 ~ 0xFFFFFFFF0xE000E000 ~ 0xE000E0FF0xE000E100 ~ 0xE000E4FFReserved spaceFlash Memory Access ControlxDSP spaceReserved spaceSystem Tick TimerNVIC Control34 www.xinnovatech.com

XN12L6120xE000ED00 ~ 0xE000EE00M0 Core SCB Controlwww.xinnovatech.com 35

XN12L6124.3 Cortex-M0 Core System Control Block4.3.1 General DescriptionThe Cortex-M0 Core System Control Block (SCB) provides M0 core system implementation information, and core systemcontrol. It includes configuration, control, and reporting of the system exceptions. The SCB registers list as:Table 4-2: Summary of the Cortex M0 core SCB registers (base address 0xE000-ED00)Symbol Access Offset Address Description Reset valueCPUID RO 0x00 The information of M0 core. 0x410CC200ICSR RW 0x04 NMI interrupt control and status 0x00000000AIRCR RW 0x0C Application Interrupt and Reset Control Register 0xFA050000SCR RW 0x10 System Control Register 0x00000000CCR RO 0x14 Configuration and Control Register 0x00000204SHPR2 RW 0x1C System handle Priority Register2 0x00000000SHPR3 RW 0x20 System handle Priority Register3 0x000000004.3.2 CPUID RegisterThe CPUID register contains the M0 core processor part number, version, and implementation information. See the registersummary in for its attributes.Table 4-3: CPUID Register (CPUID, address0xE000-ED00) bit descriptionBit Symbol Description3:0 REVISION Revision number15:4 PARTNO Part number of the processor: 0xC20 = Cortex-M019:16 CONSTANT The architecture of the processor:, 0xC = ARMv6-M architecture23:20 - Reserved31:24 IMPLEMENTER Implementer code: 0x41 = ARM4.3.3 Interrupt Control and State RegisterThe Interrupt Control and State Register (ICSR) is used to control and indicate non-maskable interrupt.Table 4-4: Interrupt Control and State Register (ICSR, address0xE000-ED04) bit descriptionBit Symbol Access Description5:0 VECTACTIVE RO Contains the active exception number:0 = Thread modeNone 0 = The exception number [1] of the currently active exception.Note: Subtract 16 from this value to obtain the CMSIS IRQ number that identifies thecorresponding bit in the Interrupt Clear-Enable, Set-Enable, Clear-Pending,Set-pending, and Priority Register.11:6 - - Reserved.36 www.xinnovatech.com

XN12L61217:12 VECTPENDING RO Indicates the exception number of the highest priority pending enabled exception:0 = no pending exceptionsNone 0 = the exception number of the highest priority pending enabled exception.21:18 - - Reserved.22 ISRPENDING RO Interrupt pending flag, excluding NMI and Faults:0 = interrupt not pending1 = interrupt pending.24:23 - - Reserved.25 PENDSTCLR WO SysTick exception clear-pending bit. Write:0 = no effect1 = removes the pending state from the SysTick exception. This bit is WO. On a registerread its value is Unknown.26 PENDSTSET RW SysTick exception set-pending bit.Write:0 = no effect1 = changes SysTick exception state to pending.Read:0 = SysTick exception is not pending1 = SysTick exception is pending.27 PENDSVCLR WO PendSV clear-pending bit.Write:0 = no effect1 = removes the pending state from the PendSV exception.28 PENDSVSET RW PendSV set-pending bit.Write:0 = no effect1 = changes PendSV exception state to pending.Read:0 = PendSV exception is not pending1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSVexception state to pending.30:29 - - Reserved.www.xinnovatech.com 37

XN12L61231 NMIPENDSET RW NMI set-pending bit. Write:0 = no effect1 = changes NMI exception state to pending.Read:0 = NMI exception is not pending1 = NMI exception is pending.Because NMI is the highest-priority exception, normally the processor enters the NMIexception handler as soon as it detects a write of 1 to this bit. Entering the handler thenclears this bit to 0. This means a read of this bit by the NMI exception handler returns 1only if the NMI signal is reasserted while the processor is executing that handler.4.3.4 Application Interrupt and Reset Control RegisterThe Application Interrupt and Reset Control Register (AIRCR) provides endian status for data accesses and reset control ofthe system.Table 4-5: Application Interrupt and Reset Control Register (AIRCR, address0xE000-ED0C) bit descriptionBit Symbol Access Description0 - - Reserved.1 VECTCLRACTIVE WO Reserved for debug use. This bit reads as 0. When writing to the register you must write0 to this bit, otherwise behavior is Unpredictable.2 SYSRESETREQ WO System reset request:0 = no effect1 = requests a system level reset. This bit reads as 0.14:3 - - Reserved15 ENDIANESS RO Data endianness implemented:0 = Little-endian1 = Big-endian.31:16 VECTKEY WO Register key: On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.4.3.5 System Control RegisterThe System Control Register (SCR) controls features of entry to and exit from low power state.Table 4-6: System Control Register (SCR, address0xE000-ED10) bit descriptionBit Symbol Description0 - Reserved1 SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode:0 = do not sleep when returning to Thread mode.1 = enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enablesan interrupt driven application to avoid returning to an empty main application.38 www.xinnovatech.com

XN12L6122 SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode:0 = sleep1 = deep sleep.3 - Reserved.4 SEVONPEND Send Event on Pending bit:0 = only enabled interrupts or events can wake up the processor, disabled interrupts are excluded1 = enabled events and all interrupts, including disabled interrupts, can wake up the processor.When an event or interrupt enters pending state, the event signal wakes up the processor fromWFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.The processor also wakes up on execution of an SEV instruction.31:5 - Reserved4.3.6 Configuration and Control RegisterThe Configuration and Control Register (CCR) is a read-only register and indicates some aspects of the behavior of theCortex-M0 processor.Table 4-7: Configuration and Control Register (CCR, address0xE000-ED14) bit descriptionBit Symbol Description2:0 - Reserved.3 UNALIGN_TRP Always reads as one, indicates that all unaligned accesses generate a HardFault.8:4 - Reserved.9 STKALIGN Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, theprocessor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from theexception it uses this stacked bit to restore the correct stack alignment.31:10 - Reserved.4.3.7 System Handle Priority RegistersTo improve software efficiency, the Cortex Microcontroller Software Interface Standard (CMSIS) simplifies the SCB registerpresentation. In the CMSIS, the array of system handle priority registers (SHPR) corresponds to the registersSHPR2-SHPR3.Table 4-8: SHPR2 Register (SHPR2, address0xE000-ED1C) bit descriptionBit Symbol Description29:0 - Reserved.31:30 PRI_11 Priority of system handle -11 – SVCall“0” denotes the highest priority and “3” denotes lowest priorityTable 4-9: SHPR3 Register (SHPR3, address0xE000-ED20) bit descriptionBit Symbol Description21:0 - Reserved.www.xinnovatech.com 39

XN12L61223:22 PRI_14 Priority of system handle -14 – PendSV“0” denotes the highest priority and “3” denotes lowest priority29:24 - Reserved.31:30 PRI_15 Priority of system handle -15 – SysTick“0” denotes the highest priority and “3” denotes lowest priority4.4 Nested Vectored Interrupt Controller (NVIC)4.4.1 NVIC DescriptionThe Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allowsfor low interrupt latency and efficient processing of late arriving interrupts. The major features:• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0.• Tightly coupled interrupt controller provides low interrupt latency.• Controls system exceptions and peripheral interrupts.• Supports 32 vectored interrupts.• Four programmable interrupt priority levels with hardware priority level masking.• Software interrupts generation.• Non-Maskable Interrupt (NMI) with configurable source.The following lists the interrupt sources for system and each peripheral function. Each peripheral device may have one ormore interrupt lines to the Vectored Interrupt Controller. Each line may represent more than one interrupt source. There is nosignificance or priority about what line is connected where, except for certain standards from ARM.Table 4-10: Vectored Interrupt sources and vector listExceptionIRQOffset Addr.Exception Type Priority DescriptionNumberNumberin VectorTable0x00Initial SP Value1 0x04 Reset -3 the Highest2 -14 0x08 NMI -23 -13 0x0C HardFault -110~4 0x10~0x28 Reserved11 -5 0x2C SVCall Configurable (1)13~12 0x30~0x34 Reserved14 -2 0x38 PendSV Configurable (1)15 -1 0x3C SysTick Configurable (1)16 0 0x40 wake-upinterrupt 0Configurable (2)Connected to a PIO input pin serving as wake-uppin when the part is in Deep-sleep mode; Interrupt 0correspond to PIO0_0, PIO0_4 and PIO0_8.40 www.xinnovatech.com

XN12L61217 1 0x44 wake-upinterrupt 118 2 0x48 wake-upinterrupt 219 3 0x4C wake-upinterrupt 3Configurable (2)Configurable (2)Configurable (2)Connected to a PIO input pin serving as wake-uppin when the part is in Deep-sleep mode; Interrupt 1correspond to PIO0_1, PIO0_5 and PIO0_9.Connected to a PIO input pin serving as wake-uppin when the part is in Deep-sleep mode; Interrupt 2correspond to PIO0_2, PIO0_6 and PIO0_10.Connected to a PIO input pin serving as wake-uppin when the part is in Deep-sleep mode; Interrupt3 correspond to PIO0_3, PIO0_7 and PIO0_11.20 4 0x50 - -21 5 0x54 - -22 6 0x58 - -23 7 0x5C - -24 8 0x60 ADC 1 interrupt Configurable (2) A/D Converter end of conversion25 9 0x64 ADC 2 interrupt Configurable (2) A/D Converter end of conversion26 10 0x68 UART 2 interrupt Configurable (2) Transmit Holding Register Empty (THRE)Transmit Holding Register overrun(THROE)Receive Buffer Full(RBRS)Receive Buffer Overrun(RBROE)27 11 0x6C UART 3 interrupt Configurable (2) Transmit Holding Register Empty (THRE)Transmit Holding Register overrun(THROE)Receive Buffer Full(RBRS)Receive Buffer Overrun(RBROE)28 12 0x70 TWS Configurable (2) SI (state change)29 13 0x74 CT16B0 Configurable (2) Match 3 to 0Capture 3 to 030 14 0x78 CT16B1 Configurable (2) Match 3 to 0Capture 3 to 031 15 0x7C CT32B0 Configurable (2) Match 3 to 0Capture 3 to 032 16 0x80 CT32B1 Configurable (2) Match 3 to 0Capture 3 to 033 17 0x84 SPI Configurable (2) Tx FIFO half empty Rx FIFO half fullRx TimeoutRx Overrun34 18 0x88 UART0 Configurable (2) Transmit Holding Register Empty (THRE)Transmit Holding Register overrun(THROE)Receive Buffer Full(RBRS)Receive Buffer Overrun(RBROE)www.xinnovatech.com 41

XN12L61235 19 0x8C UART1 Configurable (2) Transmit Holding Register Empty (THRE)Transmit Holding Register overrun(THROE)Receive Buffer Full(RBRS)Receive Buffer Overrun(RBROE)36 20 0x90 Comparator Configurable (2) Comparator 0/1 interrupt37 21 0x94 ADC0 Configurable (2) A/D Converter end of conversion38 22 0x98 WDT Configurable (2) Watchdog interrupt (WDINT)39 23 0x9C BOD Configurable (2) Brown-out detect40 24 0xA0 - -41 25 0xA4 PIO0 Configurable (2) GPIO interrupt status of port 042 26 0xA8 PIO1 Configurable (2) GPIO interrupt status of port 143 27 0xAC PIO2 Configurable (2) GPIO interrupt status of port 244 28 0xB0 - -45 29 0xB4 DMA Configurable (2) DMA request interrupt46 30 0xB8 RTC Configurable (2) RTC interrupt47 31 0xBC DAC Configurable (2) D/A converter interruptNote:(1) See SCB control register SHPR2-SHPR3.(2) See IPR0~IPR7 of NVIC.4.4.2 Nested Vectored Interrupt Controller Register ListThe listed NVIC control registers allow user to control IRQ0~IRQ31, including interrupt enable, pending, and priority.Table 4-11: NVIC register summarySymbol Access Address Description Reset valueINTNMI R/W 0x4004 8174 Non-Maskable Interrupt (NMI) source configISER R/W 0xE000 E100 Interrupt Set-enable Register 0x00000000ICER R/W 0xE000 E180 Interrupt Clear-enable Register 0x00000000ISPR R/W 0xE000 E200 Interrupt Set-pending Register 0x00000000ICPR R/W 0xE000 E280 Interrupt Clear-pending Register 0x00000000IPR0 R/W 0xE000 E400 Interrupt Priority Registers IPR0 0x00000000IPR1 R/W 0xE000 E404 Interrupt Priority Registers IPR1 0x00000000IPR2 R/W 0xE000 E408 Interrupt Priority Registers IPR2 0x00000000IPR3 R/W 0xE000 E40C Interrupt Priority Registers IPR3 0x00000000IPR4 R/W 0xE000 E410 Interrupt Priority Registers IPR4 0x00000000IPR5 R/W 0xE000 E414 Interrupt Priority Registers IPR5 0x00000000IPR6 R/W 0xE000 E418 Interrupt Priority Registers IPR6 0x00000000IPR7 R/W 0xE000 E41C Interrupt Priority Registers IPR7 0x0000000042 www.xinnovatech.com

XN12L6124.4.3 Interrupt Set-enable RegisterThe Interrupt Set-Enable Register (ISER) enables interrupts, and show which interrupts are enabled.Table 4-12: Interrupt Set-Enable Register (ISER, address 0xE000 E100) bit descriptionBit Symbol Description Reset Value31:0 SETENA Interrupt IRQ0~IRQ31 set-enable bits.0x00000000Write:0 = no effect1 = enable interrupt.Read:0 = interrupt disabled1 = interrupt enabled.If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, assertingits interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.4.4.4 Interrupt Clear-enable RegisterThe Interrupt Clear-enable Register (ICER) disables interrupts, and show which interrupts are enabled.Table 4-13: Interrupt Clear-enable Register (ICER, address 0xE000 E180) bit descriptionBit Symbol Description Reset Value31:0 CLRENA Interrupt IRQ0~IRQ31 clear-enable bits.0x00000000Write:0 = no effect1 = disable interrupt.Read:0 = interrupt disabled1 = interrupt enabled.4.4.5 Interrupt Set-pending RegisterThe Interrupt Set-pending Register (ISPR) forces interrupts into the pending state and shows which interrupts are pending.Table 4-14: Interrupt Set-pending Register (ISPR, address 0xE000 E200) bit descriptionBit Symbol Description Reset Value31:0 SETPEND Interrupt IRQ0~IRQ31 set-pending bits.0x00000000Write:0 = no effect1 = changes interrupt state to pending.Read:0 = interrupt is not pending1 = interrupt is pending.Note: Writing 1 to the ISPR bit corresponding to:www.xinnovatech.com 43

XN12L612• an interrupt that is pending has no effect• a disabled interrupt sets the state of that interrupt to pending.4.4.6 Interrupt Clear-pending RegisterThe interrupt Clear-pending Register (ICPR) removes the pending state from interrupts, and show which interrupts arepending.Table 4-15: Interrupt Clear-pending Register (ICPR, address 0xE000 E280) bit descriptionBit Symbol Description Reset Value31:0 CLRPEND Interrupt IRQ0~IRQ31 clear-pending bits.0x00000000Write:0 = no effect1 = removes pending state of an interrupt.Read:0 = interrupt is not pending1 = interrupt is pending.Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.4.4.7 Interrupt Priority RegistersThe Interrupt Priority Registers IPR0-IPR7 provide an 2-bit priority field for each interrupt (IRQ0~IRQ31). These registers areonly word-accessible. Each register holds four priority fields as shown:31 24 23 16 15 8 7 0IPR7PRI_31 PRI_30 PRI_29 PRI_28......IPRnPRI_(4n+3) PRI_(4n+2) PRI_(4n+1) PRI_(4n)......IPR0PRI_3 PRI_2 PRI_1 PRI_0Figure 4-3: IPR registerTable 4-16: IPRn Register (IPR0~7, address 0x0xE000 E400~0xE000 E41C) bit descriptionBit Symbol Description Reset Value7:0 Priority, byte offset 0 Each priority field holds a priority value, 0-3.0x0015:823:1631:24Priority, byte offset 1Priority, byte offset 2Priority, byte offset 3The lower the value, the greater the priority of the corresponding interrupts.The processor implements only bits [7:6] of each field, bits [5:0] read aszero and ignore writes.0x000x000x00Find the IPR number and byte offset for interrupt M as follows:44 www.xinnovatech.com

XN12L612• the corresponding IPR number, N, is given by N = N DIV 4• the byte offset of the required Priority field in this register is M MOD 4, where:– byte offset 0 refers to register bits 7:0– byte offset 1 refers to register bits 15:8– byte offset 2 refers to register bits 23:16– byte offset 3 refers to register bits 31:244.4.7.1 NMI Interrupt Source Configuration RegisterThis register configures a source for the ARM Cortex-M0 Non-Maskable Interrupt (NMI).Table 4-17: NMI interrupt source configuration register (INTNMI, address 0x4004 8174) bit descriptionBit Symbol Value Description Reset value5:0 NMISRC NMI interrupts source select. -0 ~ 3 wake-up interrupt 0~37~ 4 Reserved8 ADC19 ADC210 UART211 UART312 TWS13 CT16B014 CT16B115 CT32B016 CT32B117 SPI18 UART019 UART120 Reserved21 ADC022 WDT23 BOD24 Reserved25 PIO026 PIO127 Reserved28 Reserved29 Reserved30 RTC31 DACwww.xinnovatech.com 45

XN12L61232~62 Reserved63 NMI disabled31:6 - - Reserved 0x04.5 System Tick TimerThe SysTick timer is an integral part of the Cortex-M0. The SysTick timer is intended to generate a fixed 10 millisecondinterrupt for use by an operating system or other system management software. Since the SysTick timer is a part of theCortex-M0, it facilitates porting of software by providing a standard timer that is available on Cortex-M0 based devices.The SysTick timer can be used for:• An RTOS tick timer which fires at a programmable rate (for example 100 Hz) and invokes a SysTick routine.• A high-speed alarm timer using the core clock.• A simple counter. Software can use this to measure time to completion and time used.• An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control andstatus register can be used to determine if an action completed within a set duration, as part of a dynamic clockmanagement control loop.Features:• Simple 24-bit timer.• Uses dedicated exception vector.• Clocked internally by the system clock.Table 4-18: Register overview: SysTick timer (base address 0xE000 E000)Symbol Access Address offset Description Reset valueSYST_CSR R/W 0x010 System Timer Control and status register 0x0000 0000SYST_RVR R/W 0x014 System Timer Reload value register 0x0000 0000SYST_CVR R/W 0x018 System Timer Current value register 0x0000 00004.5.1 System Timer Control and Status RegisterThe sysTick Timer Control and Status Register contains control information for the SysTick timer and provides a status flag.This register is part of the ARM Cortex-M0 core system timer register block. This register determines the clock source forthe system tick timer.Table 4-18: SysTick timer Control and Status Register (SYST_CSR - 0xE000 E010) bit descriptionBit Symbol Value Description Reset value0 ENABLE System Tick counter enable. 00 The counter is disabled.1 The counter is enabled1 TICKINT System Tick interrupt enable. 00 The System Tick interrupt is disabled.1 The System Tick interrupt is enabled.46 www.xinnovatech.com

XN12L61215:2 - Reserved. NA16 COUNTFLAG - Returns 1 if the SysTick timer counted to 0 since the last read of this register. 031:17 - - Reserved NA4.5.2 System Timer Reload Value RegisterThe System Timer Reload Value Register is set to the value that will be loaded into the SysTick timer whenever it countsdown to zero. This register is loaded by software as part of timer initialization.Table 4-19: System Timer Reload Value Register (SYST_RVR - 0xE000 E014) bit descriptionBit Symbol Description Reset value23:0 RELOAD This is the value that is loaded into the System Tick counter when it counts down to 0. 031:24 - Reserved NA4.5.3 System Timer Current Value RegisterThe System Timer Current Value Register returns the current count from the System Tick counter when it is read bysoftware.Table 4-20: System Timer Current Value Register (SYST_CVR - 0xE000 E018) bit descriptionBit Symbol Description Reset value23:0 CURRENT Reading this register returns the current value of the System Tick counter. Writing any0value clears the System Tick counter and the COUNTFLAG bit in STCTRL.31:24 Reserved NA4.5.4 Usage of System Tick TimerThe SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt. The intent is to provide a fixed 10millisecond time interval between interrupts. The SysTick timer is clocked from the CPU clock (the system clock) or from thereference clock, which is fixed to half the frequency of the CPU clock. In order to generate recurring interrupts at a specificinterval, the SYST_RVR register must be initialized with the correct value for the desired interval. The default value gives a10 millisecond interrupt rate if the CPU clock is set to 20MHz.Example:1. Program the SYST_RVR register with the reload value RELOAD to obtain the desired time interval.2. Clear the SYST_CVR register by writing to it. This ensures that the timer will count from the SYST_RVR value ratherthan an arbitrary value when the timer is enabled.3. Program the SYST_SCR register with the value 0x7 which enables the SysTick timer and the SysTick timer interrupt.The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the systemclock set to 20MHz.The system tick clock = system clock = 20MHz.RELOAD = (system tick clock frequency × 10 ms) −1= (20MHz ×10 ms) −1www.xinnovatech.com 47

XN12L612= 200000−1= 199999= 0x00030D3F4.6 System ControlXN12L612 system control includes:• System Resets• System Memory Remap• Clock control• System Tick• Interrupt source control• Power Management• Peripheral Control in system levelTable 4-21 : System Control Register SummarySymbol Access AddressoffsetBase:0x4003 8000DescriptionReset valuePCON R/W 0x000 Power control register 0x0000 0000GPREG0 R/W 0x004 General purpose register 0 0x0000 0000GPREG1 R/W 0x008 General purpose register 1 0x0000 0000GPREG2 R/W 0x00C General purpose register 2 0x0000 0000GPREG3 R/W 0x010 General purpose register 3 0x0000 0000SYSCFG R/W 0x014 System configuration registers (RTC clock control0x0000 0000and hysteresis of the WAKEUP pin).Base:0x4004 8000SYSMEMREMAP R/W 0x000 System memory remap 0x0000 0000PRESETCTRL R/W 0x004 Peripheral reset control 0x0000 FFFFSYSPLLCTRL R/W 0x008 System PLL control 0x0000 0000SYSPLLSTAT R 0x00C System PLL status 0x0000 0000- - 0x010 -Reserved -0x01CSYSOSCCTRL R/W 0x020 System oscillator control 0x0000 0000WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x0000 0000IRCCTRL R/W 0x028 IRC control 0x0000 0080- - 0x02C Reserved -SYSRESSTAT R/W 0x030 System reset status register 0x0000 0000- - 0x034 - Reserved -48 www.xinnovatech.com

XN12L6120x03CSYSPLLCLKSEL R/W 0x040 System PLL clock source select 0x0000 0000SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0x0000 0000- - 0x048 -Reserved -0x06CMAINCLKSEL R/W 0x070 Main clock source select 0x0000 0000MAINCLKUEN R/W 0x074 Main clock source update enable 0x0000 0000SYSAHBCLKDIV R/W 0x078 System AHB clock divider 0x0000 0001- - 0x07C Reserved -SYSAHBCLKCTRL R/W 0x080 System AHB clock control 0xF01F FFFF- - 0x084 - 0x094 Reserved -UART0CLKDIV R/W 0x098 UART0 clock divider 0x0000 0000UART1CLKDIV R/W 0x09C UART1 clock divider 0x0000 0000- - 0x0A0-Reserved -0x0DCCLKOUTCLKSEL R/W 0x0E0 CLKOUT clock source select 0x0000 0000CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0x0000 0000CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0x0000 0000- - 0x0ECReserved --0x0FCPIOPORCAP0 R 0x100 POR captured PIO status 0 userdependentPIOPORCAP1 R 0x104 POR captured PIO status 1 userdependentPIOPORCAP2 R 0x108 POR captured PIO status 2 userdependent- - 0x 10C -Reserved -0x130IOCONFIGCLKDIV6 R/W 0x134 Peripheral clock 6 to the IOCONFIG block for0x0000 0000programmable glitch filterIOCONFIGCLKDIV5 R/W 0x138 Peripheral clock 5 to the IOCONFIG block for0x0000 0000programmable glitch filterIOCONFIGCLKDIV4 R/W 0x13C Peripheral clock 4 to the IOCONFIG block for0x0000 0000programmable glitch filterIOCONFIGCLKDIV3 R/W 0x140 Peripheral clock 3 to the IOCONFIG block for0x0000 0000programmable glitch filterIOCONFIGCLKDIV2 R/W 0x144 Peripheral clock 2 to the IOCONFIG block for0x0000 0000programmable glitch filterIOCONFIGCLKDIV1 R/W 0x148 Peripheral clock 1 to the IOCONFIG block for0x0000 0000programmable glitch filterwww.xinnovatech.com 49

XN12L612IOCONFIGCLKDIV0 R/W 0x14C Peripheral clock 0 to the IOCONFIG block for0x0000 0000programmable glitch filterBODCTRL R/W 0x150 BOD control 0x0000 0000- - 0x154 Reserved -AHBPRIO - 0x158 AHB priority setting 0x0000 0004- - 0x15C -Reserved -0x16CIRQLATENCY R/W 0x170 IQR delay. Allows trade-off between interrupt0x0000 0010latency and determinism.INTNMI R/W 0x174 NMI interrupt source configuration control 0x0000 003F- - 0x178 -Reserved -0x1FCDSWAKECTL R/W 0x200 Deep sleep wake up control register 0x0000 0000DSWAKEEN R/W 0x204 Deep sleep wake up signal enable register 0x0000 0000DSWAKECLR W 0x208 Deep sleep wake up signal reset register 0x0000 0000DSWAKE R 0x20C Deep sleep wake up signal status register 0x0000 0000- - 0x210 -Reserved -0x22CPDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep mode 0x0000 FFFFPDAWAKECFG R/W 0x234 Power-down states after wake-up from Deep-sleep0x0000 FDF0modePDRUNCFG R/W 0x238 Power-down configuration register 0x0000 FDF0- - 0x22C ReservedUART2CLKDIV R/W 0x240 UART2 clock divider 0x0000 0000UART3CLKDIV R/W 0x244 UART3 clock divider 0x0000 00004.6.1 System ResetThe system reset can be triggered by the following events:• The Power-On Reset (POR)• The low level on the RESET# pin• Watchdog Time Out Reset• Brown-Out Detector Reset (BOD)• Software Reset• System Reset from Power-down wake upThe RESET# pin is a Schmitt trigger input pin. Assertion of Reset by any source, once the operating voltage attains a usablelevel, starts the IRC causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, andthe flash controller has completed its initialization. On the assertion of a reset source external to the Cortex-M0 CPU (POR,BOD reset, External reset, and Watchdog reset), the following processes are initiated:50 www.xinnovatech.com

XN12L612• The IRC starts up. After the IRC-start-up time, the IRC provides a stable clock output.• The boot code in the ROM starts. The boot code performs the boot tasks and may jump to the flash.When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mappedfrom the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.4.6.1.1 System Memory Remap RegisterThe System Memory Remap Register selects whether the ARM interrupt vectors are read from the boot ROM, the flash, orthe SRAM.Table 4-22: System Memory Remap Register (SYSMEMREMAP, address 0x4004 8000) bit descriptionBit Symbol Value Description Reset value1:0 MAP System memory remap. Value 0x3 is reserved. 000x00x10x2Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.User RAM Mode. Interrupt vectors are re-mapped to Static RAM.User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.31:2 - - Reserved 0x004.6.1.2 System Reset Status RegisterThe SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits.The POR event clears all other bits in this register, but if another reset signal (e.g., EXTRST) remains asserted after the PORsignal is negated, then its bit is set to detect.Table 4-23: System Reset Status Register (SYSRESSTAT, address 0x4004 8030) bit descriptionBit Symbol Value Description Reset value0 POR POR reset status 00 no POR detected1 POR detected1 EXTRST reset status 00 no RESET event detected1 RESET detected2 WDT Status of the Watchdog reset 00 no WDT reset detected1 WDT reset detected3 BOD Status of the Brown-out detect reset 00 no BOD reset detected1 BOD reset detected4 SYSRST Status of the software system reset. The ARM software reset has the same0effect as the hardware reset using the RESET# pin.0 no System reset detected1 System reset detected31:5 - - Reserved 0x00www.xinnovatech.com 51

XN12L6124.6.1.3 PIO State at System ResetThe PIO status is captured and restored into two registers when POR reset.The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0 at power-on-reset. Each bitrepresents the reset state of one GPIO pin. This register is a read-only status register.Table 4-24: POR Captured PIO Status Register 0 (PIOPORCAP0, address 0x4004 8100) bit descriptionBit Symbol Description Reset value31:0 PIO0_STAT Raw reset status input PIO0_0 to PIO0_31 User implementation dependentThe PIOPORCAP1 register captures the state (HIGH or LOW) of the PIO pins of port 1 at power-on-reset. Each bitrepresents the reset state of one PIO pin. This register is a read-only status register.Table 4-25: POR Captured PIO Status Register 1 (PIOPORCAP1, address 0x4004 8104) bit descriptionBit Symbol Description Reset value6:0 PIO1_STAT Raw reset status input PIO1_0 to PIO1_6 User implementation dependent31:7 - Reserved NAThe PIOPORCAP2 register captures the state (HIGH or LOW) of the PIO pins of port 2 at power-on-reset. Each bitrepresents the reset state of one PIO pin. This register is a read-only status register.Table 4-26: POR Captured PIO Status Register 2 (PIOPORCAP2, address 0x4004 8108) bit descriptionBit Symbol Description Reset value6:0 PIO2_STAT Raw reset status input PIO2_0 to PIO1_15 User implementation dependent31:7 - Reserved NA4.6.1.4 Software ResetThe software is able to trigger system reset by setting SYSRESETREQ bit of M0 core AIRCR register. See section SCB.4.6.1.5 PORThe built-in analog module Power-On-Reset (POR) is used to monitor power on state and issue POR signal to resetCortex-M0 core and related peripherals.4.6.1.6 BODThe BOD supports two functions to device via power supply voltage monitoring:1. Reset and hold reset to device when power supply voltage drop to 2.624V. The hysteresis voltage window is about0.135V (Typical).2. Issue BOD interrupt when power supply voltage drop to 2.828V (Typical) level. The hysteresis voltage window is 0.101V(Typical).Table 4-27: BOD control register (BODCTRL, address 0x4004 8150) bit descriptionBit Symbol Value Description Reset value3:0 - - Reserved 0x04 BODRSTENA BOD reset enable 052 www.xinnovatech.com

XN12L6120 Disable reset function.1 Enable reset function.5 - - Reserved 0x06 BODINTCLR - Write 1 to clear interrupt signal NA31:5 - - Reserved 0x04.6.2 Clock control4.6.2.1 General descriptionCompare with other MCU system, XN12L612 applies very flexible clock system. The user is able to configure MCU clock fordifferent applications to achieve the efficient power management. See following figure for an overview of the XN12L612system.XTALINXTALOUTSYS_OSCSYS_OSC_CLKSYS_PLLCLK_INPLLSystem AHBCLK DIVIDERSystem ClkARM CorePeripheralPCLKSYS_OSC_BYPASSSYS_PLLCLKIN_SELMAIN_CLKIRC_OSCIRC_OSC_CLKMAINCLK_SELSYSAHBCLKCTRLWDT_CLKWDT_OSCWDT_OSC_CLKWDT_CLK_SELINTERNALCLOCKDIVIDERSUART0/1,RTC,SysTickPCLKRTCXINRTCXOUTRTC_OSC1Hz1KHzRTCTimerRTCDIVIDERRTC_SELCLOCKOUTDIVIDERCLOCKOUTOutside-Chip-InsideCLOCKOUT_SELInside-Chip-OutsideFigure 4-4: Clock System block diagramFollowing reset, the XN12L612 will operate from the IRC oscillator until switched by software. This allows systems to operatewithout any external crystal and the boot loader code to operate at a known frequency.The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories. UART0/1/2/3 haveindividual clock dividers to derive peripheral clocks from the main clock. The watchdog clock can be derived from the WDTwww.xinnovatech.com 53

XN12L612oscillator output or the main clock. The main clock and the clock outputs from the IRC, the system oscillator, and thewatchdog oscillator can be observed directly on the CLKOUT pin.4.6.2.2 System Oscillator ControlThis register configures the frequency range for the system oscillator.Table 4-28: System Oscillator Control Register (SYSOSCCTRL, address 0x4004 8020) bit descriptionBit Symbol Value Description Reset value0 BYPASS Bypass system oscillator 00 Oscillator is not bypassed.1 Bypass enabled. PLL input (sys_osc_clk) is fed directly fromthe XTALIN and XTALOUT pins.1 FREQRANGE Determines frequency range for Low-power oscillator. 00 0.4 - 3MHz frequency range.1 3 - 16MHz frequency range31:2 - Reserved 0x004.6.2.3 Watchdog Oscillator ControlThis register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog partcontains the oscillator function and generates an analog clock (F clkana). With the digital part, the analog output clock (F clkana)can be divided to the required output clock frequency WDT_CLK. The analog output frequency (F clkana) can be adjusted withthe FREQSEL bits between 320kHz and 2.2MHz. With the digital part F clkana will be divided (divider ratios =4, 8, 16,..., 256) toWDT_CLK using the DIVSEL bits when watchdog oscillator is selected as WDT clock source (see WDT section).In this case, the output clock frequency of the watchdog clock can be calculated asWDT_CLK = F clkana/(4 × (1 + DIVSEL)) = 1.25K Hz to 550K Hz (nominal values).Note: Any setting of the FREQSEL bits will yield a F clkana value within ± 20% of the listed frequency value. The watchdog oscillator is theclock source with the lowest power consumption. If accurate timing is required, use the IRC or system clock.Note: The frequency of the watchdog oscillator is undefined after reset. The watchdog oscillator frequency must be programmed by writingto the WDTOSCCTRL register before using the watchdog oscillator.Table 4-29: Watchdog Oscillator Control Register (WDTOSCCTRL, address 0x4004 8024) bit descriptionBit Symbol Value Description Reset value4:0 DIVSEL Select divider for F clkana . 0x08:5 FREQSEL Select watchdog oscillator analog output frequency (F clkana). 0x00x10x20x30x40x50x60x70.32Hz0.6MHz0.85MHz1.04MHz1.16MHz1.28MHz1.43MHz54 www.xinnovatech.com

XN12L6120x80x90xA0xB0xC0xD0xE0xF1.52MHz1.63MHz1.7MHz1.8MHz1.92MHz2MHz2.08MHz2.2MHz31:9 - - Reserved 0x04.6.2.4 Internal Resonant Crystal ControlThis register is used to trim the on-chip 20MHz oscillator. The trimmed value is factory-preset and written by the boot codeon start-up.Table 4-30: Internal Resonant Crystal Control Register (IRCCTRL, address 0x4004 8028) bit descriptionBit value Symbol Description Reset value9:0 TRIM Trim value 0x22031:10 - Reserved 0x004.6.2.5 System PLLThe XN12L612 uses the system PLL to create the clocks for the core and peripherals.M[7:0]VCO_OUTFINFCKUPVCTRN[6:0] PFD CP VCO ODSEL[1:0]RCKDNFOUTUPDNLKDTLKDTFigure 4-5: PLL block diagramThe block diagram of this PLL is shown in Figure. The input frequency (FIN) range is 2MHz to 50MHz. The input clock is feddirectly to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generatesa control signal when phase and/ or frequency do not match. The loop filter filters these control signals and drives the currentvoltage control oscillator (VCO), which generates the main clock and optionally two additional phases. The VCO frequencyrange is 12.5MHz to 500MHz. These clocks are either divided by 2×OD by the programmable post divider to create thewww.xinnovatech.com 55

XN12L612output clock(s), or are sent directly to the output(s). The main output clock is then divided by M by the programmablefeedback divider to generate the feedback clock. The output signal of the phase-frequency detector is also monitored by thelock detector, to signal when the PLL has locked on to the input clock. The divider values for OD and M must be selected sothat the PLL output clock frequency FOUT is not higher than 100MHz.Lock detector (LKDT)The lock detector measures the phase difference between the rising edges of the input and feedback clocks. Only when thisdifference is smaller than the so called “lock criterion” for more than eight consecutive input clock periods, the lock outputswitches from low to high. A single too large phase difference immediately resets the counter and causes the lock signal todrop (if it was high). Requiring eight phase measurements in a row to be below a certain figure ensures that the lock detectorwill not indicate lock until both the phase and frequency of the input and feedback clocks are very well aligned. Thiseffectively prevents false lock indications, and thus ensures a glitch free lock signal.Power-down controlTo reduce the power consumption when the PLL clock is not needed, a Power-down mode has been incorporated. Thismode is enabled by setting the SYSPLL_PD bit to one in the Power-down configuration register. In this mode, the internalcurrent reference will be turned off, the oscillator and the phase-frequency detector will be stopped and the dividers will entera reset state. While in Power-down mode, the lock output will be low to indicate that the PLL is not in lock. When thePower-down mode is terminated by setting the SYSPLL_PD bit to zero, the PLL will resume its normal operation and willmake the lock signal high once it has regained lock on the input clock.Divider ratio programming• Post dividerThe division ratio of the post divider is controlled by the ODSEL bits. The division ratio is two times the value of ODselected by ODSEL bits as shown in PLL Control register. This guarantees an output clock with a 50% duty cycle.• Feedback dividerThe feedback divider’s division ratio is controlled by the M bits. The division ratio between the PLL’s output clock and theinput clock is the decimal value on M bits plus one, as specified in PLL Control register.• Changing the divider valuesChanging the divider ratio while the PLL is running is not recommended. As there is no way to synchronize the change ofthe M and ODSEL values with the dividers, the risk exists that the counter will read in an undefined value, which couldlead to unwanted spikes or drops in the frequency of the output clock. The recommended way of changing betweendivider settings is to power down the PLL, adjust the divider settings and then let the PLL start up again.Frequency selectionThe PLL frequency equations use the following parameters:Table 4-31: PLL frequency parametersParameterFINVCOFOUTSystem PLLFrequency of sys_pllclkin (input clock to the system PLL) from the SYSPLLCLKSEL multiplexerFrequency of the Voltage Control Oscillator (VCO); 12.5 to 500MHz.Frequency of sys_pllclkout. FOUT must be ≦100MHz.56 www.xinnovatech.com

XN12L612ODMNSystem PLL post divider ratio; ODSEL bits in SYSPLLCTRLSystem PLL feedback divider register; M bits in SYSPLLCTRLPre-divider ratio, N bits in SYSPLLCTRLIn normal mode the post divider is enabled, giving a 50% duty cycle clock with the following frequency relations:FOUT=FIN XMNX1OD=VCD2 X ODTo select the appropriate values for M and OD, it is recommended to follow these steps:1. Specify the input clock frequency FIN.2. Calculate M to obtain the desired output frequency FOUT with M = FOUT / FIN.3. Find a value so that VCO = 2 × OD × FOUT.4. Verify that all frequencies and divider values conform to the limits specified.5. Ensure that FOUT ≦100MHz.Table 4-32: PLL configuration examplesPLL input clock sys_pllclkinMain clockN valueM valueODSELP dividerVCO(FIN)(FOUT)Pre- dividerLoop dividerbitsvaluefrequency12MHz 24MHz 1 8 10 (binary) 4 192MHz12MHz 50MHz 6 100 01 (binary) 2 200MHz4.6.2.5.1 System PLL Control RegisterThis register connects and enables the system PLL and configures the PLL multiplier and divider values. The PLL acceptsan input frequency from 2MHz to 20MHz from various clock sources. The input frequency is multiplied up to a high frequency,then divided down to provide the actual clock used by the CPU, peripherals, and memories. The PLL can produce a clock upto the maximum allowed for the CPU.Table 4-33: System PLL Control Register (SYSPLLCTRL, address 0x4004 8008) bit descriptionBit Symbol Value Description Reset value7:0 M Loop divider value. The value shall be 2≦M≦255 0x014:8 N Pre-divider value. The value shall be 1≦N≦127 0x016:15 ODSEL Post divider ratio value OD 000x0 OD = 10x1 OD = 20x2 OD = 40x3 OD = 831:17 - Reserved 0x04.6.2.5.2 System PLL Status RegisterThis register is a Read-only register and supplies the PLL lock status.Table 4-34: System PLL Status Register (SYSPLLSTAT, address 0x4004 800C) bit descriptionwww.xinnovatech.com 57

XN12L612Bit Symbol Value Description Reset value0 LOCK PLL lock status 00 PLL not locked1 PLL locked31:1 - - Reserved 0x004.6.2.5.3 System PLL Clock Source Select RegisterThis register selects the clock source for the system PLL. The SYSPLLCLKUEN register must be toggled from LOW to HIGHfor the update to take effect. When switching clock sources, both clocks must be running before updating the clock source.Table 4-35: System PLL Clock Source Select Register (SYSPLLCLKSEL, address 0x4004 8040) bit descriptionBit Symbol Value Description Reset value1:0 SEL System PLL clock source 000x00x10x20x3IRC oscillatorSystem oscillatorReservedReserved31:2 - - Reserved 0x004.6.2.5.4 System PLL Clock Source Update Enable RegisterThis register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register hasbeen written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one toSYSPLLUEN.Table 4-36: System PLL Clock Source Update Enable Register (SYSPLLCLKUEN, address 0x4004 8044) bit descriptionBit Symbol Value Description Reset value0 ENA Enable system PLL clock source update 00 No change1 Update clock source31:1 - - Reserved 0x004.6.2.6 Main Clock4.6.2.6.1 Main Clock Source Select RegisterThis register selects the main system clock which can be either any input to the system PLL, the output from the system PLL(sys_pllclkout), or the watchdog or IRC oscillators directly. The main system clock clocks the core, the peripherals, and thememories. The MAINCLKUEN register must be toggled from LOW to HIGH for the update to take effect. When switchingclock sources, both clocks must be running before updating the clock source.Table 4-37: Main Clock Source Select Register (MAINCLKSEL, address 0x4004 8070) bit descriptionBit Symbol Value Description Reset value1:0 SEL Clock source for main clock 000x00x1IRC oscillatorInput clock to system PLL58 www.xinnovatech.com

XN12L6120x20x3WDT oscillatorSystem PLL clock out31:2 - - Reserved 0x004.6.2.6.2 Main Clock Source Update Enable RegisterThis register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has beenwritten to. In order for the update to take effect, first write a zero to the MAINCLKUEN register and then write a one toMAINCLKUEN.Table 4-38: Main Clock Source Update Enables Register (MAINCLKUEN, address 0x4004 8074) bit descriptionBit Symbol Value Description Reset value0 ENA Enable main clock source update 00 No change1 Update clock source31:1 - - Reserved 0x004.6.2.7 System AHB Clock Control4.6.2.7.1 System AHB Interface Clock Divider RegisterThis register divides the main clock to provide the system clock to the core, memories, and the peripherals. The system clockcan be shut down completely by setting the DIV bits to 0x0.Table 4-39: System AHB Clock Divider Register (SYSAHBCLKDIV, address 0x4004 8078) bit descriptionBit Symbol Description Reset value7:0 DIV System AHB clock divider values 0: System clock disabled.0x011: Divide by 1.to255: Divide by 255.31:8 Reserved 0x004.6.2.7.2 System AHB Interface Clock Control RegisterThe AHBCLKCTRL register enables the clocks to individual system and peripheral blocks. The system clock (bit 0 in theAHBCLKCTRL register) provides the clock for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the SYSCONblock, and the PMU. This clock cannot be disabled.Table 4-40: System AHB Clock Control Register (SYSAHBCLKCTRL, address 0x4004 8080) bit descriptionBit Symbol Value Description Reset value0 SYS Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M01FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only.0 Reserved1 Enable1 - Reserved NA2 RAM Enables clock for RAM. 10 Disablewww.xinnovatech.com 59

XN12L6121 Enable4:3 - - Reserved NA5 TWS Enables clock for TWS. 10 Disable1 Enable6 XDSP Enables clock for xDSP. 10 Disable1 Enable7 CT16B0 Enables clock for 16-bit counter/timer 0. 10 Disable1 Enable8 CT16B1 Enables clock for 16-bit counter/timer 1. 10 Disable1 Enable9 CT32B0 Enables clock for 32-bit counter/timer 0. 10 Disable1 Enable10 CT32B1 Enables clock for 32-bit counter/timer 1. 10 Disable1 Enable11 SPI Enables clock for SPI. 10 Disable1 Enable12 UART0 Enables clock for UART0. 10 Disable1 Enable13 UART1 Enables clock for UART1. 10 Disable1 Enable14 ADC0 Enables clock for ADC0 10 Disable1 Enable15 WDT Enables clock for WDT. 10 Disable1 Enable16 IOCON Enables clock for IO configuration block. 10 Disable1 Enable17 DMA Enables clock for micro DMA. 160 www.xinnovatech.com

XN12L6120 Disable1 Enable18 - - Reserved. Write as zero. 119 RTC Enables clock for RTC.10 DisableRemark: The RTC clock source must be selected before the RTC is enabledthrough this bit.1 Enable20 CMP Enables clock for comparator. 10 Disable1 Enable23:21 - - Reserved. NA24 ADC1 Enables clock for ADC1 10 Disable1 Enable25 ADC2 Enables clock for ADC2 10 Disable1 Enable26 DAC Enables clock for DAC 10 Disable1 Enable27 UART2 Enables clock for UART2 10 Disable1 Enable28 UART3 Enables clock for UART3 10 Disable1 Enable29 GPIO0 Enables clock for GPIO port 0 10 Disable1 Enable30 GPIO1 Enables clock for GPIO port 1 10 Disable1 Enable31 GPIO2 Enables clock for GPIO port 2 10 Disable1 Enablewww.xinnovatech.com 61

XN12L6124.6.2.8 UART Clock ControlThis register configures main clock to the UART0/1/2/3 peripheral clock UARTn_PCLK. The UARTn_PCLK can be shutdown by setting the DIV bits to 0x0. The UARTn pins must be configured in the IOCON block before the UARTn clock can beenabled.Table 4-41: UARTn Clock Divider Register (UART0CLKDIV, address 0x4004 8098; UART1CLKDIV, address 0x4004 809C; UART2CLKDIV,address 0x4004 8240; UART3CLKDIV, address 0x4004 8244) bit descriptionBit Symbol Value Description Reset value7:0 DIV UARTn clock divider values 0x00x00UARTn clock disabled.0x01 Divide by 1~ to0xFF Divide by 255.31:8 - Reserved 0x004.6.2.9 CLKOUT Clock Control4.6.2.9.1 CLKOUT Clock Source Select RegisterThis register configures the clkout_clk signal to be output on the CLKOUT pin. All three oscillators and the main clock can beselected for the clkout_clk clock. The CLKOUTCLKUEN register must be toggled from LOW to HIGH for the update to takeeffect.Table 4-42: CLKOUT Clock Source Select Register (CLKOUTCLKSEL, address 0x4004 80E0) bit descriptionBit Symbol Value Description Reset value1:0 SEL CLKOUT clock source 000x00x10x20x30x4IRC oscillatorSystem oscillatorWatchdog oscillatorMain clockRTC oscillator31:2 - - Reserved 0x004.6.2.9.2 CLKOUT Clock Source Update Enable RegisterThis register updates the clock source of the CLKOUT pin with the new clock after the CLKOUTCLKSEL register has beenwritten to. In order for the update to take effect at the input of the CLKOUT pin, first write a zero to the CLKCLKUEN registerand then write a one to CLKCLKUEN.Table 4-43: CLKOUT Clock Source Updates Enable Register (CLKOUTUEN, address 0x4004 80E4) bit descriptionBit Symbol Value Description Reset value0 ENA Enable CLKOUT clock source update 00 No change1 Update clock source31:1 - - Reserved 0x0062 www.xinnovatech.com

XN12L6124.6.2.9.3 CLKOUT Clock Divider RegisterThis register determines the divider value for the clkout_clk signal on the CLKOUT pin.Table 4-44: CLKOUT Clock Divider Registers (CLKOUTDIV, address 0x4004 80E8) bit descriptionBit Symbol Value Description Reset value7:0 DIV Clock divider values 00x00Clock disabled.0x01 Divide by 1~ to0xFF Divide by 255.31:8 - - Reserved 0x004.6.2.10 IOCONFIG Filter Clock ControlThese registers individually configure main clock to the seven peripheral input clocks to the IOCONFIG programmable glitchfilter. The clocks can be shut down by setting the DIV bits to 0x0.Table 4-45: IOCONFIG Filter Clock Divider Registers 0 to 6(IOCONFIGCLKDIV0 to IOCONFIGCLKDIV6, address 4004 8014C to 400480134) bit descriptionBit Symbol Value Description Reset value7:0 DIV Clock divider values 00x000x01~0xFFClock disabled.Divide by 1toDivide by 255.31:8 - - Reserved 0x004.6.3 Power ManagementThe XN12L612 support a variety of power control features. In Active mode, when the microcontroller is running, power andclocks to selected peripherals can be optimized for power consumption. In addition, there are three special modes ofprocessor power reduction: Sleep mode, Deep-sleep mode, and Power-down mode. The Debug mode is not supported inSleep, Deep-sleep, or Power-down modes.Table 4-46: System power and clock management in different modeModuleGroupModule/BlockActive Mode Sleep Mode Deep-Sleep Mode Power Down ModeClock Power Clock Power Clock Power Clock PowerCore M0 - ON Stopped ON Stopped ON Stopped OFFMemory SRAM - ON Stopped ON Stopped ON Stopped OFFFLASH - ON Stopped ON Stopped ON Stopped OFFAnalog IRCOUT - PDRUNCFG - PDRUNCFG - OFF - OFFIRC - PDRUNCFG - PDRUNCFG - OFF - OFFBOD - PDRUNCFG - PDRUNCFG - PDSLEEPCFG - OFFADC0 - PDRUNCFG - PDRUNCFG - OFF - OFFwww.xinnovatech.com 63

XN12L612DAC - PDRUNCFG - PDRUNCFG - OFF - OFFSYSOSC - PDRUNCFG - PDRUNCFG - OFF - OFFWDTOSC - PDRUNCFG - PDRUNCFG - PDSLEEPCFG - OFFSYSPLL - PDRUNCFG - PDRUNCFG - OFF - OFFADC1 - PDRUNCFG - PDRUNCFG - OFF - OFFADC2 - PDRUNCFG - PDRUNCFG - OFF - OFFRTCOSC - PDRUNCFG - PDRUNCFG - PDSLEEPCFG - PDSLEEPCFGCOMP - PDRUNCFG - PDRUNCFG - OFF - OFFDigital TWS AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFxDSP AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFCT16B0 AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFCT16B1 AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFCT32B0 AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFCT32B1 AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFSPI AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFUART0,1,AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFF2,3ADC0,1,2AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFF/DACWDT AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFIOCON AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFDMA AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFRTC AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - ONCMP AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFGPIO0 AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFGPIO1 AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFGPIO2 AHBCLKCTRL ON AHBCLKCTRL ON AHBCLKCTRL ON - OFFWakeup WAKEUP - - - - - - - ON4.6.3.1 Power Control RegisterThe power control register selects whether one of the ARM Cortex-M0 controlled power saving modes (Sleep mode orDeep-sleep mode) or the Power-down mode, and provides the flags for Sleep or Deep-sleep modes and Power-downmodes respectively.Table 4-47: Power Control Register (PCON, address 0x4003 8000) bit descriptionBit Symbol Value Description Reset value0 - - Reserved. 0x01 DPDEN Power-down mode enable 0x00 ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M0 coreturned off).64 www.xinnovatech.com

XN12L6121 ARM WFI will enter Power down mode (ARM Cortex-M0 core powered-down) ifWDLOCKDP = 07:2 - - Reserved. 0x08 SLEEPFLAG Sleep mode flag 0x00 Read: No Sleep/Deep-sleep or Power-down mode entered.Write: No effect.1 Read: Sleep/Deep-sleep or Power-down mode entered.Write: Writing a 1 clears the SLEEPFLAG bit to 0.10:9 - - Reserved. Do not write ones to this bit. 0x011 DPDFLAG Power-down flag 0x00 Read: Power-down mode not entered. Write: No effect. 0x01 Read: Power-down mode entered.0x0Write: Clear the Power-down flag.31:12 - - Reserved. Do not write ones to this bit. 0x04.6.3.2 General Data Registers 0 to 3The general purpose registers retain data through the Power-down mode when power is still applied to the V DD(3V3) pin butthe chip has entered Power-down mode. Only a “cold” boot when all power has been completely removed from the chip willreset the general purpose registers.Table 4-48: General Data Registers 0 to 3 (GPREG0 - GPREG3, address 0x4003 8004 to 0x4003 8010) bit descriptionBit Symbol Description Reset value31:0 GPDATA Data retained during Power-down mode. 0x04.6.3.3 WAKEUP and RTC Configuration RegisterThis register controls the clock input to the RTC and the hysteresis of the WAKEUP pin. Three clocks can be selected fromthe 32 kHz RTC oscillator: the 1 Hz clock (default) and the 1 kHz clock. In addition, the peripheral RTC clock, which isderived from the main clock by the RTC clock divider, can be selected as RTC clock source. The RTC clock source must beselected before the RTC is enabled in the SYSAHBCLKCTRL register. The clock source must not be changed while the RTCis running. If the external voltage applied on pin V DD drops below BOD reset voltage level, the hysteresis of the WAKEUPinput pin has to be disabled in order for the chip to wake up from Power-down mode.Table 4-49: System Configuration Register (SYSCFG, address 0x4003 8014) bit descriptionBit Symbol Value Description Reset value9:0 - - Reserved. 0x010 WAKEUPHYS WAKEUP pin hysteresis enable 0x00 Hysteresis for WAKUP pin disabled.1 Hysteresis for WAKEUP pin enabled.12:11 RTCCLK RTC clock source select 000000 1 Hz clock01 IRC clock10 1 kHz clockwww.xinnovatech.com 65

XN12L61211 RTC PCLK31:15 - - Reserved. 0x04.6.3.4 Deep-sleep Configuration RegisterWhen the device is in Deep-sleep mode, all analog modules of device are power down. However, the RTC oscillator, theWatchDog and the BOD may work as application requirement. This register controls the behavior of the RTC oscillator, theWatchDog (WD) oscillator and the BOD circuit when the device enters Deep-sleep mode. In addition, the WD oscillatorbehavior is influenced by the WDLOCKCLK bit in the WDMODE register. All other analog blocks are shut down inDeep-sleep mode.Table 4-50: Deep-sleep Configuration Register (PDSLEEPCFG, address 0x4004 8230) bit descriptionBit Symbol Value Description Reset value2:0 - Reserved. Always write these bits as ones. 1113 BOD_PD BOD power-down control in Deep-sleep mode 10 Powered1 Powered down5:4 - Reserved. Always write these bits as ones. 116 WDTOSC_PD Watchdog oscillator power-down control in Deep-sleep mode 10 Powered1 Powered down. Must be changed to 0 before the WDLOCKCLK bit isset in the WDMODE register.11:7 - - Reserved 1111112 RTCOSC_PD RTC oscillator power-down 00 Powered1 Powered down15:13 - - Reserved 11131:16 - - Reserved 04.6.3.5 Wake-up Configuration RegisterThe bits in this register can be programmed to indicate the state the microcontroller must enter when it is waking up fromDeep-sleep mode.Table 4-51: Wake-up Configuration Register (PDAWAKECFG, address 0x4004 8234) bit descriptionBit Symbol Value Description Reset value0 IRCOUT_PD IRC oscillator output power-down 00 Powered1 Powered down1 IRC_PD IRC oscillator power-down 00 Powered1 Powered down2 - - Reserved 03 BOD_PD BOD power-down 066 www.xinnovatech.com

XN12L6120 Powered1 Powered down4 ADC0_PD ADC power-down 10 Powered1 Powered down5 SYSOSC_PD System oscillator power-down 10 Powered1 Powered down6 WDTOSC_PD Watchdog oscillator power-down 10 Powered1 Powered down7 SYSPLL_PD System PLL power-down 10 Powered1 Powered down8 - - Reserved 19 ADC1_PD ADC1 converter power-down 10 Powered1 Powered down10 ADC2_PD ADC2 converter power-down 10 Powered1 Powered down11 DAC_PD DAC converter power-down 10 Powered1 Powered down12 RTCOSC_PD RTC oscillator power-down 00 Powered1 Powered down14:13 - - Reserved 1115 COMP_PD Comparator power-down 10 Powered1 Powered down31:16 - Reserved - 04.6.3.6 Power-down Configuration RegisterThe bits in the PDRUNCFG register control the power to the various analog blocks. This register can be written to at anytime while the microcontroller is running, and a write will take effect immediately with the exception of the power-down signalto the IRC.To avoid glitches when powering down the IRC, the IRC clock is automatically switched off at a clean point. Therefore, forthe IRC a delay is possible before the power-down state takes effect.Note: Settings in this register are affected by the WDT lock status:www.xinnovatech.com 67

XN12L612• If the watchdog oscillator is selected as the clock source for the WDT, writes to bit 6 in the PDRUNCFG register are ignored if at thesame time bit 5 is set in the MOD register.• If the IRC is selected as the clock source for the WDT, writes to bits 0 and bit 1 in the PDRUNCFG register are ignored if at the sametime bit 5 is set in the MOD register.Table 4-52: Power-down Configuration Register (PDRUNCFG, address 0x4004 8238) bit descriptionBit Symbol Value Description Reset value0 IRCOUT_PD IRC oscillator output power-down 00 Powered1 Powered down1 IRC_PD IRC oscillator power-down 00 Powered1 Powered down2 - - Reserved 03 BOD_PD BOD power-down 00 Powered1 Powered down4 ADC0_PD ADC power-down 10 Powered1 Powered down5 SYSOSC_PD System oscillator power-down 10 Powered1 Powered down6 WDTOSC_PD Watchdog oscillator power-down 10 Powered1 Powered down7 SYSPLL_PD System PLL power-down 10 Powered1 Powered down8 - - Reserved 19 ADC1_PD ADC1 converter power-down 10 Powered1 Powered down10 ADC2_PD ADC2 converter power-down 10 Powered1 Powered down11 DAC_PD DAC converter power-down 10 Powered1 Powered down12 RTCOSC_PD RTC oscillator power-down 068 www.xinnovatech.com

XN12L6120 Powered1 Powered down14:13 - - Reserved 1115 COMP_PD Comparator power-down 10 Powered1 Powered down31:16 - - Reserved 04.6.3.7 Active ModeIn Active mode, the ARM Cortex-M0 core and memories are clocked by the system clock, and peripherals are clocked bythe system clock or a dedicated peripheral clock. The microcontroller is in Active mode after reset and the default powerconfiguration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The powerconfiguration can be changed during run time.Power consumption in Active mode is determined by the following configuration choices:• The SYSAHBCLKCTRL register controls which memories and peripherals are running.• The power to various analog blocks (PLL, oscillators, the ADC, the BOD circuit, and the flash block) can be controlled atany time individually through the PDRUNCFG register.• The clock source for the system clock can be selected from the IRC (default), the system oscillator, or the watchdogoscillator.• The system clock frequency can be selected by the SYSPLLCTRL and the SYSAHBCLKDIV register.• Selected peripherals (UART0/1/2/3, WDT) use individual peripheral clocks with their own clock dividers. The peripheralclocks can be shut down through the corresponding clock divider registers.4.6.3.8 Sleep ModeIn Sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of instructions is suspended untileither a reset or an enabled interrupt occurs.For peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue operation during Sleep modeand may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used bythe processor itself, memory systems and their related controllers, and internal buses. The processor state and registers,peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static.Power Configuration in Sleep ModePower consumption in Sleep mode is configured by the same settings as in Active mode:• The clock remains running.• The system clock frequency remains the same as in Active mode, but the processor is not clocked.• Analog and digital peripherals are selected as in Active mode.Enter Sleep ModeThe following steps must be performed to enter Sleep mode:www.xinnovatech.com 69

XN12L6121. The DPDEN bit in the PCON register must be set to zero.2. The SLEEPDEEP bit in the ARM Cortex-M0 SCR register must be set to zero.3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction.Wake-up from Sleep ModeSleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. Afterwake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of thePDRUNCFG and the SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default configuration inActive mode.4.6.3.9 Deep-sleep ModeIn Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down,except for the BOD circuit and the watchdog oscillator, which must be selected or deselected during Deep-sleep mode in thePDSLEEPCFG register. The RTC and the RTC oscillator are operating in Deep-sleep mode unless the RTC is powereddown. Deep-sleep mode eliminates all power used by the flash, analog peripherals and all dynamic power used by theprocessor itself, memory systems and their related controllers, and internal buses. The processor state and registers,peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static.Power Configuration in Deep-sleep ModePower consumption in Deep-sleep mode is determined by the Deep-sleep power configuration setting in the PDSLEEPCFGregister:• Except for the RTC oscillator, the only clock source available in Deep-sleep mode is the watchdog oscillator. Thewatchdog oscillator can be left running in Deep-sleep mode if required for peripheral-controlled wake-up. All other clocksources (the IRC and system oscillator) and the system PLL are shut down. The watchdog oscillator analog outputfrequency must be set to the lowest value of its analog clock output.• The BOD circuit can be left running in Deep-sleep mode if required by the application.• If the watchdog oscillator is running in Deep-sleep mode, only the watchdog timer should be enabled inSYSAHBCLKCTRL register to minimize power consumption.• The RTC and the RTC oscillator can be left running in Deep-sleep mode.Enter Deep-sleep ModeThe following steps must be performed to enter Deep-sleep mode:1. The DPDEN bit in the PCON register must be set to zero.2. Select the power configuration in Deep-sleep mode in the PDSLEEPCFG register.a) For peripheral controlled wake-up, ensure that the watchdog oscillator is powered in the PDRUNCFG register andswitch the clock source to WD oscillator in the MAINCLKSEL register.b) Without peripheral controlled wake-up and if the watchdog oscillator is shut down, ensure that the IRC is poweredin the PDRUNCFG register and switch the clock source to IRC in the MAINCLKSEL register. This ensures that thesystem clock is shut down glitch-free.70 www.xinnovatech.com

XN12L6123. Select the power configuration after wake-up in the PDAWAKECFG register.4. Configure the Deep-sleep wake up pin control:– If an external pin is used for wake-up, enable and clear the wake-up pin in the Deep-sleep wake up control registers,and enable the wake pin interrupt in the NVIC.– If the RTC is used, enable the RTC interrupt in the NVIC.5. In the SYSAHBCLKCTRL register, disable all peripherals except RTC or WDT if needed.6. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register.7. Use the ARM WFI instruction.Wake-up from Deep-sleep ModeThe microcontroller can wake up from Deep-sleep mode in the following ways:• Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 can be enabled as inputs to the wake up control.The Deep-sleep wake up control does not require any clocks and generates the interrupt if enabled in the NVIC towake up from Deep-sleep mode.• RTC match interrupt for self-timed wake-up.• Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the PDSLEEPCFG register, and the BODreset must be enabled in the BODCTRL register.• Reset from the watchdog timer. In this case, the watchdog oscillator must be running in Deep-sleep mode (seePDSLEEPCFG register), and the WDT must be enabled in the SYSAHBCLKCTRL register.• External RESET pin.Using External Pins to Wake Up from Deep-sleep Mode (Deep-sleep Wake Up Control)The Deep-sleep mode is exited when the Deep-sleep wake up control indicates an interrupt to the ARM core. The port pinsPIO0_0 to PIO0_11 are connected to the Deep-sleep wake up control and serve as wake-up pins. The user must programthe Deep-sleep wake up registers for each input to set the appropriate edge polarity for the corresponding wake-up event.Furthermore, the interrupts corresponding to each input must be enabled in the NVIC. Interrupts 0 to 3 in the NVICcorrespond to 11 PIO pins.The Deep-sleep wake up control does not require a clock to run because it uses the input signals on the enabled pins togenerate a clock edge. Therefore, the Deep-sleep wake up signals should be cleared before use.The Deep-sleep wake up control can also be used in Active mode to provide a vectored interrupt using the XN12L612’s inputpins.Using the RTC to Wake Up from Deep-sleep ModeThe RTC is clocked by the independent RTC oscillator and continues to run in Deep-sleep mode. The RTC interrupt must beenabled in the NVIC.4.6.3.10 Power-down ModeIn Power-down mode, power and clocks are shut off to the entire microcontroller with the exception of the WAKEUP pin. Themicrocontroller is blocked from entering Power-down mode when the WDLOCKDP bit is set to one in the WDMODE register.www.xinnovatech.com 71

XN12L612If the RTC is enabled before entering Power-down mode, the RTC and the RTC oscillator continue to run in Power-downmode. If the RTC is not needed in Power-down mode, disable the RTC to minimize power consumption.During Power-down mode, the contents of the SRAM and registers are not retained except for a small amount of data whichcan be stored in four 32-bit general purpose registers of the PMU block.Power Configuration in Power-down ModePower-down mode has no configuration options. All clocks, the core, and all peripherals except for the RTC and the RTCoscillator are powered down. Only the WAKEUP pin and the backup registers are powered. The low-power RTC and theRTC oscillator can be left running (this is the default).Enter Power-down ModeThe microcontroller can only enter Power down mode if the WDLOCKDP bit is set to 0 in the WDMODE register. IfWDLOCKDP = 1, the microcontroller must be reset before the Power-down mode can be entered. And the WAKEUP pinmust be pulled HIGH externally before entering Power-down mode.The following steps must be performed to enter Power-down mode:1. Write one to the DPDEN bit in the PCON register.2. Store data to be retained in the general purpose registers.3. Write one to the SLEEPDEEP bit in the ARM Cortex-M0 SCR register.4. Ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in the PDRUNCFG register beforeentering Power-down mode.5. Use the ARM WFI instruction.Wake-up from Power-down ModeWaking up from Power-down mode causes the microcontroller to reset. However, the contents of the RTC registers and thebackup registers are conserved. XN12L612 can wake up from Power-down mode in two ways:• Pulling the WAKEUP pin LOW wakes up XN12L612 from Power-down. The minimum pulse width for the HIGH-to-LOWtransition on the WAKEUP pin is 50 ns.• An RTC interrupt wakes up XN12L612 from Power-down mode.Note: The RESET pin has no functionality in Power-down mode.Using the WAKEUP Pin to Wake Up from Power-down ModePulling the WAKEUP pin LOW wakes up XN12L612 from Power-down, and the microcontroller goes through the entire resetprocess. The minimum pulse width for the HIGH-to-LOW transition on the WAKEUP pin is 50 ns.Follow these steps to wake up the microcontroller from Power-down mode using the WAKEUP pin:1. Generate a wake-up signal by going HIGH-to-LOW externally on the WAKEUP pin with a pulse length of at least 50nswhile the part is in Power-down mode.– The PMU will turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR) trippoint, a system reset will be triggered and the microcontroller re-boots.– All registers except the GPREG0 to GPREG3 will be in their reset state.72 www.xinnovatech.com

XN12L612– The contents of the RTC registers will be preserved if the RTC is enabled.2. Once the microcontroller has booted, read the power-down flag in the PCON register to verify that the reset wascaused by a wake-up event from power-down.3. Clear the power-down flag in the PCON register.4. (Optional) Read the stored data in the general purpose registers.5. Set up the PMU for the next Power-down cycle.Using the RTC to Wake Up from Power-down ModeAn RTC interrupt wakes up the microcontroller from Power-down mode in the same way the WAKEUP pin does. Thewake-up signal is generated when an RTC interrupt is created after a programmed number of clocks.To use the RTC wake-up interrupt, the RTC must be configured as follows:• Program the RTC match register with the RTC timer match value.• Clear the interrupt mask in the RTC interrupt mask register.• The clock source for the RTC must be the RTC oscillator.Follow these steps to wake up from Power-down mode using the RTC:1. Generate a self-timed RTC wake-up interrupt by setting the RTC match register.–-The PMU will turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR) trippoint, a system reset will be triggered and the microcontroller re-boots.–-All registers except the GPREG0 to GPREG3 will be in their reset state.–-The contents of the RTC registers will be preserved.2. Once the microcontroller has booted, read the power-down flag in the PCON register to verify that the reset wascaused by a wake-up event from Power-down.3. Clear the power-down flag in the PCON register.4. Read the content of the General Purpose registers if needed.5. Read the RTC count.6. (Optional) Clear the RTC interrupt in the RTC ICR register and the pending interrupt in the NVIC.7. (Optional) Read the stored data in the general purpose registers.8. Set up the PMU for the next Power-down cycle.4.6.4 Deep-sleep Wake Up ControlXN12L612 provides a set of control registers to allow external pin wake chip from deep sleep. Deep-sleep wake up controlRegister is used for external pin wake up configuration.4.6.4.1 Deep-sleep Wake Up Control RegisterThe DSWAKECTL register controls the wake up inputs of ports 0 (PIO0_0 to PIO0_11). This register selects a falling orrising edge on the corresponding PIO input to produce a falling or rising clock edge, respectively, for the Deep-sleep wakewww.xinnovatech.com 73

XN12L612up. Every bit in the DSWAKECTL register controls one port input and is connected to one wake-up interrupt in the NVIC. Bit0/4/8 in the DSWAKECTL register corresponds to interrupt 0. Bit 1/5/9 in the DSWAKECTL register corresponds to interrupt1. Bit 2/6/10 in the DSWAKECTL register corresponds to interrupt 2. Bit 3/7/11 in the DSWAKECTL register corresponds tointerrupt 3. Through this register set, external pins can be used to wake up the microcontroller from Deep-sleep mode. Eachinterrupt connected to an input must be enabled in the NVIC if the corresponding PIO pin is used to wake up themicrocontroller from Deep-sleep mode.Table 4-53: Deep-sleep Wake Up Control Register (DSWAKECTL, address 0x4004 8200) bit descriptionBit Symbol Description Reset value0 CTLPIO0_0 Edge select for wake up on pin PIO0_0 to trigger interrupt 0.00 = Falling edge1 = Rising edge1 CTLPIO0_1 Edge select for wake up on pin PIO0_1 to trigger interrupt 1.00 = Falling edge1 = Rising edge2 CTLPIO0_2 Edge select for wake up on pin PIO0_2 to trigger interrupt 2.00 = Falling edge1 = Rising edge3 CTLPIO0_3 Edge select for wake up on pin PIO0_3 to trigger interrupt 3.00 = Falling edge1 = Rising edge4 CTLPIO0_4 Edge select for wake up on pin PIO0_4 to trigger interrupt 0.00 = Falling edge1 = Rising edge5 CTLPIO0_5 Edge select for wake up on pin PIO0_5 to trigger interrupt 1.00 = Falling edge1 = Rising edge6 CTLPIO0_6 Edge select for wake up on pin PIO0_6 to trigger interrupt 2.00 = Falling edge1 = Rising edge7 CTLPIO0_7 Edge select for wake up on pin PIO0_7 to trigger interrupt 3.00 = Falling edge1 = Rising edge8 CTLPIO0_8 Edge select for wake up on pin PIO0_8 to trigger interrupt 0.00 = Falling edge1 = Rising edge9 CTLPIO0_9 Edge select for wake up on pin PIO0_9 to trigger interrupt 1.00 = Falling edge1 = Rising edge10 CTLPIO0_10 Edge select for wake up on pin PIO0_10 to trigger interrupt 2.00 = Falling edge74 www.xinnovatech.com

XN12L6121 = Rising edge11 CTLPIO0_11 Edge select for wake up on pin PIO0_11 to trigger interrupt 3.00 = Falling edge1 = Rising edge31:12 - Reserved - 04.6.4.2 Deep-sleep Wake Up Signal Enable RegisterThis DSWAKEEN register enables or disables the start signal bits in the Deep-sleep wake up.Table 4-54: Deep-sleep Wake Up Signal Enable Register(DSWAKEEN, address 0x4004 8204) bit descriptionBit Symbol Description Reset -Value0 ERPIO0_0 Enable pin PIO0_0 wake up function.00 = Disabled.1 = Enabled.1 ERPIO0_1 Enable pin PIO0_1 wake up function.00 = Disabled.1 = Enabled.2 ERPIO0_2 Enable pin PIO0_2 wake up function.00 = Disabled.1 = Enabled.3 ERPIO0_3 Enable pin PIO0_3 wake up function.00 = Disabled.1 = Enabled.4 ERPIO0_4 Enable pin PIO0_4 wake up function.00 = Disabled.1 = Enabled.5 ERPIO0_5 Enable pin PIO0_5 wake up function.00 = Disabled.1 = Enabled.6 ERPIO0_6 Enable pin PIO0_6 wake up function.00 = Disabled.1 = Enabled.7 ERPIO0_7 Enable pin PIO0_7 wake up function.00 = Disabled.1 = Enabled.8 ERPIO0_8 Enable pin PIO0_8 wake up function.00 = Disabled.1 = Enabled.9 ERPIO0_9 Enable pin PIO0_9 wake up function.00 = Disabled.1 = Enabled.www.xinnovatech.com 75

XN12L61210 ERPIO0_10 Enable pin PIO0_10 wake up function.00 = Disabled.1 = Enabled.11 ERPIO0_11 Enable pin PIO0_11 wake up function.00 = Disabled.1 = Enabled.31:12 Reserved4.6.4.3 Deep-sleep Wake Up Signal Reset RegisterWriting a one to a bit in the DSWAKECLR register resets the Deep-sleep wake up signal state. The Deep-sleep wake upuses the input signals to generate a clock edge for registering a wake up signal. This clock edge (falling or rising) sets theinterrupt for waking up from Deep-sleep mode. Therefore, the Deep-sleep wake up signal states must be cleared beforebeing used.Table 4-55: Deep-sleep Wake Up Reset Register (DSWAKECLR, address 0x4004 8208) bit descriptionBit Symbol Description Reset value0 RSRPIO0_0 Wake up signal reset for pin PIO0_0.00 = No effect.1 = Write: reset wake up signal.1 RSRPIO0_1 Wake up signal reset for pin PIO0_1.00 = No effect.1 = Write: reset wake up signal.2 RSRPIO0_2 Wake up signal reset for pin PIO0_2.00 = No effect1 = Write: reset wake up signal.3 RSRPIO0_3 Wake up signal reset for pin PIO0_3.00 = No effect.1 = Write: reset wake up signal.4 RSRPIO0_4 Wake up signal reset for pin PIO0_4.00 = No effect.1 = Write: reset wake up signal.5 RSRPIO0_5 Wake up signal reset for pin PIO0_5.00 = No effect.1 = Write: reset wake up signal.6 RSRPIO0_6 Wake up signal reset for pin PIO0_6.00 = No effect.1 = Write: reset wake up signal.7 RSRPIO0_7 Wake up signal reset for pin PIO0_7.00 = No effect.1 = Write: reset wake up signal.8 RSRPIO0_8 Wake up signal reset for pin PIO0_8.00 = No effect.76 www.xinnovatech.com

XN12L6121 = Write: reset wake up signal.9 RSRPIO0_9 Wake up signal reset for pin PIO0_9.00 = No effect.1 = Write: reset wake up signal.10 RSRPIO0_10 Wake up signal reset for pin PIO0_10.00 = No effect.1 = Write: reset wake up signal.11 RSRPIO0_11 Wake up signal reset for pin PIO0_11.00 = No effect.1 = Write: reset wake up signal.31:12 - Reserved -4.6.4.4 Deep-sleep Wake Up Signal Status RegisterThis register reflects the status of the enabled wake up signal bits. Each bit (if enabled) reflects the state of the Deep-sleepwake up signal, i.e. whether or not a wake-up signal has been received for a given pin.Table 4-56: Deep-sleep Wake Up Signal Status Register (DSWAKE, address 0x4004 820C) bit descriptionBit Symbol Description Reset value0 SRPIO0_0 Wake up signal status for PIO0_0.00 = No wake up signal received.1 = Wake up signal pending.1 SRPIO0_1 Wake up signal status for PIO0_1.00 = No wake up signal received.1 = Wake up signal pending.2 SRPIO0_2 Wake up signal status for PIO0_2.00 = No wake up signal received.1 = Wake up signal pending.3 SRPIO0_3 Wake up signal status for PIO0_3.00 = No wake up signal received.1 = Wake up signal pending.4 SRPIO0_4 Wake up signal status for PIO0_4.00 = No wake up signal received.1 = Wake up signal pending.5 SRPIO0_5 Wake up signal status for PIO0_5.00 = No wake up signal received.1 = Wake up signal pending.6 SRPIO0_6 Wake up signal status for PIO0_6.00 = No wake up signal received.1 = Wake up signal pending.7 SRPIO0_7 Wake up signal status for PIO0_7.00 = No wake up signal received.1 = Wake up signal pending.www.xinnovatech.com 77

XN12L6128 SRPIO0_8 Wake up signal status for PIO0_8.00 = No wake up signal received.1 = Wake up signal pending.9 SRPIO0_9 Wake up signal status for PIO0_9.00 = No wake up signal received.1 = Wake up signal pending.10 SRPIO0_10 Wake up signal status for PIO0_10.00 = No wake up signal received.1 = Wake up signal pending.11 SRPIO0_11 Wake up signal status for PIO0_11.00 = No wake up signal received.1 = Wake up signal pending.31:12 - Reserved -4.6.5 Miscellaneous4.6.5.1 Peripheral Reset Control RegisterThis register allows software to reset individual peripherals. If a bit in this register is set to 0, the corresponding peripheral iskeep to reset. Writing a 1 de-asserts the reset. Bit 15 of this register overwrites the flash timing for read access.Table 4-57: Peripheral Reset Control Register (PRESETCTRL, address 0x4004 8004) bit descriptionBit Symbol Value Description Reset value0 SPI_RST_N SPI reset control 10 SPI reset enabled1 SPI reset de-asserted1 TWS_RST_N TWS reset control 10 TWS reset enabled1 TWS reset de-asserted2 UART0_RST_N UART0 reset control 10 UART0 reset enabled1 UART0 reset de-asserted3 UART1_RST_N UART1 reset control 10 UART1 reset enabled1 UART1 reset de-asserted4 CT16B0_RST_N 16-bit counter/timer 0 (CT16B0) reset control 10 CT16B0 reset enabled1 CT16B0 reset de-asserted5 CT16B1_RST_N 16-bit counter/timer 1 (CT16B1) reset control 10 CT16B1 reset enabled1 CT16B1 reset de-asserted6 CT32B0_RST_N 32-bit counter/timer 0 (CT32B0) reset control 178 www.xinnovatech.com

XN12L6120 CT32B0 reset enabled1 CT32B0 reset de-asserted7 CT32B1_RST_N 32-bit counter/timer 1 (CT32B1) reset control 10 CT32B1 reset enabled1 CT32B1 reset de-asserted8 CMP_RST_N Comparator reset control 10 Comparator reset enabled1 Comparator reset de-asserted9 XDSP_RST_N xDSP reset control 10 xDSP reset enabled1 xDSP reset de-asserted10 DMA_RST_N Micro DMA reset control 10 DMA reset enabled1 DMA reset de-asserted13:11 - - Reserved. 1 1114 ADC0_RST_N ADC00 ADC0 reset enabled1 ADC0 reset de-asserted115 ADC1_RST_N ADC10 ADC1 reset enabled1 ADC1 reset de-asserted116 - - -Reserved. 117 DAC_RST_N DAC0 DAC reset enabled1 DAC reset de-asserted118 UART2_RST_N UART20 UART2 reset enabled1 UART2 reset de-asserted119 UART3_RST_N UART30 UART3 reset enabled1 UART3 reset de-asserted131:20 - Reserved 0x04.7 I/O configurationTo do pin multiplex for different application requirement, XN12L612 is designed with one IOCON register for each pinassignment. The I/O configuration registers control the electrical characteristics of the pads. The following features areprogrammable:• Pin functionwww.xinnovatech.com 79

XN12L612• Pin mode: Internal pull-up, open-drain mode,• Pin drive• Analog input or digital mode for pads hosting the ADC inputs• IO pin glitch filter4.7.1 General Description of IOCON RegisterThe following table shows the register bit allocation for all IOCON registers (except PIO0_10 and PIO0_11).Table 4-58: IOCON register bit allocation (except TWS-pins)Bit Symbol Value Description Reset value2:0 FUNC Selects pin function. 000000 Selects function 0 (default).001 Select function 1.010 Select function 2.011 Select function 3.100 Select function 4.101 Select function 5.110 Select function 6.111 Reserved.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Disable.1 Open-drain mode enabled. Remark: This is not a true open-drain mode. Inputcannot be pulled up above V DD (IO).12:11 S_MODE Sample mode 0080 www.xinnovatech.com

XN12L6120x00x1Bypass input filter.Sampling for 1 filter clock cycle. Input pulses shorter than one filter clock arerejected.0x2Sampling for 2 filter clock cycles. Input pulses shorter than two filter clocks arerejected.0x3Sampling for 3 filter clock cycles. Input pulses shorter than three filter clocks arerejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x60x7IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.Reserved31:16 - - Reserved. 04.7.1.1 Pin FunctionThe FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a peripheral function. If the pins areconfigured as GPIO pins, the DIR registers determine whether the pin is configured as an input or output. For any peripheralfunction, the pin direction is controlled automatically depending on the pin’s functionality. The GPIOnDIR registers have noeffect for peripheral functions.4.7.1.2 Pin ModeThe MODE bit in the IOCON register allows enabling or disabling an on-chip pull-up resistor for each pin. By default allpull-up resistors are enabled except for the TWS pins PIO0_10 and PIO0_11, which do not have a programmable pull-upresistor.4.7.1.3 Pin DriveTwo levels of output drive can be selected for each normal-drive pin, named low mode and high mode. Four pins (PIO0_27,PIO0_28, PIO0_29, PIO0_12) are designated high-drive pins with a high mode and low mode output drive.4.7.1.4 Open-drain ModeAn open-drain mode can be enabled for all digital I/O pins. Except for pins PIO0_10 and PIO0_11, this mode is not a trueopen-drain mode. The input cannot be pulled up above V DD (IO) .4.7.1.5 A/D-modeIn A/D-mode, the digital receiver is disconnected to obtain an accurate input voltage for analog-to-digital conversions. Thismode is available in those IOCON registers that control pins which can function as ADC inputs. If A/D mode is selected, thepin mode setting has no effect.www.xinnovatech.com 81

XN12L6124.7.1.6 TWS Mode (I2C Compatible)The TWS pins PIO0_10 and PIO0_11 can be programmed to support a true open-drain mode independently of whether theTWS function is selected or another digital function. If the TWS function is selected, all three TWS modes, Standard mode,Fast-mode, and Fast-mode plus, are supported. A digital glitch filter can be configured for all functions. Pins PIO0_10 andPIO0_11 operate as high-current sink drivers (20mA) independently of the programmed function.4.7.1.7 Programmable Glitch FilterAll PIO pins are equipped with a programmable, digital glitch filter. The filter rejects input pulses with a selectable duration ofshorter than one, two, or three cycles of a filter clock (S_MODE = 1, 2, or 3). The filter clock can be selected from one ofseven peripheral clocks PCLK0 to 6, which are derived from the main clock using the IOCONFIGCLKDIV0 to 6 registers.The filter can also be bypassed entirely.Any input pulses of duration T pulse of either polarity will be rejected if:t pulse < t PCLKn × S_MODEInput pulses of one filter clock cycle longer may also be rejected:t pulse < t PCLKn × (S_MODE + 1)Note: The filtering effect is accomplished by requiring that the input signal be stable for (S_MODE +1) successive edges of the filter clockbefore being passed on to the chip. Enabling the filter results in delaying the signal to the internal logic and should be done only if specificallyrequired by an application. For high-speed or time critical functions, for example the timer captures inputs or the SPI function; ensure thatthe filter is bypassed. If the delay of the input signal must be minimized, select a faster PCLK and a higher sample mode (S_MODE) tominimize the effect of the potential extra clock cycle. If the sensitivity to noise spikes must be minimized, select a slower PCLK and lowersample mode.4.7.2 IOCON Register ListTable 4-59: Register overview: I/O configuration block (base address 0x4004 4000)Symbol Access AddressoffsetDescriptionReset value- R/W 0x000 Reserved. -- R/W 0x004 Reserved. -PIO0_19 R/W 0x008 Configures pin PIO0_19/ACMP0_I0/CT32B0_CAP1/CT32B0_MAT1 0x0000 0090PIO0_20 R/W 0x00C Configures pin PIO0_20/ACMP0_I1/CT32B0_CAP2/CT32B0_MAT2 0x0000 0090PIO0_21 R/W 0x010 Configures pin PIO0_21/ACMP0_I2/CT32B0_CAP3/CT32B0_MAT3/PWM1_0 0x0000 0090PIO0_22 R/W 0x014 Configures pin PIO0_22/ACMP0_I3/PWM1_1 0x0000 0090PIO0_23 R/W 0x018 Configures pin0x0000 0090PIO0_23/ACMP1_I0/CT32B1_CAP0/CT32B1_MAT0/PWM_FAULT2PIO0_24 R/W 0x01C Configures pin0x0000 0090PIO0_24/ACMP1_I1/CT32B1_CAP1/CT32B1_MAT1/PWM_FAULT3PIO0_25 R/W 0x020 Configures pin SWDIO/ACMP1_I2/CT32B1_CAP2/CT32B1_MAT2/PIO0_25 0x0000 0090PIO0_26 R/W 0x024 Configures pin SWCLK/ACMP1_I3/CT32B1_CAP3/CT32B1_MAT3/PIO0_26 0x0000 0090PIO0_27 R/W 0x028 Configures pin PIO0_27/ACMP0_O/DA0/PWM_FAULT0 0x0000 009082 www.xinnovatech.com

XN12L612PIO2_12 R/W 0x02C Configures pin PIO2_12/RXD1/ PWM2_2. 0x0000 0090PIO2_13 R/W 0x030 Configures pin PIO2_13/TXD1/ PWM2_3. 0x0000 0090PIO2_14 R/W 0x034 Configures pin PIO2_14/ PWM2_0. 0x0000 0090PIO2_15 R/W 0x038 Configures pin PIO2_15/ PWM2_1. 0x0000 0090PIO0_28 R/W 0x03C Configures pin PIO0_28/ACMP1_O/DA0/CT16B0_CAP0/CT16B0_MAT0 0x0000 0090PIO0_29 R/W 0x040 Configures pin PIO0_29/ROSC/CT16B0_CAP1/CT16B0_MAT1 0x0000 0090PIO0_0 R/W 0x044 Configures pin PIO0_0/PWM0_2 0x0000 0090PIO0_1 R/W 0x048 Configures pin PIO0_1/RXD0/CT32B0_CAP0/CT32B0_MAT0 0x0000 0090PIO0_2 R/W 0x04C Configures pin PIO0_2/TXD0/CT32B0_CAP1/CT32B0_MAT1 0x0000 0090- R/W 0x050 Reserved -PIO0_3 R/W 0x054 Configures pin PIO0_3/CT32B0_CAP2/CT32B0_MAT2/PWM0_4/PWM1_4 0x0000 0090PIO0_4 R/W 0x058 Configures pin PIO0_4/CT32B0_CAP3/CT32B0_MAT3/PWM0_5/PWM1_5 0x0000 0090PIO0_5 R/W 0x05C Configures pin PIO0_5/ PWM0_3. 0x0000 0090PIO0_6 R/W 0x060 Configures pin PIO0_6/CT32B1_CAP0/CT32B1_MAT0/PWM0_6/PWM1_2 0x0000 0090PIO0_7 R/W 0x064 Configures pin PIO0_7/CT32B1_CAP1/CT32B1_MAT1/PWM0_7/PWM1_3 0x0000 0090PIO0_8 R/W 0x068 Configures pin PIO0_8/RXD1/CT32B1_CAP2/CT32B1_MAT2/PWM0_0 0x0000 0090PIO0_9 R/W 0x06C Configures pin PIO0_9/TXD1/CT32B1_CAP3/CT32B1_MAT3/PWM0_1 0x0000 0090PIO2_0 R/W 0x070 Configures pin PIO2_0/CT16B0_CAP0/CT16B0_MAT0/PWM1_2 0x0000 0090PIO2_1 R/W 0x074 Configures pin PIO2_1/CT16B0_CAP1/CT16B0_MAT1/RXD0/PWM_FAULT2 0x0000 0090PIO2_2 R/W 0x078 Configures pin PIO2_2/CT16B1_CAP0/CT16B1_MAT0/TXD0/PWM_FAULT3 0x0000 0090PIO2_3 R/W 0x07C Configures pin PIO2_3/CT16B1_CAP1/CT16B1_MAT1/PWM1_3 0x0000 0090PIO2_4 R/W 0x080 Configures pin PIO2_4/CT32B0_CAP0/CT32B0_MAT0/PWM1_0 0x0000 0090PIO2_5 R/W 0x084 Configures pin PIO2_5/CT32B0_CAP1/CT32B0_MAT1/ PWM1_1 0x0000 0090PIO2_6 R/W 0x088 Configures pin PIO2_6/CT32B0_CAP2/CT32B0_MAT2/PWM2_6 0x0000 0090PIO2_7 R/W 0x08C Configures pin PIO2_7/CT32B0_CAP3/CT32B0_MAT3/PWM2_7 0x0000 0090PIO0_10 R/W 0x090 Configures pin PIO0_10/SCL 0x0000 0080PIO0_11 R/W 0x094 Configures pin PIO0_11/SDA/CT16B0_CAP0/CT16B0_MAT0 0x0000 0080PIO0_12 R/W 0x098 Configures pin PIO0_12/CLKOUT/CT16B0_CAP1/CT16B0_MAT1 0x0000 0090PIO0_13 R/W 0x09C Configures pin RESET/PIO0_13. 0x0000 0090PIO0_14 R/W 0x0A0 Configures pin PIO0_14/SPI_CLK. 0x0000 0090PIO0_15 R/W 0x0A4 Configures pin PIO0_15/SSEL/CT16B1_CAP0/CT16B1_MAT0 0x0000 0090PIO0_16 R/W 0x0A8 Configures pin PIO0_16/MISO/CT16B1_CAP1/CT16B1_MAT1 0x0000 0090PIO0_17 R/W 0x0AC Configures pin PIO0_17/SPI_MOSI. 0x0000 0090PIO0_18 R/W 0x0B0 Configures pin PIO0_18/SWCLK/CT32B0_CAP0/CT32B0_MAT0 0x0000 0090PIO0_30 R/W 0x0B4 Configures pin R/PIO0_30/AD0. 0x0000 0090PIO0_31 R/W 0x0B8 Configures pin R/PIO0_31/AD1/PWM1_7. 0x0000 0090PIO1_0 R/W 0x0BC Configures pin R/PIO1_0/AD2. 0x0000 0090PIO1_1 R/W 0x0C0 Configures pin R/PIO1_1/AD3/ PWM0_4/PWM1_4. 0x0000 0090PIO1_2 R/W 0x0C4 Configures pin PIO1_2/SWDIO/AD4. 0x0000 0090PIO1_3 R/W 0x0C8 Configures pin PIO1_3/AD5/WAKEUP. 0x0000 0090www.xinnovatech.com 83

XN12L612PIO1_4 R/W 0x0CC Configures pin PIO1_4/AD6/ PWM0_5/PWM1_5. 0x0000 0090PIO1_5 R/W 0x0D0 Configures pin PIO1_5/AD7/CT16B1_CAP0/CT16B1_MAT0 0x0000 0090PIO1_6 R/W 0x0D4 Configures pin PIO1_6/CT16B1_CAP1/CT16B1_MAT1/PWM_FAULT1 0x0000 0090- - 0x0D8 Reserved. -- - 0x0DC Reserved. -PIO2_8 R/W 0x0E0 Configures pin PIO2_8/CT32B1_CAP0/CT32B1_MAT0/PWM2_4 0x0000 0090PIO2_9 R/W 0x0E4 Configures pin PIO2_9/CT32B1_CAP1/CT32B1_MAT1/PWM2_5 0x0000 0090PIO2_10 R/W 0x0E8 Configures pin PIO2_10/CT32B1_CAP2/CT32B1_MAT2/TXD1 0x0000 0090PIO2_11 R/W 0x0EC Configures pin PIO2_11/CT32B1_CAP3/CT32B1_MAT3/RXD1 0x0000 009084 www.xinnovatech.com

XN12L6124.7.2.1 PIO0_0 IOCON RegisterTable 4-60: PIO0_0 register (PIO0_0, address 0x4004 4044) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x0Selects function PIO0_0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 2 mA drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.2 PIO0_1 IOCON RegisterTable 4-61: PIO0_1 register (PIO0_1, address 0x4004 4048) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 000www.xinnovatech.com 85

XN12L6120x00x10x20x30x4Selects function PIO0_1.Reserved.Select function RXD0.Select function CT32B0_CAP0.Select function CT32B0_MAT0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.3 PIO0_2 IOCON RegisterTable 4-62: PIO0_2 register (PIO0_2, address 0x4004 404C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 00086 www.xinnovatech.com

XN12L6120x00x10x20x30x4Selects function PIO0_2.Reserved.Select function TXD0.Select function CT32B0_CAP1.Select function CT32B0_MAT1.3 Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.4 PIO0_3 IOCON RegisterTable 4-63: PIO0_3 register (PIO0_3, address 0x4004 4054) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 000www.xinnovatech.com 87

XN12L6120x00x10x20x30x4Selects function PIO0_3.Reserved.Reserved.Select function CT32B0_CAP2.Select function CT32B0_MAT2.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.5 PIO0_4 IOCON RegisterTable 4-64: PIO0_4 register (PIO0_4, address 0x4004 4058) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 00088 www.xinnovatech.com

XN12L6120x00x10x20x30x4Selects function PIO0_4.Reserved.Reserved.Select function CT32B0_CAP3.Select function CT32B0_MAT3.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.6 PIO0_5 IOCON RegisterTable 4-65: PIO0_5 register (PIO0_5, address 0x4004 405C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 000www.xinnovatech.com 89

XN12L6120x0Selects function PIO0_5.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.7 PIO0_6 IOCON RegisterTable 4-66: PIO0_6 register (PIO0_6, address 0x4004 4060) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO0_6.Reserved.Reserved.Select function CT32B1_CAP0.90 www.xinnovatech.com

XN12L6120x4Select function CT32B1_MAT0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.8 PIO0_7 IOCON RegisterTable 4-67: PIO0_7 register (PIO0_7, address 0x4004 4064) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO0_7.Reserved.Reserved.Select function CT32B1_CAP1.www.xinnovatech.com 91

XN12L6120x4Select function CT32B1_MAT1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.9 PIO0_8 IOCON RegisterTable 4-68: PIO0_8 register (PIO0_8, address 0x4004 4068) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO0_8.Reserved.Select function RXD1.Select function CT32B1_CAP2.92 www.xinnovatech.com

XN12L6120x4Select function CT32B1_MAT2.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.10 PIO0_9 IOCON RegisterTable 4-69: PIO0_9 register (PIO0_9, address 0x4004 406C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO0_9.Reserved.Select function TXD1.Select function CT32B1_CAP3.www.xinnovatech.com 93

XN12L6120x4Select function CT32B1_MAT3.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.11 PIO0_10 IOCON RegisterTable 4-70: PIO0_10 register (PIO0_10, address 0x4004 4090) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x2Selects function PIO0_10.Reserved.Select TWS-bus function SCL.5:3 - Reserved. 00094 www.xinnovatech.com

XN12L6126 INV Invert input 00 Input not inverted.1 Input inverted.9:7 - - Reserved. 00110 TOD True open-drain mode. 00 Disable.1 True open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x60x0IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.Reserved.31:16 - Reserved. 04.7.2.12 PIO0_11 IOCON RegisterTable 4-71: PIO0_11 register (PIO0_11, address 0x4004 4094) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_11.Reserved.Select TWS-bus function SDA.Select function CT16B0_CAP0.Select function CT16B0_MAT0.5:3 - - Reserved. 0006 INV Invert input 00 Input not inverted.1 Input inverted.9:7 - - Reserved. 00110 TOD True open-drain mode. 00 Disable.1 True open-drain mode enabled.www.xinnovatech.com 95

XN12L61212:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x60x0IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.Reserved.31:16 - Reserved. 04.7.2.13 PIO0_12 IOCON RegisterTable 4-72: PIO0_12 register (PIO0_12, address 0x4004 4098) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_12.Reserved.Select function CLKOUT.Select function CT16B0_CAP1.Select function CT16B0_MAT1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (High-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.96 www.xinnovatech.com

XN12L6121 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 0www.xinnovatech.com 97

XN12L6124.7.2.14 PIO0_13 IOCON RegisterTable 4-73: RESET_PIO0_13 register (RESET_PIO0_13, address 0x4004 409C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x1Selects function RESET.Select function PIO0_13.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 098 www.xinnovatech.com

XN12L6124.7.2.15 PIO0_14 IOCON RegisterTable 4-74: PIO0_14 register (PIO0_14, address 0x4004 40A0) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x2Selects function PIO0_14.Reserved.Select function SCK.0x3~4 Reserved.0x5Select function RXD2.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 2 mA drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIVSelect peripheral clock divider for input filter sampling clock.0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 0www.xinnovatech.com 99

XN12L6124.7.2.16 PIO0_15 IOCON RegisterTable 4-75: PIO0_15 register (PIO0_15, address 0x4004 40A4) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x40x5Selects function PIO0_15.Reserved.Select function SSEL.Select function CT16B1_CAP0.Select function CT16B1_MAT0.Select function TXD2.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 2 mA drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.100 www.xinnovatech.com

XN12L61231:16 - - Reserved. 04.7.2.17 PIO0_16 IOCON RegisterTable 4-76: PIO0_16 register (PIO0_16, address 0x4004 40A8) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x40x5Selects function PIO0_16.Reserved.Select function MISO.Select function CT16B1_CAP1.Select function CT16B1_MAT1.Select function RXD3.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 2 mA drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIVSelect peripheral clock divider for input filter sampling clock.0000x00x10x20x30x40x5IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.www.xinnovatech.com 101

XN12L6120x6IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.18 PIO0_17 IOCON RegisterTable 4-77: PIO0_17 register (PIO0_17, address 0x4004 40AC) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x2Selects function PIO0_17.Reserved.Select function MOSI.0x3~5 Reserved.0x6Select function TXD3.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 2 mA drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIVSelect peripheral clock divider for input filter sampling clock.0000x00x10x20x30x40x5IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.102 www.xinnovatech.com

XN12L6120x6IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.19 PIO0_18 IOCON RegisterTable 4-78: PIO0_18 register (PIO0_18, address 0x4004 40B0) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_18.Select function SWCLK.Reserved.Select function CT32B0_CAP0.Select function CT32B0_MAT0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 2 mA drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIVSelect peripheral clock divider for input filter sampling clock.0000x00x10x20x30x40x5IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.www.xinnovatech.com 103

XN12L6120x6IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.20 PIO0_19 IOCON RegisterTable 4-79: PIO0_19 register (PIO0_19, address 0x4004 4008) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_19.Reserved.Select function ACMP0_I0.Select function CT32B0_CAP1.Select function CT32B0_MAT1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x3IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.104 www.xinnovatech.com

XN12L6120x40x50x6IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.21 PIO0_20 IOCON RegisterTable 4-80: PIO0_20 register (PIO0_20, address 0x4004 400C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_20.Reserved.Select function ACMP0_I1.Select function CT32B0_CAP2.Select function CT32B0_MAT2.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x1IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.www.xinnovatech.com 105

XN12L6120x20x30x40x50x6IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.22 PIO0_21 IOCON RegisterTable 4-81: PIO0_21 register (PIO0_21, address 0x4004 4010) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_21.Reserved.Select function ACMP0_I2.Select function CT32B0_CAP3.Select function CT32B0_MAT3.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 000106 www.xinnovatech.com

XN12L6120x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.23 PIO0_22 IOCON RegisterTable 4-82: PIO0_22 register (PIO0_22, address 0x4004 4014) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x2Selects function PIO0_22.Reserved.Select function ACMP0_I3.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 000www.xinnovatech.com 107

XN12L6120x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.24 PIO0_23 IOCON RegisterTable 4-83: PIO0_23 register (PIO0_23, address 0x4004 4018) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_23.Reserved.Select function ACMP1_I0.Select function CT32B1_CAP0.Select function CT32B1_MAT0.3 - - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x2Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.108 www.xinnovatech.com

XN12L6120x3Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.25 PIO0_24 IOCON RegisterTable 4-84: PIO0_24 register (PIO0_24, address 0x4004 401C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_24.Reserved.Select function ACMP1_I1.Select function CT32B1_CAP1.Select function CT32B1_MAT1.3 - - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x0Bypass input filter.www.xinnovatech.com 109

XN12L6120x10x20x3Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.26 PIO0_25 IOCON RegisterTable 4-85: SWDIO_PIO0_25 register (SWDIO_PIO0_25, address 0x4004 4020) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x40x50x6Selects function SWDIO.Reserved. Do not use.Select function ACMP1_I2.Select function CT32B1_CAP2.Select function CT32B1_MAT2.Reserved.Select function PIO0_25.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 0110 www.xinnovatech.com

XN12L6120 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.27 PIO0_26 IOCON RegisterTable 4-86: SWCLK_PIO0_26 register (SWCLK_PIO0_26, address 0x4004 4024) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x40x50x6Selects function SWCLK.Reserved.Select function ACMP1_I3.Select function CT32B1_CAP3.Select function CT32B1_MAT3.Reserved.Select function PIO0_26.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 0www.xinnovatech.com 111

XN12L6129 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.28 PIO0_27 IOCON RegisterTable 4-87: PIO0_27 register (PIO0_27, address 0x4004 4028) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x2Selects function PIO0_26.Reserved. Do not use.Select function ACMP0_O.0x3~5 Reserved. Do not use.0x6Select DA03 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 10 Analog mode enabled.112 www.xinnovatech.com

XN12L6121 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (High-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.29 PIO0_28 IOCON RegisterTable 4-88: PIO0_28 register (PIO0_28, address 0x4004 403C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_28.Reserved.Select function ACMP1_O.Select function CT16B0_CAP0.Select function CT16B0_MAT0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.www.xinnovatech.com 113

XN12L6127 - Reserved. 18 - Reserved. 09 DRV Drive current mode (High-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.30 PIO0_29 IOCON RegisterTable 4-89: PIO0_29 register (PIO0_29, address 0x4004 4040) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO0_29.Reserved.Reserved.Select function CT16B0_CAP1.Select function CT16B0_MAT1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.114 www.xinnovatech.com

XN12L6127 - Reserved. 18 - Reserved. 09 DRV Drive current mode (High-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved 04.7.2.31 PIO0_30 IOCON RegisterTable 4-90: PIO0_30 register (PIO0_30, address 0x4004 40B4) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Reserved.Select function PIO0_30.Reserved.Select function AD0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 1www.xinnovatech.com 115

XN12L6120 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIVSelect peripheral clock divider for input filter sampling clock.0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.32 PIO0_31 IOCON RegisterTable 4-91: PIO0_31 register (PIO0_31, address 0x4004 40B8) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Reserved.Select function PIO0_31.Reserved.Select function AD1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.116 www.xinnovatech.com

XN12L6127 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIVSelect peripheral clock divider for input filter sampling clock.0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.33 PIO1_0 IOCON RegisterTable 4-92: PIO1_0 register (PIO1_0, address 0x4004 40BC) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x2Reserved.Select function PIO1_0.Select function AD2.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.www.xinnovatech.com 117

XN12L6127 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 2 mA drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIVSelect peripheral clock divider for input filter sampling clock.0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.34 PIO1_1 IOCON RegisterTable 4-93: PIO1_1 register (PIO1_1, address 0x4004 40C0) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x2Reserved.Select function PIO1_0.Select function AD3.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.118 www.xinnovatech.com

XN12L6127 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 2 mA drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.35 PIO1_2 IOCON RegisterTable 4-94: PIO1_2 register (PIO1_2, address 0x4004 40C4) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x2Selects function PIO1_2.Select function SWDIO.Select function AD4.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.www.xinnovatech.com 119

XN12L6127 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.36 PIO1_3 IOCON RegisterTable 4-95: PIO1_3 register (PIO1_3, address 0x4004 40C8) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. This pin functions as WAKEUP pin if the part000is in Power-down mode regardless of the value of FUNC.0x00x1Selects function PIO1_3.Select function AD5.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.120 www.xinnovatech.com

XN12L6127 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.37 PIO1_4 IOCON RegisterTable 4-96: PIO1_4 register (PIO1_4, address 0x4004 40CC) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x1Selects function PIO1_4.Select function AD6.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 ADMODE Analog/Digital mode 1www.xinnovatech.com 121

XN12L6120 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - -. Reserved 04.7.2.38 PIO1_5 IOCON RegisterTable 4-97: PIO1_5 register (PIO1_5, address 0x4004 40D0) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO1_5.Select function AD7.Select function CT16B1_CAP0.Select function CT16B1_MAT0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.122 www.xinnovatech.com

XN12L6127 ADMODE Analog/Digital mode 10 Analog mode enabled.1 Digital mode enabled.8 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.39 PIO1_6 IOCON RegisterTable 4-98: PIO1_6 register (PIO1_6, address 0x4004 40D4) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x2Selects function PIO1_6.Select function CT16B1_CAP1.Select function CT16B1_MAT1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.www.xinnovatech.com 123

XN12L6127 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode drive current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.40 PIO2_0 IOCON RegisterTable 4-99: PIO2_0 register (PIO2_0, address 0x4004 4070) bit descriptionZ` Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x20x30x4Selects function PIO2_0.Reserved.Select function CT16B0_CAP0.Select function CT16B0_MAT0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 1124 www.xinnovatech.com

XN12L6128 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.41 PIO2_1 IOCON RegisterTable 4-100: PIO2_1 register (PIO2_1, address 0x4004 4074) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO2_1.Reserved.Select function CT16B0_CAP1.Select function CT16B0_MAT1.Select function RXD0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 1www.xinnovatech.com 125

XN12L6128 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.42 PIO2_2 IOCON RegisterTable 4-101: PIO2_2 register (PIO2_2, address 0x4004 4078) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x4Selects function PIO2_2.Reserved.Select function CT16B1_CAP0.Select function CT16B1_MAT0.Select function TXD0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 1126 www.xinnovatech.com

XN12L6128 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.43 PIO2_3 IOCON RegisterTable 4-102: PIO2_3 register (PIO2_3, address 0x4004 407C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO2_3.Reserved.Select function CT16B1_CAP1.Select function CT16B1_MAT1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 0www.xinnovatech.com 127

XN12L6129 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.44 PIO2_4 IOCON RegisterTable 4-103: PIO2_4 register (PIO2_4, address 0x4004 4080) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO2_4.Reserved.Select function CT32B0_CAP0.Select function CT32B0_MAT0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 0128 www.xinnovatech.com

XN12L6120 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.45 PIO2_5 IOCON RegisterTable 4-104: PIO2_5 register (PIO2_5, address 0x4004 4084) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO2_5.Reserved.Select function CT32B0_CAP1.Select function CT32B0_MAT1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.www.xinnovatech.com 129

XN12L6121 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.46 PIO2_6 IOCON RegisterTable 4-105: PIO2_6 register (PIO2_6, address 0x4004 4088) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO2_6.Reserved.Select function CT32B0_CAP2.Select function CT32B0_MAT2.0x4~5 Reserved.0x6Select function RXD2.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 0130 www.xinnovatech.com

XN12L6120 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.47 PIO2_7 IOCON RegisterTable 4-106: PIO2_7 register (PIO2_7, address 0x4004 408C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO2_7.Reserved.Select function CT32B0_CAP3.Select function CT32B0_MAT3.0x4~5 Reserved.0x6Select function TXD2.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 0www.xinnovatech.com 131

XN12L6129 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 04.7.2.48 PIO2_8 IOCON RegisterTable 4-107: PIO2_8 register (PIO2_8, address 0x4004 40E0) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO2_8.Reserved.Select function CT32B1_CAP0.Select function CT32B1_MAT0.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 0132 www.xinnovatech.com

XN12L6120 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.49 PIO2_9 IOCON RegisterTable 4-108: PIO2_9 register (PIO2_9, address 0x4004 40E4) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 00sL00x00x10x20x3Selects function PIO2_9.Reserved.Select function CT32B1_CAP1.Select function CT32B1_MAT1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.www.xinnovatech.com 133

XN12L6121 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIVSelect peripheral clock divider for input filter sampling clock.0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.50 PIO2_10 IOCON RegisterTable 4-109: PIO2_10 register (PIO2_10, address 0x4004 40E8) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x40x5Selects function PIO2_10.Reserved.Select function CT32B1_CAP2.Select function CT32B1_MAT2.Reserved.Select function TXD1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 09 DRV Drive current mode (Normal-drive pin). 0134 www.xinnovatech.com

XN12L6120 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.51 PIO2_11 IOCON RegisterTable 4-110: PIO2_11 register (PIO2_11, address 0x4004 40EC) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x30x40x5Selects function PIO2_11.Reserved.Select function CT32B1_CAP3.Select function CT32B1_MAT3.Reserved.Select function RXD1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - Reserved. 18 - Reserved. 0www.xinnovatech.com 135

XN12L6129 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.52 PIO2_12 IOCON RegisterTable 4-111: PIO2_12 register (PIO2_12, address 0x4004 402C) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO2_12.Reserved.Reserved.Selects function RXD1.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - - Reserved 18 - - Reserved 09 DRV Drive current mode (Normal-drive pin). 0136 www.xinnovatech.com

XN12L6120 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - -. Reserved 04.7.2.53 PIO2_13 IOCON RegisterTable 4-112: PIO2_13 register (PIO2_13, address 0x4004 4030) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x00x10x20x3Selects function PIO2_13.Reserved.Reserved.Select function TXD1.3 - - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 - - Reserved. 18 - - Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.www.xinnovatech.com 137

XN12L6121 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.54 PIO2_14 IOCON RegisterTable 4-113: PIO2_14 register (PIO2_14, address 0x4004 4034) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x0Selects function PIO2_14.0x1~4 Reserved0x5Selects function RXD3.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 Reserved. 18 Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 0138 www.xinnovatech.com

XN12L6120 Open-drain mode disabled.1 Open-drain mode enabled.12:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - - Reserved. 04.7.2.55 PIO2_15 IOCON RegisterTable 4-114: PIO2_15 register (PIO2_15, address 0x4004 4038) bit descriptionBit Symbol Value Description Reset value2:0 FUNC Selects pin function. 0000x0Selects function PIO2_15.0x1~5 Reserved.0x6Selects function TXD3.3 - Reserved 04 MODE Selects function mode (on-chip pull-up resistor control). 10 Inactive (pull-up resistor not enabled).1 Pull-up resistor enabled.5 - Reserved. 06 INV Invert input 00 Input not inverted.1 Input inverted.7 Reserved. 18 Reserved. 09 DRV Drive current mode (Normal-drive pin). 00 Low mode current selected.1 High mode current selected.10 OD Open-drain mode. 00 Open-drain mode disabled.1 Open-drain mode enabled.www.xinnovatech.com 139

XN12L61212:11 S_MODE Sample mode 000x00x10x20x3Bypass input filter.Input pulses shorter than one filter clock are rejected.Input pulses shorter than two filter clocks are rejected.Input pulses shorter than three filter clocks are rejected.15:13 CLK_DIV Select peripheral clock divider for input filter sampling clock. 0000x00x10x20x30x40x50x6IOCONFIGCLKDIV0.IOCONFIGCLKDIV1.IOCONFIGCLKDIV2.IOCONFIGCLKDIV3.IOCONFIGCLKDIV4.IOCONFIGCLKDIV5.IOCONFIGCLKDIV6.31:16 - Reserved. 0140 www.xinnovatech.com

XN12L6125 GPIO5.1 General DescriptionXN12L612 provides up to 55 GPIOs. The following are major features of GPIO:• Digital ports can be configured as input or output by software.• Read and write data operations from/to the port pins are maskable.• Bit-level set and clear registers allow a single-instruction set or clear of any number of pins in one port.• Bit-level invert registers allow inverting the output of any number of pins in one port.• Each individual port pin can serve as external interrupt input.• Interrupts can be configured on single falling or rising edges and on both edges.• Individual interrupt levels can be programmed.• All GPIO pins are configured as inputs (with pull-up resistors enabled) after reset.5.2 Pin DescriptionTable 5-1: Available GPIO pins/portsPort Pins GPIO register bits used LQFP64GPIO0 PIO0_0 to PIO0_31 31:0 yesGPIO1 PIO1_0 to PIO1_6 6:0 yesGPIO2 PIO2_0 to PIO2_15 15:0 yes5.3 Control Register DescriptionAll GPIOs are grouped into 3 ports: Port0, Port1 and Port2. Each port has its own value and control registers to manageGPIO feature.• Port 0: All GPIO0 registers use bits 0 to 31.• Port 1: All GPIO1 registers use bits 0 to 6. Bits 7 to 31 are reserved.• Port 2: All GPIO2 registers use bits 0 to 15. Bits 16 to 31 are reserved.Table 5-2: Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000)Symbol Access Address offset Description Reset valueMASK R/W 0x000 Pin value mask register. Affects operations on PIN, OUT, SET,0x0000 0000CLR, and NOT registers.PIN R 0x004 Pin value register. configurationdependentOUT R/W 0x008 Pin output value register. 0x0000 0000SET W 0x00C Pin output value set register. NACLR W 0x010 Pin output value clear register. NANOT W 0x014 Pin output value invert register. 0x0000 0000www.xinnovatech.com 141

XN12L612DIR R/W 0x020 Data direction register. 0x0000 0000IS R/W 0x024 Interrupt sense register. 0x0000 0000IBE R/W 0x028 Interrupt both edges register. 0x0000 0000IEV R/W 0x02C Interrupt event register. 0x0000 0000IE R/W 0x030 Interrupt mask register. 0x0000 0000RIS R 0x034 Raw interrupt status register. 0x0000 0000MIS R 0x038 Masked interrupt status register. 0x0000 0000IC W 0x03C Interrupt clear register. 0x0000 0000- - 0x040 Reserved. 0x0000 00005.3.1 GPIO Mask RegisterThis register masks the read and/or write accesses to the following masked registers: PIN, OUT, SET, CLR, and NOT. Onlybits set to 0 in the MASK register enable the corresponding bits in the masked registers to be changed or their value to beread. Setting any mask bit to 0 allows the pin output to be changed by write operations to the pin’s OUT, SET, CLR, andNOT registers. The current state of the pin can be read from the PIN registers and the current value of the OUT registers canbe read. Setting any mask bit to 1 allows write operations to the pin’s OUT, SET, CLR, and NOT registers to have no effecton the pin’s output level. Read operations return 0 regardless of the pin’s level or the value of the OUT register.Table 5-3: GPIO Mask Register (MASK - address 0x5000 0000 (GPIO0), 0x5001 0000 (GPIO1), 0x5002 0000 (GPIO2)) bit descriptionBit Symbol Value Description Reset valuex (31~0) MASKx GPIO pin PIOn_x access control. 0x00 not masked.1 masked.5.3.2 GPIO Pin Value RegisterThis register provides the current logic state of port pins that are configured to perform digital functions. A read operation onthis register will return the logic value of the pin regardless of whether the pin is configured for input or output, or whether it isconfigured as GPIO or any other applicable alternate digital function. For example, a particular port pin may have GPIO input,GPIO output, and counter/timer match output and capture input as selectable functions. Through the PIN register, thecurrent logic state of the pin can be read in any configuration, e.g. the state of the capture input could be read.As an exception, the pin state cannot be read if its analog function is selected (if applicable) because selecting the pin as anADC input disconnects the digital features of the pin. In that case, the pin value read in the PIN register is not valid.Note that read operations are masked by the MASK bits. Read operations on masked bits always return 0 regardless of thepin’s actual level.Table 5-4: GPIO Pin Value Register (PIN - address 0x5000 0004 (GPIO0), 0x5001 0004 (GPIO1);0x5002 0004 (GPIO2)) bit descriptionBit Symbol Value Description Reset valuex (31~0) PINx GPIO pin PIOn_x value. 0142 www.xinnovatech.com

XN12L6120 Digital pin level is LOW.1 Digital pin level is HIGH.5.3.3 GPIO Pin Output RegisterWriting 0 or 1 to this register produces LOW or HIGH levels at the corresponding port pins. The port pin is set to this value ifit is configured as GPIO output. For all other configurations (input, non-GPIO function), the value of the OUT register bit hasno effect on the pin output level. Write operations are masked by the MASK registers.Reading this register returns the contents of the GPIO output register regardless of the digital pin configuration and direction.Read operations are masked by the MASK registers.The SET, CLR, and NOT registers write to the OUT register to allow bit-wise setting, clearing, and inverting of individual portpins. The port output state is determined by the contents of the OUT register only.Table 5-5: GPIO Pin Output Register (OUT - address 0x5000 0008 (GPIO0), 0x5001 0008 (GPIO1), 0x5002 0008 (GPIO2)) bit descriptionBit Symbol Value Description Reset Valuex (31~0) OUTx GPIO pin PIOn_x output value. 00 Write: Set GPIO output pin to LOW. Read: GPIO output value is LOW.1 Write: Set GPIO output pin to HIGH. Read: GPIO output value is HIGH.5.3.4 GPIO Pin Output Set RegisterThis register is used to produce a HIGH level output at the port pins configured as GPIO output in the DIR register and asGPIO in the corresponding IOCONFIG register. Writing 1 sets the corresponding port pin to HIGH. Writing 0 has no effect onthe GPIO output level. If a pin is not configured as GPIO and output, the SET register has no effect on the pin level.This register is a write-only register. Note that write operations to the SET register are masked by the MASK register.Table 5-6: GPIO Pin Output Set Register (SET - address 0x5000 000C (GPIO0), 0x5001 000C (GPIO1), 0x5002 000C (GPIO2)) bitdescriptionBit Symbol Description Reset valuex (31~0) SETx Set GPIO pin PIOn_x output value. Write:00 = No effect on the GPIO output level.1 = GPIO output is set to HIGH.5.3.5 GPIO Pin Output Clear RegisterThis register is used to produce a LOW level output at the port pins configured as GPIO output in the DIR register and asGPIO in the corresponding IOCONFIG register. Writing 1 sets the corresponding port pin to LOW. Writing 0 has no effect onthe GPIO output level. If a pin is not configured as GPIO and output, the CLR register has no effect on the pin level.This register is a write-only register. Note that write operations to the CLR register are masked by the MASK register.Table 5-7: GPIO Pin Output Clear Register (CLR - address 0x5000 0010 (GPIO0), 0x5000 1010 (GPIO1), 0x5002 0010 (GPIO2)) bitdescriptionwww.xinnovatech.com 143

XN12L612Bit Symbol Description Reset valuex (31~0) CLEARx Clear GPIO pin PIOn_x output value. Write:00 = No effect on the GPIO output level.1 = GPIO output is set to LOW.5.3.6 GPIO NOT RegisterThis register is used to invert the output level at the port pins configured as GPIO output in the DIR register and as GPIO inthe corresponding IOCONFIG register. Writing 1 inverts the corresponding port pin. Writing 0 has no effect on the GPIOoutput level. If a pin is not configured as GPIO and output, the NOT register has no effect on the pin level. This register is awrite-only register. Note that write operations to the NOT register are masked by the MASK register.Table 5-8: GPIO NOT Register (NOT - address 0x5000 0014 (GPIO0), 0x5001 0014 (GPIO1), 0x5002 0014 (GPIO2)) bit descriptionBit Symbol Description Reset valuex (31~0) NOT Invert GPIO pin PIOn_x output value. Write:00 = No effect on the GPIO output level.1 = GPIO output is inverted from its current value.5.3.7 GPIO Data Direction RegisterTable 5-9: GPIO Data Direction Register (DIR - address 0x5000 0020 (GPIO0), 0x5001 0020 (GPIO1), 0x5002 0020 (GPIO2)) bitdescriptionBit Symbol Value Description Reset valuex (31~0) IOx Selects GPIO pin PIOn_x as input or output. 00 Pin PIOn_x is configured as input.1 Pin PIOn_x is configured as output.5.3.8 GPIO Interrupt Sense RegisterTable 5-10: GPIO Interrupt Sense Register (IS - address 0x5000 0024 (GPIO0), 0x5001 0024 (GPIO1), 0x5002 0024 (GPIO2)) bitdescriptionBit Symbol Value Description Reset valuex (31~0) ISENSEx Selects interrupt on pin PIOn_x as level or edge sensitive. 00 Interrupt on pin PIOn_x is configured as edge sensitive.1 Interrupt on pin PIOn_x is configured as level sensitive.5.3.9 GPIO Interrupt Both Edges Sense RegisterTable 5-11: GPIO Interrupt Both Edges Sense Register (IBE - address 0x5000 0028 (GPIO0), 0x5001 0028 (GPIO1), 0x5002 0028 (GPIO2))bit descriptionBit Symbol Value Description Reset valuex (31~0) IBEx Selects interrupt on pin PIOn_x to be triggered on both edges. 00 0 = Interrupt on pin PIOn_x is controlled through register IEV.144 www.xinnovatech.com

XN12L6121 1 = Both edges on pin PIOn_x trigger an interrupt.5.3.10 GPIO Interrupt Event RegisterTable 5-12: GPIO Interrupt Event Register (IEV - address 0x5000 002C (GPIO0), 0x5001 002C (GPIO1), 0x5002 002C (GPIO2)) bitdescriptionBit Symbol Value Description Reset valuex (31~0) IEVx Selects interrupt on pin PIOn_x to be triggered rising or falling edges. 00 Depending on setting in register IS, falling edges or LOW level on pin PIOn_xtrigger an interrupt.1 Depending on setting in register IS, rising edges or HIGH level on pin PIOn_xtrigger an interrupt.5.3.11 GPIO Interrupt Mask RegisterBits set to HIGH in the IE register allow the corresponding pins to trigger their individual interrupts and the combined INTRline. Clearing a bit disables interrupt triggering on that pin.Table 5-13: GPIO Interrupt Mask Register (IE - address 0x5000 0030, 0x5001 0030 (GPIO1),0x5002 0030 (GPIO2)) bit descriptionBit Symbol Value Description Reset valuex (31~0) MASKx Selects interrupt on pin PIOn_x to be masked. 00 0 = Interrupt on pin PIOn_x is masked.1 1 = Interrupt on pin PIOn_x is not masked.5.3.12 GPIO Raw Interrupt Status RegisterBits read HIGH in the IRS register reflect the raw (prior to masking) interrupt status of the corresponding pins indicating thatall the requirements have been met before they are allowed to trigger the IE. Bits read as zero indicate that thecorresponding input pins have not initiated an interrupt. The register is read-only.Table 5-14: GPIO Raw Interrupt Mask Status Register (RIS - address 0x5000 0034 (GPIO0), 0x5001 0034 (GPIO1), 0x5002 0034 (GPIO2))bit descriptionBit Symbol Value Description Reset valuex (31~0) RAWSTx Raw interrupt status. 00 0 = No interrupt on pin PIOn_x.1 1 = Interrupt requirements met on PIOn_x.5.3.13 GPIO Masked Interrupt Status RegisterBits read HIGH in the MIS register reflect the status of the input lines triggering an interrupt. Bits read as LOW indicate thateither no interrupt on the corresponding input pins has been generated or that the interrupt is masked. MIS is the state of theinterrupt after masking. The register is read-only.www.xinnovatech.com 145

XN12L612Table 5-15: GPIO Masked Interrupt Status Register (MIS - address 0x5000 0038 (GPIO0), 0x5001 0038 (GPIO1), 0x5002 0038 (GPIO2))bit descriptionBit Symbol Value Description Reset valuex (31~0) MASKx Selects interrupt on pin PIOn_x to be masked. 00 No interrupt or interrupt masked on pin PIOn_x.1 Interrupt on PIOn_x.5.3.14 GPIO Interrupt Clear RegisterThe synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPsafter the clear of the interrupt edge detection logic, before the exit of the interrupt service routine.Table 5-16: GPIO Interrupt Clear Register (IC - address 0x5000 003C, 0x5001 003C (GPIO1), 0x5002 003C (GPIO2)) bit descriptionBit Symbol Value Description Reset valuex (31~0) CLRx Selects interrupt on pin PIOn_x to be cleared. Clears the interrupt edge0detection logic. Write:0 0 = No effect.1 1 = Clears edge detection logic for pin PIOn_x.146 www.xinnovatech.com

XN12L6126 16-Bit Timer/Counter6.1 General DescriptionXN12L612 has two multi functions 16-bit counters/timers. The timer/counter clocks are provided by system clock, which iscontrolled by the SYSAHBCLKDIV. And can also be disabled by AHB control register for power saving. The following aremain features:• Programmable 16-bit prescaler to timer/counter clock.• Normal Counter or timer operation plus:– Edge count mode– Gated count Mode– Quadrature count mode– Trigger count Mode– Signed count mode• 16-bit capture channels that can take a snapshot of the timer value when an input signal transitions. A capture event mayalso optionally generate an interrupt.• The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easypulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on thetrailing edge.• Four 16-bit match registers that allow:– Continuous operation with optional interrupt generation on match.– Stop timer on match with optional interrupt generation.– Reset timer on match with optional interrupt generation.• Two external outputs corresponding to match registers with the following capabilities:– Set LOW on match.– Set HIGH on match.– Toggle on match.– Do nothing on match.• For each timer, up to four match registers can be configured as PWM allowing usage of up to two match outputs as singleedge controlled PWM outputs.www.xinnovatech.com 147

XN12L612CAPTURE REGISTER 3CAPTURE REGISTER 2CAPTURE GEGISTER 1CAPTURE REGISTER 0MATCH REGISTER 3MATCH REGISTER 2MATCH REGISTER 1MATCH REGISTER 0CAPTURE CONTROL REGISTERMATCH CONTROL REGISTERENTERNAL MATCH REGISTERINTERRUPT REGISTERCONTROL==LOAD[3:0]==MAT[1:0]INTERRUPTCAP[3:0]TIMER CONTROLREGISTERReset/EnableTIMER COUNTER+ -COUNT/Edge CNTQUADCNTGATECNTTRIGGERCNTSIGNEDCNTPRISECSOURCE SELMAXVALPRESCALE REGISTERPRESCALECOUNTERCAP[3:0]Other C16B MATC32B MATPCLKFigure 6-1: 16-bit counter/timer block diagram148 www.xinnovatech.com

XN12L6126.2 Pin DescriptionThe following table gives a brief summary of the counter/timer related pins.Table 6-1: 16-Bits counter/timer pin descriptionPin Type DescriptionCT16B0_CAP[1:0]CT16B1_CAP[1:0]CT16B0_MAT[1:0]CT16B1_MAT[1:0]InputOutputCapture Signal:A transition on a capture pin can be configured to load the Capture Register with thevalue in the counter/timer and optionally generate an interrupt. Counter/Timer blockcan select a capture signal as a clock source instead of the PCLK derived clock.External Match Outputs of CT16B0/1:When a match register of CT16B0/1 (MR1:0) equals the timer counter (TC), thisoutput can either toggle, go LOW, go HIGH, or do nothing. The External MatchRegister (EMR) and the PWM Control Register (PWMCON) control the functionality ofthis output.In addition, the level and edge outputs of the two comparators are internally connected to the remaining capture channels 2and 3 of each of the 16-bit counter/timer.6.3 Register DescriptionTable 6-2: Register overview: 16-bit counter/timer (CT16B0 base address 0x4001 0000; CT16B1 base address 0x4001 4000)Symbol Access Address offset Description Reset valueIR R/W 0x000 Interrupt Register. The IR can be written to clear interrupts. The IR0can be read to identify which of eight possible interrupt sources arepending.TCR R/W 0x004 Timer Control Register. The TCR is used to control the timer counter0functions. The timer counter can be disabled or reset through theTCR.TC R/W 0x008 Timer Counter. The 16-bit TC is incremented every PR+1 cycles of0PCLK. The TC is controlled through the TCR.PR R/W 0x00C Prescale register. When the prescale counter is equal to this value,0the next clock increments the TC and clears the PC.PC R/W 0x010 Prescale Counter. The 16-bit PC is a counter which is incremented to0the value stored in PR. When the value in PR is reached, the TC isincremented and the PC is cleared. The PC is observable andcontrollable through the bus interface.MCR R/W 0x014 Match Control Register. The MCR is used to control if an interrupt is0generated and if the TC is reset when a Match occurs.MR0 R/W 0x018 Match Register 0. MR0 can be enabled through the MCR to reset the0TC, stop both the TC and PC, and/or generate an interrupt every timeMR0 matches the TC.www.xinnovatech.com 149

XN12L612MR1 R/W 0x01C Match Register 1. See MR0 description. 0MR2 R/W 0x020 Match Register 2. See MR0 description. 0MR3 R/W 0x024 Match Register 3. See MR0 description. 0CCR R/W 0x028 Capture Control Register. The CCR controls which edges of the0capture inputs are used to load the capture registers and whether ornot an interrupt is generated when a capture takes place.CR0 RO 0x02C Capture Register 0. CR0 is loaded with the value of TC when there is0an event on the CT16B0_CAP0 input.CR1 RO 0x030 Capture Register 1. CR1 is loaded with the value of TC when there is0an event on the CT16B0_CAP1 input.CR2 RO 0x034 Capture Register 3. CR2 is loaded with the value of TC when there is0an event on the input from the comparator.CR3 RO 0x038 Capture Register 3. CR3 is loaded with the value of TC when there is0an event on the input from the comparator.EMR R/W 0x03C External Match Register. The EMR controls the match function and0the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].- - 0x040 - 0x06C reserved -CTCR R/W 0x070 Count Control Register. The CTCR selects between timer and0counter mode, and in counter mode selects the signal and edge(s) forcounting.PWMC R/W 0x074 PWM Control Register. The PWMCON enables PWM mode for the0external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].6.3.1 Interrupt RegisterThe Interrupt Register consists of four bits for the match interrupts and two bits for the capture interrupts. If an interrupt isgenerated then the corresponding bit in the IR will be HIGH. Otherwise, the bit will be LOW. Writing a logic one to thecorresponding IR bit will reset the interrupt. Writing a zero has no effect. Clearing an interrupt for timer match also clears anycorresponding DMA request.Table 6-3: Interrupt Register (IR, address 0x4001 0000 (CT16B0) and 0x4001 4000 (CT16B1)) bit descriptionBit Symbol Description Reset value0 MR0INT Interrupt flag for match channel 0. 01 MR1INT Interrupt flag for match channel 1. 02 MR2INT Interrupt flag for match channel 2. 03 MR3INT Interrupt flag for match channel 3. 04 CR0INT Interrupt flag for capture channel 0 event. 05 CR1INT Interrupt flag for capture channel 1 event. 06 CR2INT Interrupt flag for capture channel 2 event. 07 CR3INT Interrupt flag for capture channel 3 event. 031:8 - Reserved -150 www.xinnovatech.com

XN12L6126.3.2 Timer Control RegisterThe Timer Control Register is used to control the operation of the counter/timer.Table 6-4: Timer Control Register (TCR, address 0x4001 0004 (CT16B0) and 0x4001 4004 (CT16B1)) bit descriptionBit Symbol Value Description Reset value0 CEN Counter enable. 00 The counters are disabled.1 The Timer Counter and Prescale Counter are enabled for counting.1 CRST Counter reset. 00 Do nothing.1 The Timer Counter and the Prescale Counter are synchronously reset on thenext positive edge of PCLK. The counters remain reset until TCR[1] is returned tozero.31: 2 - - Reserved. NA6.3.3 Timer Counter RegisterThe 16-bit timer counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset beforereaching its upper limit, the TC will count up to the value 0x0000 FFFF and then wrap back to the value 0x0000 0000. Thisevent does not cause an interrupt, but a match register can be used to detect an overflow if needed.Table 6-5: Timer Counter Register (TC, address 0x4001 0008 (CT16B0) and 0x4001 4008 (CT16B1)) bit descriptionBit Symbol Description Reset value15:0 TC Timer counter value. 031:16 - Reserved. - NA6.3.4 Prescale RegisterThe 16-bit Prescale Register specifies the maximum value for the Prescale Counter.Table 6-6: Prescale Register (PR, address 0x4001 000C (CT16B0) and 0x4001 400C (CT16B1)) bit descriptionBit Symbol Description Reset value15:0 PCVAL Prescale value. 031:16 - Reserved. -6.3.5 Prescale Counter RegisterThe 16-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the timer counter. Thisallows control of the relationship between the resolution of the timer and the maximum time before the timer overflows. ThePrescale Counter is incremented on every PCLK. When it reaches the value stored in the Prescale Register, the TimerCounter is incremented, and the Prescale Counter is reset on the next PCLK.This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, etc..www.xinnovatech.com 151

XN12L612Table 6-7: Prescale Counter Register (PC, address 0x4001 0010 (CT16B0) and 0x4001 4010 (CT16B1)) bit descriptionBit Symbol Description Reset value15:0 PC Prescale counter value. 031:16 - Reserved. -6.3.6 Match Control RegisterThe Match Control Register is used to control what operations are performed when one of the Match Register matches theTimer Counter. The function of each of the bits is shown in the following table.Table 6-8: Match Control Register (MCR, address 0x4001 0014 (CT16B0) and 0x4001 4014 (CT16B1)) bit descriptionBit Symbol Value Description Reset value0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the0TC.1 Enabled0 Disabled1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 01 Enabled0 Disabled2 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR00matches the TC.1 Enabled0 Disabled3 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the0TC.1 Enabled0 Disabled4 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 01 Enabled0 Disabled5 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR10matches the TC.1 Enabled0 Disabled6 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the0TC.1 Enabled0 Disabled7 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 01 Enabled0 Disabled152 www.xinnovatech.com

XN12L6128 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR20matches the TC.1 Enabled0 Disabled9 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the0TC.1 Enabled0 Disabled10 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 01 Enabled0 Disabled11 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR30matches the TC.1 Enabled0 Disabled31:12 Reserved. NA6.3.7 Match RegistersThe Match Register values are continuously compared to the timer counter value. When the two values are equal, actionscan be triggered automatically. The action possibilities are to generate an interrupt, reset the timer counter, or stop the timer.Actions are controlled by the settings in the MCR register.Table 6-9: Match Registers (MR0 to 3, addresses 0x4001 0018 to 24 (CT16B0) and 0x4001 4018 to 24 (CT16B1)) bit descriptionBit Symbol Description Reset value15:0 MATCH Timer counter match value. 031:16 - Reserved. - NA6.3.8 Capture Control RegisterThe Capture Control Register is used to control whether the Capture Register is loaded with the value in the counter/timerwhen the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the rising and fallingbits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below, "n"represents the timer number, 0 or 1. The capture channels 2 and 3 are connected to the edge and level outputs of thecomparators. In the description below, “n” also represents the comparator number, 0 or 1. Comparator 0 is connected toCT16B0, and comparator 1 is connected to CT16B1.Table 6-2: Capture Control Register (CCR, address 0x4001 0028 (CT16B0) and 0x4001 4028 (CT16B1)) bit descriptionBit Symbol Value Description Reset value0 CAP0RE Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on01 Enabled.0 Disabled.CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.www.xinnovatech.com 153

XN12L6121 CAP0FE Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on01 Enabled.0 Disabled.CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC.2 CAP0I Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event01 Enabled.0 Disabled.will generate an interrupt.3 CAP1RE Capture on CT16Bn_CAP1 rising edge: a sequence of 0 then 1 on01 Enabled.0 Disabled.CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.4 CAP1FE Capture on CT16Bn_CAP1 falling edge: a sequence of 1 then 0 on01 Enabled.0 Disabled.CT16Bn_CAP1 will cause CR1 to be loaded with the contents of TC.5 CAP1I Interrupt on CT16Bn_CAP1 event: a CR1 load due to a CT16Bn_CAP1 event01 Enabled.0 Disabled.will generate an interrupt.6 CAP2RE Capture on comparator n level output - rising edge: a sequence of 0 then 1 on01 Enabled.0 Disabled.the comparator n output will cause CR2 to be loaded with the contents of TC.7 CAP2FE Capture on comparator n level output - falling edge: a sequence of 1 then 0 on01 Enabled.0 Disabled.comparator n output will cause CR2 to be loaded with the contents of TC.8 CAP2I Interrupt on comparator n level output event: a CR2 load due to a comparator 001 Enabled.0 Disabled.event will generate an interrupt.9 CAP3RE Capture on comparator n edge output - rising edge: a sequence of 0 then 1 on01 Enabled.0 Disabled.the comparator n output will cause CR3 to be loaded with the contents of TC.10 CAP3FE Capture on comparator n edge output - falling edge: a sequence of 1 then 0 on01 Enabled.0 Disabled.comparator n output will cause CR3 to be loaded with the contents of TC.154 www.xinnovatech.com

XN12L61211 CAP3I Interrupt on comparator n edge output event: a CR3 load due to a comparator n0event will generate an interrupt.1 Enabled.0 Disabled.31:12 - Reserved NA6.3.9 Capture RegistersEach Capture Register is associated with a device pin and may be loaded with the counter/timer value when a specifiedevent occurs on that pin. The settings in the capture control register determine whether the capture function is enabled, andwhether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges.Table 6-3: Capture Registers (CR0 to 3, addresses 0x4001 002C to 38 (CT16B0) and 0x4001 402C to 38 (CT16B1)) bit descriptionBit Symbol Description Reset value15:0 CAP Timer counter capture value. 031:16 - Reserved. NA6.3.10 External Match RegisterThe External Match Register provides both control and status of the external match pins CT16Bn_MAT[1:0]. Match eventsfor match 0 and match 1 in each timer can cause a DMA request.Table 6-4: External Match Register (EMR, address 0x4001 003C (CT16B0) and 0x4001 403C (CT16B1)) bit descriptionBit Symbol Value Description Reset value0 EM0 External match 0. This bit reflects the state of output0CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin.When a match occurs between the TC and MR0, this bit can either toggle, goLOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output.This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function isselected in the IOCON registers (0 = LOW, 1 = HIGH).1 EM1 External match 1. This bit reflects the state of output0CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin.When a match occurs between the TC and MR1, this bit can either toggle, goLOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output.This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function isselected in the IOCON registers (0 = LOW, 1 = HIGH).2 EM2 External match 2. This bit reflects the state of match channel 2. When a match0occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, ordo nothing. Bits EMR[9:8] control the functionality of this output.3 EM3 External match 3. This bit reflects the state of output of match channel 3. When a0match occurs between the TC and MR3, this bit can either toggle, go LOW, goHIGH, or do nothing. Bits EMR[11:10] control the functionality of this output.5:4 EMC0 External match Control 0. Determines the functionality of external match 0. Table00230 shows the encoding of these bits.www.xinnovatech.com 155

XN12L61200 Do Nothing.01 Clear the corresponding external match bit/output to 0 (CT16Bi_MAT0 pin is LOWif pinned out).10 Set the corresponding external match bit/output to 1 (CT16Bi_MAT0 pin is HIGH ifpinned out).11 Toggle the corresponding external match bit/output.7:6 EMC1 External match Control 1. Determines the functionality of external match 1. 0000 Do Nothing.01 Clear the corresponding external match bit/output to 0 (CT16Bi_MAT1 pin is LOWif pinned out).10 Set the corresponding external match bit/output to 1 (CT16Bi_MAT1 pin is HIGH ifpinned out).11 Toggle the corresponding external match bit/output.9:8 EMC2 External match control 2. Determines the functionality of external match 2. 0000 Do Nothing.01 Clear the corresponding external match bit/output to 0 (CT16Bi_MAT2 pin is LOWif pinned out).10 Set the corresponding external match bit/output to 1 (CT16Bi_MAT2 pin is HIGH ifpinned out).11 Toggle the corresponding external match bit/output.11: 10 EMC3 External match control 3. Determines the functionality of external match 3. Table00230 shows the encoding of these bits.00 Do Nothing.01 Clear the corresponding external match bit/output to 0 (CT16Bi_MAT3 pin is LOWif pinned out).10 Set the corresponding external match bit/output to 1 (CT16Bi_MAT3 pin is HIGH ifpinned out).11 Toggle the corresponding external match bit/output.31: 12 - - Reserved. NATable 6-5: External match controlEMR[11:10], EMR[9:8],FunctionEMR[7:6], or EMR[5:4]00 Do Nothing.01 Clear the corresponding external match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out).10 Set the corresponding external match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out).11 Toggle the corresponding external match bit/output.DMA operationDMA requests are generated by 0 to 1 transitions of the external match 0 bit of each timer. In order to have an effect, the156 www.xinnovatech.com

XN12L612GPDMA must be configured and the relevant timer DMA request selected as a DMA source. When a timer is initially set upto generate a DMA request, the request may already be asserted before a match condition occurs. An initial DMA requestmay be avoided by having software write a one to clear the timer interrupt flag. A DMA request will be automatically clearedvia hardware by the DMA controller after servicing.If the EMR bits are set to 10 or 11 for channel 0 (rising edge or toggle), a DMA request is generated even if thecorresponding MR register is set to 0 because a match-on-zero condition exists. To disable any DMA requests, set the EMRbits for channel 0 to 00.6.3.11 Count Control RegisterThe Count Control Register is used to select between timer and counter mode, and in counter mode to select the pins andedge(s) for counting. When counter mode is chosen as a mode of operation, the CAP input (selected by the CTCR PRISELand SECSEL) is sampled on every rising edge of the PCLK clock. After comparing two consecutive samples of this CAPinput, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in the level ofthe selected CAP input. Only if the identified event occurs, and the event corresponds to the one selected by bits 2:0 in theCTCR register, will the Timer Counter register be incremented. Effective processing of the externally supplied clock to thecounter has some limitations.Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, thefrequency of the CAP input can not exceed one half of the PCLK clock. Consequently, the duration of the HIGH/LOW levelson the same CAP input in this case can not be shorter than 1/PCLK.Bits 7:4 of this register are also used to enable and configure the capture-clears-timer feature. This feature allows for adesignated edge on a particular CAP input to reset the timer to all zeros. Using this mechanism to clear the timer on theleading edge of an input pulse and performing a capture on the trailing edge, permits direct pulse-width measurement usinga single capture input without the need to perform a subtraction operation in software.Table 6-6: Count Control Register (CTCR, address 0x4001 0070 (CT16B0) and 0x4001 4070 (CT16B1)) bit descriptionBit Symbol Value Description Reset value2:0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment00Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC).Remark: If Counter mode is selected in the CTCR, bits 2:0 in the Capture ControlRegister (CCR) must be programmed as 000.000 Timer Mode: every rising PCLK edge001 Counter Mode: TC is incremented on rising edges on the CAP input selected byPRISEL(bit 11:8)010 Counter Mode: TC is incremented on falling edges on the CAP input selected byPRISEL(bit 11:8)011 Edge Count Mode: TC is incremented on both edges on the CAP input selected bybits PRISEL(bit 11:8)100 Quadrature increment position encoder mode.101 Trigger count mode.www.xinnovatech.com 157

XN12L612110 Signed count mode.111 Gate count mode.3 - - Reserved4 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the0capture-edge event specified in bits 7:5 occurs.7:5 SELCC When bit 4 is a 1, these bits select which capture input edge will cause the timer and000prescaler to be cleared. These bits have no effect when bit 4 is low.000 Rising Edge of CAP0 clears the timer (if bit 4 is set)001 Falling Edge of CAP0 clears the timer (if bit 4 is set)010 Rising Edge of CAP1 clears the timer (if bit 4 is set)011 Falling Edge of CAP1 clears the timer (if bit 4 is set)100 Rising Edge of CAP2 clears the timer (if bit 4 is set)101 Falling Edge of CAP2 clears the timer (if bit 4 is set)110 Rising Edge of CAP3 clears the timer (if bit 4 is set)111 Falling Edge of CAP3 clears the timer (if bit 4 is set)11:8 PRISEL Primary clock source select.0000 Capture pin 0.0001 Capture pin 1.0010 Comparator 0.0011 Comparator 1..0100 Reserved0101 CT16B1_MAT0./ CT16B0_MAT00110 CT32B0_MAT0.0111 CT32B1_MAT0.1xxxPrescale counter000015:12 SECSEL Secondary clock source select.0000 Capture pin 0.0001 Capture pin 1.0010 Comparator 0.0011 Comparator 1..0100 Reserved0101 CT16B1_MAT0./ CT16b0_MAT00110 CT32B0_MAT0.0111 CT32B1_MAT0.1xxxPrescale counter000016 IPS Secondary source input polarity select.0 No invert polarity of secondary source input1 Invert polarity of secondary source input031: 17 - - Reserved. NA158 www.xinnovatech.com

XN12L6126.3.11.1 Edge Count ModeWhen the count mode field is set to edge count mode, the counter will count both edges of the selected external clock source.This mode is useful for counting the changes in the external environment such as a simple encoder wheel.6.3.11.2 Quadrature Count ModeWhen the count mode field is set to quadrature mode, the counter will decode the primary and secondary external inputs asquadrature encoded signals. Quadrature signals are usually generated by rotary or linear sensors used to monitormovement of motor shafts or mechanical equipment. The quadrature signals are square waves, 90° out-of-phase. Thedecoding of quadrature signal provides both count and direction information. A timing diagram illustrating the basic operationof a quadrature incremental position encoder is provided in the following figure.PHASE A(Primary)PHASE B(Secondary)COUNT+1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1Figure 6-2: Quadrature incremental position encoder6.3.11.3 Triggered Count ModeWhen the count mode field is set to trigger count, the counter will begin counting the primary clock source after a positivetransition of the secondary input occurs. The counting will continue until a compare event occurs, or another positive inputtransition is detected. If a second input transition occurs before a terminal count is reached, counting will stop. Subsequentsecondary input transitions will continue to cause the counting to restart and stop until a compare event occurs.PrimarySecondaryCOUNT 0 1 2 3 456 7 8Figure 6-3: Triggered count mode6.3.11.4 Signed Count ModeWhen the count Mode field is set to 110, the counter counts the primary clock source while the selected secondary sourceprovides the selected count direction (up/down).PrimarySecondaryCOUNT 0 1 2 3 4 3 2 1 0 1 2 3 4 5Figure 6-4: Signed Count Modewww.xinnovatech.com 159

XN12L6126.3.11.5 Gated Count ModeWhen the count mode field is set to 111, the counter will count while the selected secondary input signal is high. This modeis used to time the duration of external events. If the selected input is inverted by setting the Input Polarity Select (IPS) bit,the counter will count while the selected secondary input is low.PrimarySecondaryCOUNT 0 1 2 3 456 7 8 9Figure 6-5: Gated Count Mode6.3.12 Timer PWM Control registerThe PWM Control Register is used to configure the match outputs as PWM outputs. Each match output can beindependently set to perform either as PWM output or as match output whose function is controlled by the external matchregister (EMR). For each timer, a maximum of three single edge controlled PWM outputs can be selected on theCT16Bn_MAT[1:0] outputs. One additional match register determines the PWM cycle length. When a match occurs in any ofthe other match registers, the PWM output is set to HIGH. The timer is reset by the match register that is configured to setthe PWM cycle length. When the timer is reset to zero, all currently HIGH match outputs configured as PWM outputs arecleared.Table 6-7: PWM Control Register (PWMC, address 0x4001 0074 and 0x4001 4074 (CT16B1)) bit descriptionBit Symbol Value Description Reset value0 PWMEN0 PWM mode enable for channel0. 00 CT16Bi_MAT0 is controlled by EM0.1 PWM mode is enabled for CT16Bi_MAT0.1 PWMEN1 PWM mode enable for channel1. 00 CT16Bi_MAT01 is controlled by EM1.1 PWM mode is enabled for CT16Bi_MAT1.2 PWMEN2 PWM mode enable for channel2. 00 CT16Bi_MAT2 is controlled by EM2.1 PWM mode is enabled for CT16Bi_MAT2.3 PWMEN3 PWM mode enable for channel3. 00 CT16Bi_MAT3 is controlled by EM3.1 PWM mode is enabled for CT16Bi_MAT3.31:4 - Reserved NA6.3.12.1 Rules for Single Edge Controlled PWM Outputs1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle (timer is set to zero) unless theirmatch value is equal to zero.2. Each PWM output will go HIGH when its match value is reached. If no match occurs (i.e. the match value is greater thanthe PWM cycle length), the PWM output remains continuously LOW.160 www.xinnovatech.com

XN12L6123. If a match value larger than the PWM cycle length is written to the match register, and the PWM signal is HIGH already,then the PWM signal will be cleared on the next start of the next PWM cycle.4. If a match register contains the same value as the timer reset value (the PWM cycle length), then the PWM output will bereset to LOW on the next clock tick. Therefore, the PWM output will always consist of a one clock tick wide positive pulsewith a period determined by the PWM cycle length (i.e. the timer reload value).5. If a match register is set to zero, then the PWM output will go to HIGH the first time the timer goes back to zero and willstay HIGH continuously.Note: When the match outputs are selected to perform as PWM outputs, the timer reset (MRnR) and timer stop (MRnS) bits in the MatchControl Register MCR must be set to zero except for the match register setting the PWM cycle length. For this register, set the MRnR bit toone to enable the timer reset when the timer value matches the value of the corresponding match register.PWM2/MAT2MR2 = 100PWM1/MAT1MR1 = 41PWM0/MAT0MR0 = 650 41 65 100(counter is reset)Figure 6-6: Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and MAT 3:0 enabled as PWMoutputs by the PWCON register.www.xinnovatech.com 161

XN12L6127 32-Bit Timer/Counter7.1 General DescriptionSimilar to 16-bit Timer/Counter, XN12L612 has two multi functions 32-bit counters/timers. The timer/counter clocks areprovided by system clock, which is controlled by the SYSAHBCLKDIV. And can also disabled by AHB control register forpower saving. The following are main features:• Programmable 32-bit prescaler to timer/counter clock.• Normal Counter or timer operation plus:– Edge count mode– Gated count Mode– Quadrature count mode– Trigger count Mode– Signed count mode• 32-bit capture channels that can take a snapshot of the timer value when an input signal transitions. A capture event mayalso optionally generate an interrupt.• The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easypulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on thetrailing edge.• Four 32-bit match registers that allow:– Continuous operation with optional interrupt generation on match.– Stop timer on match with optional interrupt generation.– Reset timer on match with optional interrupt generation.• Two external outputs corresponding to match registers with the following capabilities:– Set LOW on match.– Set HIGH on match.– Toggle on match.– Do nothing on match.• For each timer, up to four match registers can be configured as PWM allowing to use up to two match outputs as singleedge controlled PWM outputs.• Up to two match registers can be used to generate timed DMA requests.162 www.xinnovatech.com

XN12L612CAPTURE REGISTER 3CAPTURE REGISTER 2CAPTURE GEGISTER 1CAPTURE REGISTER 0MATCH REGISTER 3MATCH REGISTER 2MATCH REGISTER 1MATCH REGISTER 0CAPTURE CONTROL REGISTERMATCH CONTROL REGISTERENTERNAL MATCH REGISTERINTERRUPT REGISTERCONTROL==LOAD[3:0]==MAT[3:0]INTERRUPTCAP[3:0]TIMER CONTROLREGISTERReset/EnableTIMER COUNTER+ -COUNT/Edge CNTQUADCNTGATECNTTRIGGERCNTSIGNEDCNTPRISECSOURCE SELMAXVALPRESCALE REGISTERPRESCALECOUNTERCAP[3:0]C16B MATOther C32B MATPCLKFigure 7-1: 32-bit counter/timer block diagram7.2 Pin DescriptionTable 7-1: Counter/timer pin descriptionPin Type DescriptionCT32B0_CAP[3:0]CT32B1_CAP[3:0]InputCapture Signals:A transition on a capture pin can be configured to load one of the capture registers with thevalue in the timer counter and optionally generate an interrupt. The counter/timer block canselect a capture signal as a clock source instead of the PCLK derived clock.www.xinnovatech.com 163

XN12L612CT32B0_MAT[3:0]CT32B1_MAT[3:0]OutputExternal Match Output of CT32B0/1:When a match register MR3:0 equals the timer counter (TC), this output can eithertoggle, go LOW, go HIGH, or do nothing. The external match register (EMR) and thePWM Control register (PWMCON) control the functionality of this output.7.3 Register Description32-bit counter/timer0 contains the registers shown in the following table.Table 7-2: Register overview: 32-bit counter/timer (CT32B0 base address 0x4001 8000; CT32B1 base address 0x4001 C000)Symbol Access Address offset Description Reset valueIR R/W 0x000 Interrupt Register. The IR can be written to clear interrupts. The IR can be0read to identify which of eight possible interrupt sources are pending.TCR R/W 0x004 Timer Control Register. The TCR is used to control the timer counter0functions. The timer counter can be disabled or reset through the TCR.TC R/W 0x008 Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK.0The TC is controlled through the TCR.PR R/W 0x00C Prescale Register. When the Prescale Counter (below) is equal to this0value, the next clock increments the TC and clears the PC.PC R/W 0x010 Prescale Counter. The 32-bit PC is a counter which is incremented to the0value stored in PR. When the value in PR is reached, the TC isincremented and the PC is cleared. The PC is observable and controllablethrough the bus interface.MCR R/W 0x014 Match Control Register. The MCR is used to control if an interrupt is0generated and if the TC is reset when a Match occurs.MR0 R/W 0x018 Match Register 0. MR0 can be enabled through the MCR to reset the TC,0stop both the TC and PC, and/or generate an interrupt every time MR0matches the TC.MR1 R/W 0x01C Match Register 1. See MR0 description. 0MR2 R/W 0x020 Match Register 2. See MR0 description. 0MR3 R/W 0x024 Match Register 3. See MR0 description. 0CCR R/W 0x028 Capture Control Register. The CCR controls which edges of the capture0inputs are used to load the capture registers and whether or not an interruptis generated when a capture takes place.CR0 RO 0x02C Capture Register 0. CR0 is loaded with the value of TC when there is an0event on the CT32B0_CAP0 input.CR1 RO 0x030 Capture Register 1. CR1 is loaded with the value of TC when there is an0event on the CT32B0_CAP1 input.CR2 RO 0x034 Capture Register 2. CR2 is loaded with the value of TC when there is an0event on the CT32B0_CAP2 input.164 www.xinnovatech.com

XN12L612CR3 RO 0x038 Capture Register 3. CR3 is loaded with the value of TC when there is an0event on the CT32B3_CAP3 input.EMR R/W 0x03C External Match Register. The EMR controls the match function and the0external match pins CT32Bn_MAT[3:0].- - 0x040 - 0x06C reserved -CTCR R/W 0x070 Count Control Register. The CTCR selects between timer and counter0mode, and in Counter mode selects the signal and edge(s) for counting.PWMC R/W 0x074 PWM Control Register. The PWMCON enables PWM mode for the external0match pins CT32Bn_MAT[3:0].7.3.1 Interrupt RegisterThe Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts. If an interrupt isgenerated then the corresponding bit in the IR will be HIGH. Otherwise, the bit will be LOW. Writing a logic one to thecorresponding IR bit will reset the interrupt. Writing a zero has no effect. Clearing an interrupt for timer match also clears anycorresponding DMA request.Table 7-3: Interrupt Register (IR, address 0x4001 8000 (CT32B0) and IR, address 0x4001 C000) bit descriptionBit Symbol Description Reset value0 MR0INT Interrupt flag for match channel 0. 01 MR1INT Interrupt flag for match channel 1. 02 MR2INT Interrupt flag for match channel 2. 03 MR3INT Interrupt flag for match channel 3. 04 CR0INT Interrupt flag for capture channel 0 event. 05 CR1INT Interrupt flag for capture channel 1 event. 06 CR2INT Interrupt flag for capture channel 2 event. 07 CR3INT Interrupt flag for capture channel 3 event. 031:8 - Reserved - 07.3.2 Timer Control RegisterThe Timer Control Register is used to control the operation of the counter/timer.Table 7-4: Timer Control Register (TCR, address 0x4001 8004 (CT32B0) and 0x4001 C004 (CT32B1)) bit descriptionBit Symbol Value Description Reset value0 CEN Counter enable. 00 The counters are disabled.1 The Timer Counter and Prescale Counter are enabled for counting.1 CRST Counter reset. 00 Do nothing.1 The Timer Counter and the Prescale Counter are synchronously reset on thenext positive edge of PCLK. The counters remain reset until TCR[1] isreturned to zero.www.xinnovatech.com 165

XN12L61231: 14 - - Reserved. N/A7.3.3 Timer Counter RegisterThe 32-bit Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset beforereaching its upper limit, the TC will count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000.This event does not cause an interrupt, but a match register can be used to detect an overflow if needed.Table 7-5: Timer counter register (TC, address 0x4001 8008 (CT32B0) and 0x4001 5C008 (CT32B1)) bit descriptionBit Symbol Description Reset value31:0 TC Timer counter value. 07.3.4 Prescale RegisterThe 32-bit Prescale Register specifies the maximum value for the Prescale Counter.Table 7-6: Prescale register (PR, address 0x4001 800C (CT32B0) and 0x4001 5C00C (CT32B1)) bit descriptionBit Symbol Description Reset value31:0 PCVAL Prescaler value. 07.3.5 Prescale Counter RegisterThe 32-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter. Thisallows control of the relationship between the resolution of the timer and the maximum time before the timer overflows. ThePrescale Counter is incremented on every PCLK. When it reaches the value stored in the Prescale Register, the TimerCounter is incremented, and the Prescale Counter is reset on the next PCLK.This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when PR = 1, etc.Table 7-7: Prescale Register (PC, address 0x4001 8010 (CT32B0) and 0x4001 5C010 (CT32B1)) bit descriptionBit Symbol Description Reset value31:0 PC Prescale counter value. 07.3.6 Match Control RegisterThe Match Control Register is used to control what operations are performed when one of the Match Register matches theTimer Counter.Table 7-8: Match Control Register (MCR, address 0x4001 8014 (CT32B0) and 0x4001 C014 (CT32B1)) bit descriptionBit Symbol Value Description Reset value0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in0the TC.1 Enabled0 Disabled1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 01 Enabled0 Disabled166 www.xinnovatech.com

XN12L6122 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if01 Enabled0 DisabledMR0 matches the TC.3 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in0the TC.1 Enabled0 Disabled4 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 01 Enabled0 Disabled5 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if01 Enabled0 DisabledMR1 matches the TC.6 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in0the TC.1 Enabled0 Disabled7 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 01 Enabled0 Disabled8 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if01 Enabled0 DisabledMR2 matches the TC.9 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in0the TC.1 Enabled0 Disabled10 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 01 Enabled0 Disabled11 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if0MR3 matches the TC.1 Enabled0 Disabled31:12 Reserved NAwww.xinnovatech.com 167

XN12L6127.3.7 Match RegistersThe Match Register values are continuously compared to the timer counter value. When the two values are equal, actionscan be triggered automatically. The action possibilities are to generate an interrupt, reset the timer counter, or stop the timer.Actions are controlled by the settings in the MCR register.Table 7-9: Match Registers (MR0 to 3, addresses 0x4001 8018 to 24 (CT32B0) and 0x4001 C018 to 24 (CT32B1)) bit descriptionBit Symbol Description Reset value31:0 MATCH Timer counter match value. 07.3.8 Capture Control RegisterThe Capture Control Register is used to control whether one of the four capture registers is loaded with the value in the timercounter when the capture event occurs, and whether an interrupt is generated by the capture event. Setting both the risingand falling bits at the same time is a valid configuration, resulting in a capture event for both edges. In the description below,“n” represents the Timer number, 0 or 1.Table 7-10: Capture Control Register (CCR, address 0x4001 8028 (CT32B0) and 0x4001 C028 (CT32B1)) bit descriptionBit Symbol Value Description Reset value0 CAP0RE 1 Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on01 Enabled.0 Disabled.CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.1 CAP0FE 1 Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on01 Enabled.0 Disabled.CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC.2 CAP0I Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP001 Enabled.0 Disabled.event will generate an interrupt.3 CAP1RE Capture on CT32Bn_CAP1 rising edge: a sequence of 0 then 1 on01 Enabled.0 Disabled.CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.4 CAP1FE Capture on CT32Bn_CAP1 falling edge: a sequence of 1 then 0 on01 Enabled.0 Disabled.CT32Bn_CAP1 will cause CR1 to be loaded with the contents of TC.5 CAP1I Interrupt on CT32Bn_CAP1 event: a CR1 load due to a CT32Bn_CAP101 Enabled.event will generate an interrupt.168 www.xinnovatech.com

XN12L6120 Disabled.6 CAP2RE Capture on CT32Bn_CAP2 rising edge: a sequence of 0 then 1 on01 Enabled.0 Disabled.CT32Bn_CAP2 will cause CR2 to be loaded with the contents of TC.7 CAP2FE Capture on CT32Bn_CAP2 falling edge: a sequence of 1 then 0 on01 Enabled.0 Disabled.CT32Bn_CAP2 will cause CR2 to be loaded with the contents of TC.8 CAP2I Interrupt on CT32Bn_CAP2 event: a CR2 load due to a CT32Bn_CAP201 Enabled.0 Disabled.event will generate an interrupt.9 CAP3RE Capture on CT32Bn_CAP3 rising edge: a sequence of 0 then 1 on01 Enabled.0 Disabled.CT32Bn_CAP3 will cause CR3 to be loaded with the contents of TC.10 CAP3FE Capture on CT32Bn_CAP3 falling edge: a sequence of 1 then 0 on01 Enabled.0 Disabled.CT32Bn_CAP3 will cause CR3 to be loaded with the contents of TC.11 CAP3I Interrupt on CT32Bn_CAP3 event: a CR3 load due to a CT32Bn_CAP301 Enabled.0 Disabled.event will generate an interrupt.31:12 - - Reserved, user software should not write ones to reserved bits. The valueNAread from a reserved bit is not defined.7.3.9 Capture RegisterEach Capture Register is associated with a device pin and may be loaded with the timer counter value when a specifiedevent occurs on that pin. The settings in the capture control register determine whether the capture function is enabled, andwhether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges.Table 7-11: Capture Registers (CR0 to 3, addresses 0x4001 802C to 38 (CT32B0) and 0x4001 C02C to 38 (CT32B1)) bit descriptionBit Symbol Description Reset value31:0 CAP Timer counter capture value. 07.3.10 External Match RegisterThe External Match Register provides both control and status of the external match pins CAP32Bn_MAT[3:0]. Match eventsfor match 0 and match 1 in each timer can cause a DMA request. If the match outputs are configured as PWM output, thefunction of the external match registers is determined by the PWM rules.www.xinnovatech.com 169

XN12L612Table 7-12: External Match Register (EMR, address 0x4001 803C (CT32B0) and 0x4001 C03C (CT32B1)) bit descriptionBit Symbol Value Description Reset value0 EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0,0whether or not this output is connected to its pin. When a match occursbetween the TC and MR0, this bit can either toggle, go LOW, go HIGH, or donothing. Bits EMR[5:4] control the functionality of this output. This bit isdriven to the CT32B0_MAT0/CT32B1_MAT0 pins if the match function isselected in the IOCON registers (0 = LOW, 1 = HIGH).1 EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1,0whether or not this output is connected to its pin. When a match occursbetween the TC and MR1, this bit can either toggle, go LOW, go HIGH, or donothing. Bits EMR[7:6] control the functionality of this output. This bit isdriven to the CT32B0_MAT1/CT32B1_MAT1 pins if the match function isselected in the IOCON registers (0 = LOW, 1 = HIGH).2 EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2,0whether or not this output is connected to its pin. When a match occursbetween the TC and MR2, this bit can either toggle, go LOW, go HIGH, or donothing. Bits EMR[9:8] control the functionality of this output. This bit isdriven to the CT32B0_MAT2/CT32B1_MAT2 pins if the match function isselected in the IOCON registers (0 = LOW, 1 = HIGH).3 EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3,0whether or not this output is connected to its pin. When a match occursbetween the TC and MR3, this bit can either toggle, go LOW, go HIGH, or donothing. Bits EMR[11:10] control the functionality of this output. This bit isdriven to the CT32B3_MAT0/CT32B1_MAT3 pins if the match function isselected in the IOCON registers (0 = LOW, 1 = HIGH).5:4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 0000 Do Nothing.11 Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin isLOW if pinned out).10 Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin isHIGH if pinned out).11 Toggle the corresponding External Match bit/output.7:6 EMC1 External Match Control 1. Determines the functionality of External Match 1. 0000 Do Nothing.11 Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin isLOW if pinned out).10 Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin isHIGH if pinned out).11 Toggle the corresponding External Match bit/output.9:8 EMC2 External Match Control 2. Determines the functionality of External Match 2. 00170 www.xinnovatech.com

XN12L61200 Do Nothing.11 Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin isLOW if pinned out).10 Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin isHIGH if pinned out).11 Toggle the corresponding External Match bit/output.11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3. 0000 Do Nothing.11 Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin isLOW if pinned out).10 Set the corresponding External Match bit/output to 1 (CT32Bi_MAT3 pin isHIGH if pinned out).11 Toggle the corresponding External Match bit/output.31:12 - Reserved, user software should not write ones to reserved bits. The valueNAread from a reserved bit is not defined.Table 7-13: External match controlEMR[11:10], EMR[9:8],FunctionEMR[7:6], or EMR[5:4]00 Do Nothing.01 Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).10 Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).11 Toggle the corresponding External Match bit/output.DMA operationDMA requests are generated by 0 to 1 transitions of the external match 0 bit of each timer. In order to have an effect, theGPDMA must be configured and the relevant timer DMA request selected as a DMA source. When a timer is initially set upto generate a DMA request, the request may already be asserted before a match condition occurs. An initial DMA requestmay be avoided by having software write a one to clear the timer interrupt flag. A DMA request will be automatically clearedvia hardware by the DMA controller after servicing.If the EMR bits are set to 10 or 11 for channel 0 (rising edge or toggle), a DMA request is generated even if thecorresponding MR register is set to 0 because a match-on-zero condition exists. To disable any DMA requests, set the EMRbits for channel 0 to 00.7.3.11 Count Control RegisterThe Count Control Register is used to select between timer and counter mode, and in counter mode to select the pins andedge(s) for counting. Same as 16 bits timer/counter, there are When Counter Mode is chosen as a mode of operation, theCAP input (selected by the CTCR PRISEL and SECSEL, depend on counter mode) is sampled on every rising edge of thePCLK clock. After comparing two consecutive samples of this CAP input, one of the following four events is recognized:www.xinnovatech.com 171

XN12L612rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. Only if the identified eventoccurs, and the event corresponds to the one selected by CTM(bits 2:0) in the CTCR register, will the timer counter registerbe incremented. Effective processing of the externally supplied clock to the counter has some limitations. Since twosuccessive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input, the frequency ofthe CAP input can not exceed one half of the PCLK clock. Consequently, duration of the HIGH/LOWLOW levels on the sameCAP input in this case can not be shorter than 1/PCLK. Bits 7:4 of this register are also used to enable and configure thecapture-clears-timer feature. This feature allows for a designated edge on a particular CAP input to reset the timer to allzeros. Using this mechanism to clear the timer on the leading edge of an input pulse and performing a capture on the trailingedge, permits direct pulse-width measurement using a single capture input without the need to perform a subtractionoperation in software.Table 7-14: Count Control Register (CTCR, address 0x4001 8070 (CT32B0) and 0x4001 C070 (CT32B1)) bit descriptionBit Symbol Value Description Reset value2:0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment00Timer’s Prescale Counter (PC), or clear PC and increment Timer Counter (TC).Remark: If Counter mode is selected in the CTCR, bits 2:0 in the Capture ControlRegister (CCR) must be programmed as 000.000 Timer Mode: every rising PCLK edge001 Counter Mode: TC is incremented on rising edges on the CAP input selected byPRISEL(bit 11:8)010 Counter Mode: TC is incremented on falling edges on the CAP input selected byPRISEL(bit 11:8)011 Edge Count Mode: TC is incremented on both edges on the CAP input selected bybits PRISEL(bit 11:8)100 Quadrature increment position encoder mode.101 Trigger count mode.110 Signed count mode.111 Gate count mode.3 - - Reserved NA4 ENCC Setting this bit to 1 enables clearing of the timer and the prescaler when the0capture-edge event specified in bits 7:5 occurs.7:5 SELCC When bit 4 is a 1, these bits select which capture input edge will cause the timer000and prescaler to be cleared. These bits have no effect when bit 4 is low.000 Rising Edge of CAP0 clears the timer (if bit 4 is set)001 Falling Edge of CAP0 clears the timer (if bit 4 is set)010 Rising Edge of CAP1 clears the timer (if bit 4 is set)011 Falling Edge of CAP1 clears the timer (if bit 4 is set)100 Rising Edge of CAP2 clears the timer (if bit 4 is set)101 Falling Edge of CAP2 clears the timer (if bit 4 is set)110 Rising Edge of CAP3 clears the timer (if bit 4 is set)111 Falling Edge of CAP3 clears the timer (if bit 4 is set)172 www.xinnovatech.com

XN12L61211:8 PRISEL Primary clock source select. 00000000 Capture pin 0.0001 Capture pin 1.0010 Capture pin 2.0011 Capture pin 3.0100 Reserved0101 CT16b1_MAT0.0110 CT32b0_MAT0.0111 CT32b1_MAT0./ CT32b0_MAT01xxxPrescale counter15:12 SECSEL Secondary clock source select. 00000000 Capture pin 0.0001 Capture pin 1.0010 Capture pin 2.0011 Capture pin 3.0100 Reserved0101 CT16b1_MAT0.0110 CT32b0_MAT0.0111 CT32b1_MAT0./ CT32b0_MAT01xxxPrescale counter16 IPS Secondary source input polarity select. 00 No invert polarity of secondary source input1 Invert polarity of secondary source input31: 17 - - Reserved. NA7.3.12 PWM Control RegisterThe PWM Control Register is used to configure the match outputs as PWM outputs. Each match output can beindependently set to perform either as PWM output or as match output whose function is controlled by the External MatchRegister (EMR). For each timer, a maximum of three single edge controlled PWM outputs can be selected on the MATn.2:0outputs. One additional match register determines the PWM cycle length. When a match occurs in any of the other matchregisters, the PWM output is set to HIGH. The timer is reset by the match register that is configured to set the PWM cyclelength. When the timer is reset to zero, all currently HIGH match outputs configured as PWM outputs are cleared.Table 7-15: PWM Control Register (PWMC, 0x4001 8074 (CT32B0) and 0x4001 C074 (CT32B1)) bit descriptionBit Symbol Value Description Reset value0 PWMEN0 PWM mode enable for channel0. 00 CT32Bi_MAT0 is controlled by EM0.1 PWM mode is enabled for CT32Bi_MAT0.1 PWMEN1 PWM mode enable for channel1. 00 CT32Bi_MAT01 is controlled by EM1.www.xinnovatech.com 173

XN12L6121 PWM mode is enabled for CT32Bi_MAT1.2 PWMEN2 PWM mode enable for channel2. 00 CT32Bi_MAT2 is controlled by EM2.1 PWM mode is enabled for CT32Bi_MAT2.3 PWMEN3 PWM mode enable for channel3. Note: It is recommended to use match0channel 3 to set the PWM cycle.0 CT32Bi_MAT3 is controlled by EM3.1 PWM mode is enabled for CT32Bi_MAT3.31:4 - - Reserved, user software should not write ones to reserved bits. The value readNAfrom a reserved bit is not defined.7.3.13 Rules for Single Edge Controlled PWM Outputs1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle (timer is set to zero) unless theirmatch value is equal to zero.2. Each PWM output will go HIGH when its match value is reached. If no match occurs (i.e. the match value is greaterthan the PWM cycle length), the PWM output remains continuously LOW.3. If a match value larger than the PWM cycle length is written to the match register, and the PWM signal is HIGHalready, then the PWM signal will be cleared with the start of the next PWM cycle.4. If a match register contains the same value as the timer reset value (the PWM cycle length), then the PWM output willbe reset to LOW on the next clock tick after the timer reaches the match value. Therefore, the PWM output willalways consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length (i.e. thetimer reload value).5. If a match register is set to zero, then the PWM output will go to HIGH the first time the timer goes back to zero andwill stay HIGH continuously.Note: When the match outputs are selected to perform as PWM outputs, the timer reset (MRnR) and timer stop (MRnS) bits in the MatchControl Register MCR must be set to zero except for the match register setting the PWM cycle length. For this register, set the MRnR bit toone to enable the timer reset when the timer value matches the value of the corresponding match register.PWM2/MAT2MR2 = 100PWM1/MAT1MR1 = 41PWM0/MAT0MR0 = 650 41 65 100(counter is reset)Figure 7-2: Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3)andMAT3:0 enabled as PWM outputs by the PWMCON registerFigure 7-3 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the174 www.xinnovatech.com

XN12L612match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset. This gives a full lengthcycle to the match value. The interrupt indicating that a match occurred is generated in the next clock after the timerreached the match value.Figure 7-4 shows a timer configured to stop and generate an interrupt on match. The prescaler is again set to 2 and thematch register set to 6. In the next clock after the timer reaches the match value, the timer enable bit in TCR is cleared, andthe interrupt indicating that a match occurred is generated.PCLKprescalecountertimercountertimer counterreset2 0 1 2 0 1 2 0 1 2 0 14 5 6 0 1interruptFigure 7-3: A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabledPCLKprescalecountertimercountertimer counterreset2 0 1 2 04 5 61 0interruptFigure 7-4: A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabledwww.xinnovatech.com 175

XN12L6128 Watchdog Timer (WDT)8.1 General DescriptionThe watchdog timer is used to reset/interrupt microcontroller when user application running into error and fail to feedwatchdog timer. With programmable timer, the user can set timer in wide range for different application. XN12L612watchdog timer (WDT) has following major features:• Independent WDT oscillator clock source with flexible frequency set• Watchdog can trigger both reset and interrupt• Support power saving modeThe block diagram of the Watchdog is shown below in the following figure. The synchronization logic (PCLK - WDCLK) is notshown in the block diagram.feed okTCWDT_CLK24-bit down counterenable countFEEDWD TVWINDOWfeed sequenceDetect andprotectioninrangecompare0WDINTVALfeed okTC writefeed errorcompareunderflowcompareshadow bitfeed okMODregisterWDPRO TECT(MOD [4])WDTOF(MOD [2])WDINT(MOD [3])WDRESET(MOD [1])WDEN(MOD [0])chip resetwatchdoginterruptFigure 8-1: Watchdog block diagram176 www.xinnovatech.com

XN12L6128.2 Register DescriptionTable 8-1: Register overview: Watchdog timer (base address 0x4000 4000)Name Access Address offset Description Reset valueMOD R/W 0x000 Watchdog mode register. This register contains the basic0x0000 0003mode and status of the Watchdog TimerTC R/W 0x004 Watchdog timer constant register. This register determines0x0000 FFFFthe time-out value.FEED WO 0x008 Watchdog feed sequence register. Writing 0xAA followedNAby 0x55 to this register reloads the Watchdog timer withthe value contained in TC.TV RO 0x00C Watchdog timer value register. This register reads out the0xFFcurrent value of the Watchdog timer.CLKSEL R/W 0x010 Watchdog clock source selection register. 0WARNINT R/W 0x014 Watchdog Warning Interrupt compares value. 0WINDOW R/W 0x018 Watchdog Window compares value. 0xFF FFFF8.3 Watchdog Mode RegisterThe Watchdog Mode Register controls the operation of the watchdog as per the combination of WDEN and RESET bits.Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source. If a watchdoginterrupt occurs in Sleep mode, it will wake up the device.Table 8-2: Watchdog Mode Register (MOD - 0x4000 4000) bit descriptionBit Symbol Value Description Reset value0 WDEN Watchdog enable bit. The WDEN bit can be locked from subsequent writes by1the WDLOCKEN bit.0 The watchdog timer is stopped.1 The watchdog timer is running. The watchdog timer is automatically enabled atreset without requiring a valid feed sequence. Any subsequent writes to this bitrequire a valid feed sequence before the change can take effect.1 WDRESET Watchdog reset enable bit. This bit can be changed at any time. The1WDRESET bit is set by an external reset or a Watchdog timer reset. TheWDRESET bit can be locked from subsequent writes by the WDLOCKEN bit.0 A watchdog time-out will cause an interrupt.1 A watchdog timeout will cause a chip reset.2 WDTOF Watchdog time-out flag. The Watchdog time-out flag is set when the Watchdogtimes out, when a feed error occurs, or when WDPROTECT =1 and an attemptis made to write to the WDTC register. This flag is cleared by software writing a0 (Only afterexternalreset)0 to this bit. Causes a chip reset if WDRESET = 1.www.xinnovatech.com 177

XN12L6123 WDINT The Watchdog interrupt flag is set when the Watchdog counter reaches the0value specified by WDWARNINT. This flag is cleared when any reset occurs,and is cleared by software by writing a 1 to this bit.4 WDPROTECT Watchdog update mode. This bit is Set Only. Once the WDPROTECT bit is0set, it cannot be cleared by software. The WDPROTECT bit is cleared by anexternal reset or a Watchdog timer reset.0 The watchdog timer constant value (WDTC) can be changed at any time.1 The watchdog timer constant value (WDTC) can be changed only after thecounter is below the value of WARNINT and WINDOW.5 WDLOCKCLK Watchdog clock lock bit. This bit is cleared on reset and can subsequently be0written to only once to set it. Once this bit has been set, it can only be clearedthrough resetting the chip.0 The watchdog clock (WDCLK) can be disabled at any time.1 Setting this bit disables any writes to the bit or bits that control the power to thecurrently selected watchdog clock source in the power configuration registersPDRUNCFG, PDSLEEPCFG, and PDAWAKECFG. Other bits in the powerconfiguration registers are not affected. Setting the WDLOCKCLK bit ensuresthat the WDT always has a valid clock source for WDCLK provided that thewatchdog oscillator and/or the IRC are powered.Remark: Before setting the WDLOCKCLK bit, the user must enable either thewatchdog oscillator or the IRC or both in all three power configuration registersin order to keep the selected clock source running in Active, Sleep, orDeep-sleep modes. Once the WDLOCKCLK bit is set, the watchdog clocksource cannot be switched off or on. If the WDT is to be running in Deep-sleepmode, the watchdog oscillator must be enabled in the PDSLEEPCFG registerbefore setting the WDLOCKCLK bit.6 WDLOCKDP Power-down disable bit. This bit is cleared on reset and can subsequently be0written to only once to set it. Once this bit has been set, it can only be clearedthrough resetting the chip.0 Power-down mode can be entered at any time.1 The DPDEN bit in the PMU cannot be set to 1.7 WDLOCKEN Watchdog enables and reset lockout bit. This bit is cleared on reset and can0subsequently be written to only once to set it. Once this bit has been set, it canonly be cleared through resetting the chip.0 The WDEN and WDRESET bits can be written to by software any time toenable or disable watchdog operation.178 www.xinnovatech.com

XN12L6121 If this bit is set to one, all subsequent writes to the WDEN and WDRESET bitswill be blocked. The watchdog will be permanently disabled or enableddepending on the state of the WDEN bit when the WDLOCK bit was set. Thereset behavior is affected as follows:• If the watchdog is enabled and the WDRESET is bit set to one before settingthe WDLOCKEN bit, a watchdog trigger always causes a reset and thisbehavior cannot be overwritten by software.• If the watchdog is enabled and the WDRESET bit is set to zero beforesetting the WDLOCKEN bit, a watchdog trigger always causes an interrupt andthis behavior cannot be overwritten by software.31: 8 ReservedTable 8-3: Watchdog operating modes selectionWDEN WDRESET Mode of Operation0 X (0 or 1) Debug/Operate without the Watchdog running.1 0 Watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not.When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT will setthe WDINT flag and the Watchdog interrupt request will be generated.1 1 Watchdog reset mode: both the watchdog interrupt and watchdog reset are enabled.When this mode is selected, the watchdog counter reaching the value specified by WDWARNINT will setthe WDINT flag and the Watchdog interrupt request will be generated. The watchdog counter reaching zerowill reset the microcontroller.Other causes for a watchdog reset are: A watchdog feed or changing the WDTC value (if theWDPROTECT bit is set in the MOD register) before reaching the value of WDWINDOW.8.3.1 Watchdog Timer Constant RegisterThe Watchdog Timer Constant Register (TC) determines the time-out value. Every time a feed sequence occurs, the TCcontent is reloaded into the Watchdog timer. This is pre-loaded with the value 0x00 FFFF upon reset. Writing values below0xFF will cause 0xFF to be loaded into the TC. Thus the minimum time-out interval is TWDT_CLK × 256. If theWDPROTECT bit in MOD = 1, an attempt to change the value of TC before the watchdog counter is below the values ofWARNINT and WINDOW will cause a watchdog reset and set the WDTOF flag.Table 8-4: Watchdog Timer Constant Register (TC - 0x4000 4004) bit descriptionBit Symbol Description Reset value23:0 WDTC Watchdog time-out interval. 0x00 FFFF31:24 - Reserved8.3.2 Watchdog Feed RegisterWriting 0xAA followed by 0x55 to this register will reload the Watchdog timer with the WDTC value. This operation will alsostart the Watchdog if it is enabled via the MOD register. Setting the WDEN bit in the MOD register is not sufficient to enablethe Watchdog. A valid feed sequence must be completed after setting WDEN before the Watchdog is capable of generatingwww.xinnovatech.com 179

XN12L612a reset. Until then, the Watchdog will ignore feed errors. After writing 0xAA to WDFEED, access to any Watchdog registerother than writing 0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled, and sets theWDTOF flag. The reset will be generated during the second PCLK following an incorrect access to a Watchdog registerduring a feed sequence. Interrupts should be disabled during the feed sequence. An abort condition will occur if an interrupthappens during the feed sequence.Table 8-5: Watchdog Feed Register (FEED - 0x4000 4008) bit descriptionBit Symbol Description Reset value7:0 WDFEED Feed value should be 0xAA followed by 0x55. -31:8 Reserved8.3.3 Watchdog Timer Value RegisterThe Watchdog Timer Value Register is used to read the current value of Watchdog timer counter. When reading the value ofthe 24-bit counter, the lock and synchronization procedure takes up to 6 WDT_CLK cycles plus 6 PCLK cycles, so the valueof WDTV is older than the actual value of the timer when it's being read by the CPU.Table 8-6: Watchdog Timer Value Register (TV - 0x4000 400C) bit descriptionBit Symbol Description Reset value23:0 WDTV Counter timer value. 0x00 00FF31:24 - Reserved NA8.3.4 Watchdog Timer Clock Source Selection RegisterThis register allows selecting the clock source for the Watchdog timer. The clock source selection bits can be locked bysoftware using bit 31 of this register, so that they cannot be modified. In addition, changes to the clock source are ignored ifnot both the watchdog oscillator and the IRC are powered in the PDRUNCFG register. This prevents the user from switchingto a non-existing clock source. If the WDT is running in Deep-sleep mode, the watchdog oscillator must be selected as clocksource. On reset, the clock source selection bits are always unlocked.Table 8-7: Watchdog Timer Clock Source Selection Register (CLKSEL - address 0x4000 4010) bit descriptionBit Symbol Value Description Reset value1:0 WDSEL These bits select the clock source for the Watchdog timer as described below.00Warning: Improper setting of this value may result in incorrect operation of theWatchdog timer, which could adversely affect system operation. If the WDLOCKbit in this register is set, the WDSEL bits cannot be modified.Remark: Writes to the WDSEL bits are ignored if the corresponding clock sourceis powered down in the PDRUNCFG register.0x0Selects the Internal RC oscillator as the Watchdog clock source (default). In activemode only.0x1Selects the watchdog oscillator as the Watchdog clock source. Must be selected ifthe WDT is running in Deep-sleep mode.0x20x3Reserved.Reserved.180 www.xinnovatech.com

XN12L61230:2 - - Reserved. NA31 WDLOCK Lock Watchdog clock source. 00 This bit is set to 0 on any reset. It cannot be cleared by software.1 Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of thisregister cannot be modified.8.3.5 Watchdog Timer Warning Interrupt RegisterThe WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt. When thewatchdog timer counter matches the value defined by WDWARNINT, an interrupt will be generated after the subsequentWDCLK. A match of the watchdog timer counter to WDWARNINT occurs when the bottom 10 bits of the counter have thesame value as the 10 bits of WARNINT, and the remaining upper bits of the counter are all 0. This gives a maximum time of1,023 watchdog timer counts (4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. If WARNINT is setto 0, the interrupt will occur at the same time as the watchdog event.Table 8-8: Watchdog Timer Warning Interrupt Register (WARNINT - 0x4000 4014) bit descriptionBit Symbol Description Reset value9:0 WARNINT Watchdog warning interrupt compare value. 031:10 - Reserved NA8.3.6 Watchdog Timer Window RegisterThe WD WINDOW register determines the highest WDTV value allowed when a watchdog feed is performed. If a feed validsequence completes prior to WDTV reaching the value in WDWINDOW, a watchdog event will occur. WDWINDOW resets tothe maximum possible WDTV value, so windowing is not in effect. Values of WDWINDOW below 0x100 will make itimpossible to ever feed the watchdog successfully.Table 8-9: Watchdog Timer Window Register (WINDOW - 0x4000 4018) bit descriptionBit Symbol Description Reset value23:0 WDWINDOW Watchdog window value. 0xFF FFFF31:24 - Reserved NA8.4 Watchdog Timer Clock and Power ControlThe watchdog timer block uses two clocks: PCLK and WDT_CLK. PCLK is used for the APB accesses to the watchdogregisters and is derived from the system clock. The WDT_CLK is used for the watchdog timer counting and is derived fromthe WDT clock system. Two clocks can be used as a clock source for WDT_CLK clock: the IRC and the watchdog oscillator.The clock source is selected in the WDCLKSEL register, but note that the clock source may be locked by software throughthe MODE register.There is some synchronization logic between these two clock domains. When the MOD and TC registers are updated byAPB operations, the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When thewatchdog timer is WDCLK clock cycles, the synchronization logic will first lock the value of the counter on WDCLK and thensynchronize it with the PCLK for reading as the TV register by the CPU.www.xinnovatech.com 181

XN12L612The watchdog oscillator can be powered down in the PDRUNCFG register if it is not used - unless bit 5 in the MOD registeris set. The clock to the watchdog register block (PCLK) can be disabled in the AHBCLKCTRL register for power savings.8.5 Watchdog Lock FeatureThe watchdog timer operation can be locked in several ways to ensure that the WDT is always running. The lock featuresare enabled by a one-time write to the corresponding lock register bit and can only be reversed by a chip reset.The following lock mechanisms can be applied:• Lock the enable/disable state of the WDT and simultaneously whether the watchdog triggers an interrupt or a reset.• Lock the switching of clock sources. This lock mechanism prevents changing to a clock source that is powered down.• Lock the power control to any WDT clock source in the PDRUNCFG, PDSLEEPCFG, PDAWAKECFG registers.• Lock updating the WDT reload value.• Lock entering Power-down mode.Note: The lock features must be used with caution.• Ensure that the WDT clock source is selected to be powered on in all three power configuration registers PDSLEEPCFG,PDRUNCFG, and PDAWAKECFG before locking power control and the clock source select.• The watchdog oscillator must be turned on before locking power control if the WDT is used in Deep-sleep mode.8.6 Watchdog Timing ExamplesThe following figures illustrate several aspects of Watchdog Timer operation is shown below:WDCLK / 4WatchdogCounter125A 1259 1258 1257Early FeedEventWatchdogResetConditions:WINDOW = 0x1200WARNINT = 0x3FFTC = 0x2000Figure: 8-2 Early Watchdog Feed with Windowed Mode Enabled182 www.xinnovatech.com

XN12L612WDCLK / 4WatchdogCounter125A 1259 1258 1257Early FeedEventWatchdogResetConditions:WINDOW = 0x1200WARNINT = 0x3FFTC = 0x2000Figure 8-3: Correct Watchdog Feed with Windowed Mode EnabledWDCLK / 4WatchdogCounter0403 0402 0401 0400 03FF 03FE 03FD 03FC 03FB 03FA 03F9WatchdogInterruptConditions:WINDOW = 0x1200WARNINT = 0x3FFTC = 0x2000Figure 8-4: Watchdog warning interruptwww.xinnovatech.com 183

XN12L6129 xDSP9.1 General DescriptionXN12L612 integrates a mini DSP processor (known as xDSP), which is used to handle the microcontroller’s complexarithmetic operation. The xDSP is independent from the ARM core and provides a set of registers interface of software. ThexDSP performs a set of predefined functions by called from xDSP register. The xDSP_PCLK clock is provided system clockand controlled by SYSAHBCLKDIV. Like the other peripherals, the power of xDSP can be shut down for power saving. ThexDSP is able to perform the following functions:• CRC calculation• 32-bit divider• Sin• Cos• Arctan9.2 xDSP Interface Register DescriptionTable 9-1: Register overview: CRC engine (base address 0x5007 0000)Name Access Address offset Description Reset valueCRC_MODE R/W 0x00 CRC mode register 0x0000 0000CRC_SEED R/W 0x04 CRC seed register 0x0000 FFFFCRC_SUM R/W 0x08 Read: CRC checksum register0x0000 FFFFWrite: CRC data register~ ~ ~DIVIDEND R/W 0x100 32-bit divider operator: singed dividend. 0x0000 0000DIVISOR R/W 0x104 32-bit divider operator: signed divisor. 0x0000 0000QUOTIENT RO 0x108 32-bit divider result: signed quotient. 0x0000 0000~ ~ ~CORDIC_CTRL R/W 0x200 CORDIC Control register. 0x0000 0000CORDIC_X R/W 0x204 32-bit CORDIC x 0x0000 0000CORDIC_Y R/W 0x208 32-bit CORDIC y 0x0000 0000CORDIC_PH R/W 0x20C 32-bit CORDIC phase 0x0000 0000CORDIC_RLTX RO 0x210 32-bit CORDIC result x 0x0000 0000CORDIC_RLTY RO 0x214 32-bit CORDIC result y 0x0000 0000CORDIC_RLTPH RO 0x218 32-bit CORDIC result phase 0x0000 0000184 www.xinnovatech.com

XN12L61215.1.1 CRC Mode RegisterTable 9-2: CRC mode register (CRC_MODE, address 0x5007 0000) bit descriptionBit Symbol Value Description Reset value1:0 CRC_POLY CRC polynomial: 0000 CRC-CCITT polynomial01 CRC-16 polynomial1XCRC-32 polynomial2 BIT_RVS_WR Data bit order: 00 No bit order reverse for CRC_WR_DATA (per byte)1 Bit order reverse for CRC_WR_DATA (per byte)3 CMPL_WR Data complement: 00 No 1’s complement for CRC_WR_DATA1 1’s complement for CRC_WR_DATA4 BIT_RVS_SUM CRC sum bit order: 00 No bit order reverse for CRC_SUM1 Bit order reverse for CRC_SUM5 CMPL_SUM CRC sum complement: 00 No 1’s complement for CRC_SUM1 1’s complement for CRC_SUM6 SEED_OP CRC seed option set 00 Use default seed.1 Use seed register as CRC seed.7 SEED_SET - Write 1 to load seed to CRC generator. 031:8 Reserved - Always 0 when read NA15.1.2 CRC Seed RegisterTable 9-3: CRC Seed Register (CRC_SEED, address 0x5007 0004) bit descriptionBit Symbol Description Reset value31:0 CRC_SEED A write access to this register will load CRC seed value to CRC_SUM register withselected bit order and 1’s complement pre-processes.0x0000FFFFNote: Writing an access to this register will overrule the CRC calculation in progresses.15.1.3 CRC Checksum RegisterThis register is a Read-only register containing the most recent checksum.Table 9-4: CRC Checksum Register (CRC_SUM, address 0x5007 0008) bit descriptionBit Symbol Description Reset value31:0 CRC_SUM The most recent CRC sum can be read through this register with selected bit order0x0000 FFFFand 1’s complement post-processes.www.xinnovatech.com 185

XN12L61215.1.4 CRC Data RegisterThis register is a Write-only register containing the data block for which the CRC sum will be calculated.Table 9-5: CRC Data Register (CRC_DATA, address 0x5007 0008) bit descriptionBit Symbol Description Reset value31:0 CRC_WR_DATA Data written to this register will be taken to perform CRC calculation with selected bit order-and 1’s complement pre-process. Any write size 8, 16 or 32-bit are allowed and acceptback-to-back transactions.15.1.5 Dividend RegisterTable 9-6: Dividend Register (DIVIDEND, address 0x5007 0100) bit descriptionBit Symbol Description Reset value31:0 DIVIDEND Signed 32-bit dividend value. -15.1.6 Divisor RegisterTable 9-7: Divisor Register (DIVISOR, address 0x5007 0104) bit descriptionBit Symbol Description Reset value31:0 DIVISOR Signed 32-bit divisor value. -15.1.7 Quotient RegisterTable 9-8: QUOTIENT Register (QUOTIENT, address 0x5007 0108) bit descriptionBit Symbol Description Reset value31:0 QUOTIENT Signed 32-bit quotient value of dividend/divisor.. -15.1.8 CORDIC Control RegisterTable 9-9: CORDIC Control Register (CODIC_CTRL, address 0x5007 0200) bit descriptionBit Symbol Value Description Reset value4:0 RES CORDIC resolution: 000~15 Not used16~32 16~32 bit resolution to CORDIC result.5 - Reserved. 07:6 MODE CORDIC mode 0000 Do nothing01 arctan CORDIC mode.10 sin/cos CORDIC mode.31:8 - - Reserved. 015.1.9 CORDIC X RegisterTable 9-10: CORDIC X Register (CODIC_X, address 0x5007 0204) bit descriptionBit Symbol Description Reset value31:0 CORDIC_X Signed 32-bit CORDIC X value. The value range from -2 RES-1 to 2 RES-1 . The bit 31~RES shall be0extended by sign.186 www.xinnovatech.com

XN12L61215.1.10 CORDIC Y RegisterTable 9-11: CORDIC Y Register (CODIC_Y, address 0x5007 0208) bit descriptionBit Symbol Description Reset value31:0 CORDIC_Y Signed 32-bit CORDIC Y value. The value range from -2 RES-1 to 2 RES-1 . The bit 31~RES shall be0extended by sign.15.1.11 CORDIC Phase RegisterTable 9-12: CORDIC Phase Register (CODIC_PH, address 0x5007 020C) bit descriptionBit Symbol Description Reset value31:0 CORDIC_PH Signed 32-bit CORDIC phase value. The value range from -2 RES-1 to 2 RES-1 . The bit 31~RES0shall be extended by sign.15.1.12 CORDIC Operation X Result RegisterTable 9-13: CORDIC X Result Register (CODIC_RLTX, address 0x5007 0210) bit descriptionBit Symbol Description Reset value31:0 CORDIC_RLTX Read only0Signed 32-bit CORDIC operation X result value. The value range from -2 RES-1 to 2 RES-1 . The bit31~RES shall be extended by sign.15.1.13 CORDIC Operation Y Result RegisterTable 9-14: CORDIC Y Result Register (CORDIC_RLTY, address 0x5007 0214) bit descriptionBit Symbol Description Reset value31:0 CORDIC_RLTY Read only0Signed 32-bit CORDIC operation Y result value. The value range from -2 RES-1 to 2 RES-1 . Thebit 31~RES shall be extended by sign.15.1.14 CORDIC Operation Phase Result RegisterTable 9-15: CORDIC Phase Result Register (CODIC_RLTPH, address 0x5007 0218) bit descriptionBit Symbol Description Reset value31:0 CORDIC_RLTPH Read only0Signed 32-bit CORDIC operation phase result value. The value range from -2 RES-1 to 2 RES-1 .The bit 31~RES shall be extended by sign.9.3 Functions Description15.1.15 CRC CalculationThe following sections describe the register settings for each supported CRC standard:CRC-CCITT set-upPolynomial = x 16 + x 12 + x 5 + 1www.xinnovatech.com 187

XN12L612Seed Value = 0xFFFFBit order reverse for data input: NO1's complement for data input: NOBit order reverse for CRC sum: NO1's complement for CRC sum: NOCRC_MODE = 0x0000 0000CRC_SEED = 0x0000 FFFFCRC-16 set-upPolynomial = x 16 + x 15 + x 2 + 1Seed Value = 0x0000Bit order reverse for data input: YES1's complement for data input: NOBit order reverse for CRC sum: YES1's complement for CRC sum: NOCRC_MODE = 0x0000 0015CRC_SEED = 0x0000 0000CRC-32 set-upPolynomial = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1Seed Value = 0xFFFF FFFFBit order reverse for data input: YES1's complement for data input: NOBit order reverse for CRC sum: YES1's complement for CRC sum: YESCRC_MODE = 0x0000 0036188 www.xinnovatech.com

XN12L612CRC_SEED = 0xFFFF FFFF15.1.16 32-Bit DividerxDSP provides 32-bit performance-optimized signed integer division. The following steps show operations:1. Put signed dividend value to DIVIDENT register.2. Put signed divisor value to DIVISOR register.3. Read signed quotient value from QUOTIENT register15.1.17 Sin/Cos/ArctanxDSP has built-in Coordinate Rotation Digital Computer (CORDIC) algorithm to do computing of Sin, Cos and Arctan. Usethe following steps to set up xDSP CORDIC:1. Set up CORDIC resolution: xDSP CORDIC supports up to 32-bit resolutions. To have better accuracy to operation results,the CORDIC control register RES bits setting to 16~32 are recommended. The RES value decides the significant bits inall CORDIC_X, CORDIC_Y and CORDIC_PH registers.2. Set up CORDIC mode: xDSP CORDIC supports Sin, Cos and Arctan three operations. User must set up proper mode asrequired.3. Phase register input/output range: the CORDIC can only accept from -π/2 to +π/2 for phase. Convert to xDSP CORDICPhase input is mapped into -0x6487ed51 to +0x6487ed51 at 32-bit CORDIC resolution and -0x6487 (-0x6487ed51 >> 16)to +0x6487 (+0x6487ed51 >> 16) at 16-bit CORDIC resolution.4. CORDIC x, y register conversion: only bits [RES:0] in register are valid and bit RES is singed bit. The value is mapped to-1 to +1. Example: 32-bit CORDIC, -0x7fff ffff -> -1 and +0x7fff ffff -> +1.5. Sin calculation:a) Write CORDIC_PHb) Write CORDIC Mode to 10-> Sin/Cos modec) Read CORDIC_RLTY6. Cos calculation:a) Write CORDIC_PHb) Write CORDIC Mode to 10 -> Sin/Cos modewww.xinnovatech.com 189

XN12L612c) Read CORDIC_RLTX7. Arctan calculation:a) Write CORDIC_X and CORDIC_Yb) Write CORDIC Mode to 01 -> Arctan modec) Read CORDIC_RLTPH190 www.xinnovatech.com

XN12L61210 UART10.1 General DescriptionXN12L612 provides four UART peripherals: UART0, UART1, UART2 and UART3. All are able to support infraredcommunications by changing to IrDA configuration. The clock and power of the UARTs are controlled by SYSAHBCLKCTRLregister and UARTn_PCLK which is enabled in the UARTn clock divider register (See UART0CLKDIV / UART1CLKDIV /UART2CLKDIV / UART3CLKDIV).IRDAEN bitTXIrDA TransmitEncoderTXDn PinUARTIRDAEN bitRXIrDA ReceiverDecoderRXDn PinFigure 10-1: UART/IrDA block diagramTransmitter BufferShift RegisterTXTX FSMAPBInterfaceBaud Rate GeneratorRX FSMReceiver BufferShift RegisterRXFigure 10-2: UART block diagramwww.xinnovatech.com 191

XN12L61210.2 Pin DescriptionTable 10-1: UART0,1, 2, 3 pin descriptionPin Type DescriptionRXD0 Input UART0 Serial Input. Serial receive data.TXD0 Output UART0 Serial Output. Serial transmit data.RXD1 Input UART1 Serial Input. Serial receive data.TXD1 Output UART1 Serial Output. Serial transmit data.RXD2 Input UART2 Serial Input. Serial receive data.TXD2 Output UART2 Serial Output. Serial transmit data.RXD3 Input UART3 Serial Input. Serial receive data.TXD3 Output UART3 Serial Output. Serial transmit data.10.3 UART Register DescriptionEach UART has own control register set and different base address:• UART0 0x4000 8000• UART1 0x4000 C000• UART2 0x4007 0000• UART3 0x4007 4000The UART contains registers organized as shown in the following table.Table 10-2: Register overview (UART0: base address-0x4000 8000; UART1 base address-0x4000 c000; UART2: base address-0x40070000; UART3 base address-0x4007 4000)Name Access Address offset Description Reset valueUARTnRBR RO 0x000 Receiver Buffer Register. Contains the received character toNAbe read.UARTnTHR WO 0x000 Transmit Holding Register. The next character to beNAtransmitted.UARTnSTATE R/W 0x004 State of current RBR and THR buffer. 0x00UARTnCTRL R/W 0x008 Control UART interrupt enable and disable. 0x00UARTnINTSTATUS R/W 0x00C UART RX/TX interrupt status. 0x0UARTnBAUDDIV R/W 0x010 UART Baud rate divider. 0x1010.3.1 UART Receiver Buffer RegisterThe UARTnRBR is the UART Read buffer, which contains the last character received and can be read via the bus interface.When buffer is filled192 www.xinnovatech.com

XN12L612Table 10-3: UART Receiver Buffer Register (UARTnRBR – n=0,1, 2, 3) bit descriptionBit Symbol Description Reset value7:0 RBR The UART Receiver Buffer Register contains the received byte in the UART RX. NA31:8 - Reserved -10.3.2 UART Transmitter Holding RegisterThe UARTnTHR is the Write buffer, and is always Write Only.Table 10-4: UART Transmitter Holding Register (UARTnTHR – n=0,1, 2, 3) bit descriptionBit Symbol Description Reset value7:0 THR Writing to the UART Transmit Holding Register causes the data to be moved to UART ShiftNAregister. Then automatically send out in TX line.31:8 - Reserved -10.3.3 UART State RegisterThe UARTnSTATE is used to provide UART transceiver buffer status.Table 10-5: UART STATE Register (UARTnSTATE– n=0,1, 2, 3) bit descriptionBit Symbol Value Description Reset value0 - - Reserved. 01 - - Reserved. 02 THROE Transmit Buffer overrun indicator. 01 Overrun error. Write 1 to clear error.3 RBROE Receiver Buffer overrun indicator. 01 Overrun error. Write 1 to clear error.4 BRADRDY Baudrate auto detection indicator. 01 Baudrate auto detection is done. Write 1 to clear.31:5 - - Reserved. NA10.3.4 UART Control RegisterThe UARTnCTRL is used to enable DMA, THR, RBR and the four UART interrupt sources.Table 10-6: UART Interrupt Enable Register (UARTnCTRL– n=0,1, 2, 3) bit descriptionBit Symbol Value Description Reset value0 THRE THR Enable. Enables to Transmit Data. 00 Disable the THR.1 Enable the THR.1 RBRE RBR Enable. Enables to Receive Data. 00 Disable the RBR.1 Enable the RBR.www.xinnovatech.com 193

XN12L6122 THRIE THR Interrupt Enable. Enables the UART THR status interrupts. The status0of this interrupt can be read.0 Disable the THR status interrupt.1 Enable the THR status interrupt.3 RBRIE RBR Interrupt Enable. Enables the UART RBR status interrupts. The0status of this interrupt can be read.0 Disable the RBR status interrupt.1 Enable the RBR status interrupt.4 THROIE THR Overrun Interrupt Enable. Enables the UART THR Overrun Error0interrupt. The status of this interrupt can be read.0 Disable the THR Overrun Error interrupt.1 Enable the THR Overrun Error interrupt.5 RBROIE RBR Overrun Interrupt Enable. Enables the UART RBR Overrun Error0interrupts. The status of this interrupt can be read.0 Disable the RBR Overrun Error interrupt.1 Enable the RBR Overrun Error interrupt.6 THRHS THR High Speed Mode Enable. 00 Disable the High Speed Mode.1 Enable the High Speed Mode.7 IRDAEN IrDA Mode Select. 00 IrDA not used.1 IrDA mode enabled.8 DMATXEN TX DMA enable bit 00 Disable.1 Enable9 DMARXEN RX DMA enable bit 00 Disable.1 Enable14:10 - - Reserved NA15 BRADEN Baudrate auto detect enable bit 00 Disable.1 Enable31:10 - - Reserved NA10.3.5 UART Interrupt Status RegisterThe UARTnINTSTATUS provides a status code that denotes the priority and source of a pending interrupt. The interruptsare frozen during an IIR access. If an interrupt occurs during an IIR access, the interrupt is recorded for the next IIR access.Table 10-7: UART Interrupt Status Register (UARTnINTSTATUS – n=0,1, 2, 3) bit descriptionBit Symbol Value Description Reset value194 www.xinnovatech.com

XN12L6120 THRIES Interrupt status. The interrupt occurs when data transmit completed. 00 No interrupt is pending.1 The interrupt is pending. Write 1 to clear interrupt.1 RBRIES Interrupt status. The interrupt occurs when received data. 00 No interrupt is pending.1 The interrupt is pending. Write 1 to clear interrupt.2 THROIES Interrupt status. The interrupt occurs when THR buffer overrun. 00 No interrupt is pending.1 The interrupt is pending. Write 1 to clear interrupt.3 RBROIES Interrupt status. The interrupt occurs when RBR buffer overrun. 00 No interrupt is pending.1 The interrupt is pending. Write 1 to clear interrupt.31:4 - - Reserved. NAThe buffer overrun status in the STATE field is used to drive the overrun interrupt signals. Therefore, clearing the bufferoverrun status de-asserts the overrun interrupt, and clearing the overrun interrupt bit also clears the buffer overrun status bitin the STATE field.10.3.6 UART Baudrate Divider RegisterThe UART Baudrate Divider Register (UARTnBAUDDIV) controls the clock pre-scalar for the baud rate generation and canbe read and written at the user’s discretion. This pre-scalar takes the APB clock and generates an output clock according tothe specified fractional requirements.Table 10-8: UART UARTnBAUDDIV Register (UARTnBAUDDIV – n=0,1, 2, 3) bit descriptionBit Symbol Description Reset value19:0 BAUDDIV Baud-rate generation pre-scalar divisor value. The minimum number is 16. 0x1031:20 - Reserved. 0The UART baudrate can be calculated as (n=0,1):UARTnbaudrate=UARTn_PCLK / BAUDDIVWhere UARTn_PCLK is the peripheral clock, and BAUDDIV must be more than 16.10.4 Operation Description10.4.1 UART Communication ConventionData FormatTo simplify the user’s configuration to UART control register operation, both UART0 and UART1 applies fixed data format fordata communication: 1 start bit, 8 data bits, 1 stop bits, no parity and hardware flow control.Baudratewww.xinnovatech.com 195

XN12L612The user can set BAUDDIV value of UARTnBAUDDIV register to generate different baud rate for application requirement.Instead of set BAUDDIV to generate UART baud rate, UART also support baudrate auto detection to received data. To usethis feature, the user have to reset and set BRADEN bit in UARTnCTRL register to initial UART baudrate auto detectionstate machine, then wait for 0x80 from host. If 0x80 is received, UART will set baudrate automatically. This baudrate will beused for communication until the user initial another communication session.10.4.2 IrDA FunctionIRDAEN of UART Control register is used to enable/disable IrDA mode on UARTn. When IrDA mode is enabled, theRXDn/TXDn pins will be able to receive/send data with fixed pulse width of 3/16 UART baud rate. The pulse width is at least1.63us to meet IrDA standard. The following diagram shows the conversion between UART data and IrDA signal.TXStart Bit0Bit PeriodStop Bit1 0 1 0 01 1 0 1IrDA OUTIrDA IN3/16RX010 1 0 0 1 1 0 1Figure 10-3: UART and IrDA signal comparison196 www.xinnovatech.com

XN12L61211 SPI11.1 General DescriptionXN12L612 provides an extended SPI(Serial Peripheral Interface) interface which is compliant to standard SPI and 4-wireSynchronous Serial Interface (SSI) bus. It can interact with multiple masters and slaves on the bus. Only a single master anda single slave can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, withframes of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master. The SPI_PCLK areprovided by system clock, which is controlled by the SYSAHBCLKDIV. The following are major features:• Compatible with standard SPI and 4-wire TI SSI• Synchronous Serial Communication• Master or slave operation• Eight-frame FIFOs for both transmit and receive• 4-bit to 16-bit frame11.2 Pin DescriptionTable 11-1: SPI pin descriptionPinNameTypeInterface pin name/functionSPISSIPin DescriptionSCK I/O SCK CLK Serial Clock. SCK/CLK is a clock signal used to synchronize the transfer of data. It isdriven by the master and received by the slave. When SPI interface is used, theclock is programmable to be active-high or active-low, otherwise it is alwaysactive-high. SCK only switches during a data transfer. Any other time, the SPIinterface either holds it in its inactive state or does not drive it (leaves it inhigh-impedance state).SSEL I/O SSEL FS Frame Sync/Slave Select. When the SPI interface is a bus master, it drives thissignal to an active state before the start of serial data and then releases it to aninactive state after the data has been sent. The active state of this signal can be highor low depending upon the selected bus and mode. When the SPI interface is a busslave, this signal qualifies the presence of data from the Master according to theprotocol in use. When there is just one bus master and one bus slave, the FrameSync or Slave Select signal from the Master can be connected directly to the slave’scorresponding input. When there is more than one slave on the bus, furtherqualification of their Frame Select/Slave Select inputs will typically be necessary toprevent more than one slave from responding to a transfer.www.xinnovatech.com 197

XN12L612MISO I/O MISO DR(M)DX(S)Master In Slave Out. The MISO signal transfers serial data from the slave to themaster. When the SPI is a slave, serial data is output on this signal. When the SPI isa master, it clocks in serial data from this signal. When the SPI is a slave and is notselected by FS/SSEL, it does not drive this signal (leaves it in high-impedance state).MOSI I/O MOSI DX(M)DR(S)Master Out Slave In. The MOSI signal transfers serial data from the master to theslave. When the SPI is a master, it outputs serial data on this signal. When the SPI isa slave, it clocks in serial data from this signal.11.3 Register DescriptionTable 11-2: Register overview: SPI (base address 0x4004 0000)Symbol Access Address offset Description Reset valueCR0 R/W 0x000Control Register 0. Selects the serial clock rate, bus type, and datasize.0x0CR1 R/W 0x004 Control Register 1. Selects master/slave and other modes. 0x0DR R/W 0x008 Data Register. Writes fill the transmit FIFO, and reads empty the0x0receive FIFO.SR RO 0x00C Status Register 0x0000 0003CPSR R/W 0x010 SPI Clock Prescale Register 0x0IMSC R/W 0x014 Interrupt Mask Set and Clear Register 0x0RIS RO 0x018 Raw Interrupt Status Register -MIS RO 0x01C Masked Interrupt Status Register 0x0000 0008ICR WO 0x020 SPIICR Interrupt Clear Register NADMACR R/W 0x024 DMA Control Register 0x011.3.1 SPI Control Register 0This register controls the basic operation of the SPI controller.Table 11-3: SPI Control Register 0 (CR0 - address 0x4004 0000) bit descriptionBit Symbol Value Description Reset value3:0 DSS Data Size Select. This field controls the number of bits transferred in each0000frame. Values 0000-0010 are not supported and should not be used.0x30x40x50x60x70x80x90xA4-bit transfer5-bit transfer6-bit transfer7-bit transfer8-bit transfer9-bit transfer10-bit transfer11-bit transfer198 www.xinnovatech.com

XN12L6120xB0xC0xD0xE0xF12-bit transfer13-bit transfer14-bit transfer15-bit transfer16-bit transfer5:4 FRF Frame Format 000x00x10x20x3SPISSIThis combination is not supported and should not be used.This combination is not supported and should not be used.6 CPOL Clock Out Polarity. This bit is only used in SPI mode. 00 SPI controller maintains the bus clock low between frames.1 SPI controller maintains the bus clock high between frames.7 CPHA Clock Out Phase. This bit is only used in SPI mode. 00 SPI controller captures serial data on the first clock transition of the frame, thatis, the transition away from the inter-frame state of the clock line.1 SPI controller captures serial data on the second clock transition of the frame,that is, the transition back to the inter-frame state of the clock line.31:8 - Reserved.11.3.2 SPI Control Register 1This register controls certain aspects of the operation of the SPI controller.Table 11-4: SPI Control Register 1 (CR1 - address 0x4004 0004) bit descriptionBit Symbol Value Description Reset value0 LBM Loop Back Mode. 00 During normal operation.1 Serial input is taken from the serial output (MOSI or MISO) rather than theserial input pin (MISO or MOSI respectively).1 SSE SPI Enable. 00 The SPI controller is disabled.1 The SPI controller will interact with other devices on the serial bus. Softwareshould write the appropriate control information to the other SPI registersand interrupt controller registers, before setting this bit.2 MS Master/Slave Mode. This bit can only be written when the SSE bit is 0. 00 The SPI controller acts as a master on the bus, driving the SCLK, MOSI, andSSEL lines and receiving the MISO line.1 The SPI controller acts as a slave on the bus, driving MISO line andreceiving SCLK, MOSI, and SSEL lines.3 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is01, this blocks this SPI controller from driving the transmit data line (MISO).www.xinnovatech.com 199

XN12L6124 CSFL SSEL control 00 SSEL is forced to high between two frame1 SSEL is keep low when SSE=15 RSFR Clear receive FIFO 00 Stop to clear FIFO1 Clear receive FIFO6 FILTEN Enable SPI data line filter 00 SPI data line filter disable1 SPI data line filter enable31:7 Reserved NA11.3.3 SPI Data RegisterSoftware can write data to be transmitted to this register, and read data that has been received.Table 11-5: SPI Data Register (DR - address 0x4004 0008) bit descriptionBit Symbol Description Reset value15:0 DATA Write: software can write data to be sent in a future frame to this register whenever the TNF0x0000bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO waspreviously empty and the SPI controller is not busy on the bus, transmission of the data willbegin immediately. Otherwise the data written to this register will be sent as soon as allprevious data has been sent (and received). If the data length is less than 16 bit, softwaremust right-justify the data written to this register.Read: software can read data from this register whenever the RNE bit in the Status register is1, indicating that the Rx FIFO is not empty. When software reads this register, the SPIcontroller returns data from the least recent frame in the Rx FIFO. If the data length is lessthan 16 bit, the data is right-justified in this field with higher order bits filled with 0s.31:16 - Reserved -11.3.4 SPI Status RegisterThis read-only register reflects the current status of the SPI controller.Table 11-6: SPI Status Register (SR - address 0x4004 000C) bit descriptionBit Symbol Description Reset value0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 11 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 12 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. 03 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. 04 BSY Busy. This bit is 0 if the SPI controller is idle, or 1 if it is currently sending/receiving a frame0and/or the Tx FIFO is not empty.31:5 - Reserved NA200 www.xinnovatech.com

XN12L61211.3.5 SPI Clock Prescale RegisterThis register controls the factor by which the Prescaler divides the SPI peripheral clock SPI_PCLK to yield the prescalerclock that is, in turn, divided by the SCR factor in CR0, to determine the bit clock.Table 11-7: SPI Clock Prescale Register (CPSR - address 0x4004 0010) bit descriptionBit Symbol Description Reset value7:0 CPSDVSR This odd value between 1 and 255, by which SPI_PCLK is divided to yield the prescaler0output clock. Bit 0 always reads as 0.If FILTEN bit is set 1 in CR1 regisger(enable data line filter), the CPSDVSR value mustlarger than 7 in master mode.31:8 ReservedNote: the CPSR value must be properly initialized or the SPI controller will not be able to transmit data correctly.• In Slave mode, the SPI clock rate provided by the master must not exceed 1/12 of the SPI peripheral clock selected.The content of the CPSR register is not relevant.• In master mode, CPSDVSRmin = 7 or larger (odd numbers only) if data line filter is enable.11.3.6 SPI Interrupt Mask Set/Clear RegisterThis register controls whether each of the four possible interrupt conditions in the SPI controller are enabled. Note that ARMuses the word “masked” in the opposite sense from classic computer terminology, in which “masked” meant “disabled”. ARMuses the word “masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.Table 11-8: SPI Interrupt Mask Set/Clear Register (IMSC - address 0x4004 0014) bit descriptionBit Symbol Description Reset value0 RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is,0when the Rx FIFO is full and another frame is completely received. The ARM spec impliesthat the preceding frame data is overwritten by the new frame data when this occurs.1 RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs.0A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a“time-out period”. The time-out period is the same for master and slave modes and isdetermined by the SPI bit rate: 32 bits at PCLK / (CPSDVSR [SCR+1]).2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. 03 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. 031:4 - Reserved NA11.3.7 SPI Raw Interrupt Status RegisterThis read-only register contains a 1 for each interrupt condition that is asserted, regardless of whether or not the interrupt isenabled in the IMSC.Table 11-9: SPI Raw Interrupt Status Register (RIS - address 0x4004 0018) bit descriptionBit Symbol Description Reset valuewww.xinnovatech.com 201

XN12L6120 RORRIS This bit is 1 if another frame was completely received while the Rx FIFO was full. The0ARM spec implies that the preceding frame data is overwritten by the new frame datawhen this occurs.1 RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a “time-out period”. The0time-out period is the same for master and slave modes and is determined by the SPI bitrate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).2 RXRIS This bit is 1 if the Rx FIFO is at least half full. 03 TXRIS This bit is 1 if the Tx FIFO is at least half empty. 131:4 - Reserved NA11.3.8 SPI Masked Interrupt Status RegisterThis read-only register contains a 1 for each interrupt condition that is asserted and enabled in the IMSC. When an SPIinterrupt occurs, the interrupt service routine should read this register to determine the cause(s) of the interrupt.Table 11-10: SPI Masked Interrupt Status Register (MIS -address 0x4004 001C) bit descriptionBit Symbol Description Reset value0 RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this0interrupt is enabled.1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a “time-out period”, and this0interrupt is enabled. The time-out period is the same for master and slave modes and isdetermined by the SPI bit rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).2 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. 03 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. 031:4 - Reserved NA11.3.9 SPI Interrupt Clear RegisterSoftware can write one or more one(s) to this write-only register, to clear the corresponding interrupt condition(s) in the SPIcontroller. Note that the other two interrupt conditions can be cleared by writing or reading the appropriate FIFO, or disabledby clearing the corresponding bit in IMSC.Table 11-11: SPI interrupt Clear Register (ICR - address 0x4004 0020) bit descriptionBit Symbol Description Reset value0 RORIC Writing a 1 to this bit clears the “frame was received when Rx FIFO was full” interrupt. NA1 RTIC Writing a 1 to this bit clears the “Rx FIFO was not empty and has not been read for a time-outNAperiod” interrupt. The time-out period is the same for master and slave modes and isdetermined by the SPI bit rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).31:2 - Reserved NA11.3.10 SPI DMA Control RegisterThe DMACR register is the DMA control register. It is a read/write register.202 www.xinnovatech.com

XN12L612Table 11-12: SPI DMA Control Register (DMACR - address 0x4004 0024) bit descriptionBit Symbol Value Description Reset value0 RXDMAE Receive DMA Enable 00 Receive DMA disabled.1 DMA for the receive FIFO is enabled.1 TXDMAE Transmit DMA Enable 00 Transmit DMA disabled.1 DMA for the transmit FIFO is enabled.31:2 Reserved NA11.4 Operation11.4.1 SPI Frame FormatThe SPI interface is a four-wire interface where the SSEL signal behaves as a slave select. The main feature of the SPIformat is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits within theSPICR0 control register.Clock Polarity (CPOL) and Phase (CPHA) controlWhen the CPOL clock polarity control bit is LOW, it produces a steady state low value on the SCK pin. If the CPOL clockpolarity control bit is HIGH, a steady state high value is placed on the CLK pin when data is not being transferred. The CPHAcontrol bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bittransmitted by either allowing or not allowing a clock transition before the first data capture edge. When the CPHA phasecontrol bit is LOW, data is captured on the first clock edge transition. If the CPHA clock phase control bit is HIGH, data iscaptured on the second clock edge transition.SPI format with CPOL=0, CPHA=0Single and continuous transmission signal sequences for SPI format with CPOL = 0, CPHA = 0 are shown in the followingfigure.www.xinnovatech.com 203

XN12L612CLKSSELMOSIMSBLSBMISOMSBLSBQ4 to 16 bita. Single transfer with CPOL = 0 and CPHA = 0MSBLSBMSBLSBMSBLSBQMSBLSBQ4 to 16 bit4 to16 bitFigure 11-1: SPI frame format with CPOL = 0 and CPHA = 0 (a) Single and b) Continuous Transfer)In this configuration, during idle periods:• The CLK signal is forced LOW.• SSEL is forced HIGH.• The transmit MOSI/MISO pad is in high impedance.If the SPI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL mastersignal being driven LOW. This causes slave data to be enabled onto the MISO input line of the master. Master’s MOSI isenabled. One half SCK period later, valid master data is transferred to the MOSI pin. Now that both the master and slavedata have been set, the SCK master clock pin goes HIGH after one further half SCK period. The data is now captured on therising and propagated on the falling edges of the SCK signal. In the case of a single word transmission, after all bits of thedata word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has beencaptured if CSFL is 0, or SSEL line is still in LOW state if CSFL is 1.SPI format with CPOL=0, CPHA=1The transfer signal sequence for SPI format with CPOL = 0, CPHA = 1 is shown in the following figure, which covers bothsingle and continuous transfers.204 www.xinnovatech.com

XN12L612CLKSSELMOSIMSBLSBMISOQMSBLSBQ4 to 16 bitFigure 11-2: SPI frame format with CPOL = 0 and CPHA = 1In this configuration, during idle periods:• The CLK signal is forced LOW.• SSEL is forced HIGH.• The transmit MOSI/MISO pad is in high impedance.If the SPI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL mastersignal being driven LOW. Master’s MOSI pin is enabled. After a further one half SCK period, both master and slave validdata is enabled onto their respective transmission lines. At the same time, the SCK is enabled with a rising edge transition.Data is then captured on the falling edges and propagated on the rising edges of the SCK signal. In the case of a single wordtransfer, after all bits have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bithas been captured. For continuous back-to-back transfers, the SSEL pin is held LOW between successive data words ifCSFL is 1, or SSEL pin is forced to HIGH is CSFL is 0.SPI format with CPOL = 1, CPHA = 0Single and continuous transmission signal sequences for SPI format with CPOL=1, CPHA=0 are shown in the followingfigure.www.xinnovatech.com 205

XN12L612CLKSSELMOSIMSBLSBMISOMSBLSBQ4 to 16 bita. Single transfer with CPOL = 1 and CPHA = 0MSBLSBMSBLSBMSB LSB QMSB LSB Q4 to 16 bit4 to 16 bitb. Continuous transfer with CPOL = 1 and CPHA = 0Figure 11-3: SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and (b) Continuous TransferIn this configuration, during idle periods:• The CLK signal is forced HIGH.• SSEL is forced HIGH.• The transmit MOSI/MISO pad is in high impedance.If the SPI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL mastersignal being driven LOW, which causes slave data to be immediately transferred onto the MISO line of the master. Master’sMOSI pin is enabled. One half period later, valid master data is transferred to the MOSI line. Now that both the master andslave data have been set, the SCK master clock pin becomes LOW after one further half SCK period. This means that datais captured on the falling edges and be propagated on the rising edges of the SCK signal. In the case of a single wordtransmission, after all bits of the data word are transferred, the SSEL line is returned to its idle HIGH state one SCK periodafter the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSEL signal can bepulsed HIGH between each data word transfer if CSFL is 0. It also can be kept low if CSFL is 1.SPI format with CPOL = 1, CPHA = 1The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in the following figure, which covers bothsingle and continuous transfers.206 www.xinnovatech.com

XN12L612CLKSSELMOSIMSBLSBMISOQMSBLSBQ4 to 16 bitFigure 11-4: SPI frame format with CPOL = 1 and CPHA = 1In this configuration, during idle periods:• The CLK signal is forced HIGH.• SSEL is forced HIGH.• The transmit MOSI/MISO pad is in high impedance.If the SPI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSEL mastersignal being driven LOW. Master’s MOSI is enabled. After a further one half SCK period, both master and slave data areenabled onto their respective transmission lines. At the same time, the SCK is enabled with a falling edge transition. Data isthen captured on the rising edges and propagated on the falling edges of the SCK signal. After all bits have been transferred,in the case of a single word transmission, the SSEL line is returned to its idle HIGH state one SCK period after the last bithas been captured. For continuous back-to-back transmissions, the SSEL pins remains in its active LOW state if CSFL is 0,or will be driven to HIGH if CSFL is 0.11.4.2 SSI Frame FormatThe following figure shows the 4-wire SSI frame format supported by the SPI module.www.xinnovatech.com 207

XN12L612CLKFSDX/DRMSBLSB4 to 16 bita. Single frame transferCLKFSDX/DRMSB LSB MSB LSB4 to 16 bit4 to 16 bitb. Continuous/back-to-back frames transferFigure 11-5: SSI Frame Format: a) Single and b) Continuous/back-to-back Two Frames Transfer)For device configured as a master in this mode, CLK and FS are forced LOW, and the transmit data line DX is in 3-statemode whenever the SPI is idle. Once the bottom entry of the transmit FIFO contains data, FS is pulsed HIGH for one CLKperiod. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic.On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is shifted out on the DX pin. Likewise, the MSB ofthe received data is shifted onto the DR pin by the off-chip serial slave device. Both the SPI and the off-chip serial slavedevice then clock each data bit into their serial shifter on the falling edge of each CLK. The received data is transferred fromthe serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.208 www.xinnovatech.com

XN12L61212 TWS12.1 General DescriptionTWS is a kind of two wires serial communication interface, which is compatible to I 2 C-bus. It is able to support I 2 C bothmaster and slave mode. The major features as the following:• Standard I 2 C-compliant bus interfaces may be configured as Master, Slave.• Programmable clock allows adjustment of TWS transfer rates.• Data transfer is bidirectional between masters and slaves.• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus.• Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer.• Supports Fast-mode Plus, up to 3MHz.• Optional recognition of up to four distinct slave addresses.• TWS-bus can be used for test and diagnostic purposes.• The TWS block contains a standard I 2 C compliant bus interface with two pins.pull-upresistorpull-upresistorSDACompatible I 2 C busSCLSDA SCLXN12L612OTHERXN12L612OTHER I 2 CCompatibleDEVICEFigure 12-1: TWS application bus configuration12.2 Pin DescriptionTable 12-1: TWS-bus pin descriptionPin Type DescriptionSDA Input/Output TWS Serial DataSCL Input/Output TWS Serial Clockwww.xinnovatech.com 209

XN12L61212.3 Register DescriptionTable 12-2: Register overview: TWS (base address 0x4000 0000)Symbol Access AddressoffsetDescriptionResetvalueCONSET R/W 0x000 TWS Control Set Register. When a one is written to a bit of this register, the0x00STAT RO 0x004DAT R/W 0x008corresponding bit in the TWS control register is set. Writing a zero has no effect onthe corresponding bit in the TWS control register.TWS Status Register. During TWS operation, this register provides detailed statuscodes that allow software to determine the next action needed.TWS Data Register. During master or slave transmit mode, data to be transmitted iswritten to this register. During master or slave receive mode, data that has beenreceived may be read from this register.0xF80x00ADR0 R/W 0x00C TWS Slave Address Register 0. Contains the 7-bit slave address for operation of the0x00TWS interface in slave mode, and is not used in master mode. The least significantbit determines whether a slave responds to the General Call address.SCLH R/W 0x010 Duty Cycle Register High Half Word. Determines the high time of the TWS clock. 0x04SCLL R/W 0x014 Duty Cycle Register Low Half Word. Determines the low time of the TWS clock. 0x04CONCLR WO 0x018 TWS Control Clear Register. When a one is written to a bit of this register, theNAcorresponding bit in the TWS control register is cleared. Writing a zero has no effecton the corresponding bit in the TWS control register.- - 0x01C Reserved 0x00ADR1 R/W 0x020 TWS Slave Address Register 1. Contains the 7-bit slave address for operation of the0x00TWS interface in slave mode, and is not used in master mode. The least significantbit determines whether a slave responds to the General Call address.ADR2 R/W 0x024 TWS Slave Address Register 2. Contains the 7-bit slave address for operation of the0x00TWS interface in slave mode, and is not used in master mode. The least significantbit determines whether a slave responds to the General Call address.ADR3 R/W 0x028 TWS Slave Address Register 3. Contains the 7-bit slave address for operation of the0x00DATA_BUFFERTWS interface in slave mode, and is not used in master mode. The least significantbit determines whether a slave responds to the General Call address.RO 0x02C Data buffer register. The contents of the 8 MSBs of the TWSDAT shift register will betransferred to the DATA_BUFFER automatically after every nine bits (8 bits of dataplus ACK or NACK) has been received on the bus.0x00MASK0 R/W 0x030 TWS Slave address mask register 0. This mask register is associated with ADR0 to0x00determine an address match. The mask register has no effect when comparing to theGeneral Call address (‘0000000’).MASK1 R/W 0x034 TWS Slave address mask register 1. This mask register is associated with ADR0 to0x00determine an address match. The mask register has no effect when comparing to theGeneral Call address (‘0000000’).210 www.xinnovatech.com

XN12L612MASK2 R/W 0x038 TWS Slave address mask register 2. This mask register is associated with ADR0 to0x00determine an address match. The mask register has no effect when comparing to theGeneral Call address (‘0000000’).MASK3 R/W 0x03C TWS Slave address mask register 3. This mask register is associated with ADR0 to0x00determine an address match. The mask register has no effect when comparing to theGeneral Call address (‘0000000’).12.3.1 TWS Control Set registerThe CONSET registers control setting of bits in the register that controls operation of the TWS interface. Writing a one to abit of this register causes the corresponding bit in the TWS control register to be set. Writing a zero has no effect.Table 12-3: TWS Control Set register (CONSET - address 0x4000 0000) bit descriptionBit Symbol Description Reset value0 TXRX Transmit/receive flag 01 MASL Master/slave flag 02 AA Assert acknowledge flag. 03 SI TWS interrupt flag. 04 STO STOP flag. 05 STA START flag. 06 TWSEN TWS interface enable. 031:7 - Reserved NATXRX: Transmit/receive flag• When TXRX is 1, the TWS interface is work in transmit mode.• When TXRX is 0, the TWS interface is work in receive mode.MASL: Master/slave flag• When MASL is 1, the TWS interface is work as a master.• When MASL is 0, the TWS interface is work as a slave.AA: Assert Acknowledge Flag.• When set to 1, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCLline on the following situations:1. The address in the Slave Address Register has been received.2. The General Call address has been received while the General Call bit (GC) in ADRn is set.3. A data byte has been received while the TWS is in the master receiver mode.4. A data byte has been received while the TWS is in the addressed slave receiver mode• The AA bit can be cleared by writing 1 to the AAC bit in the CONCLR register. When AA is 0, a not acknowledge(HIGH level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations:1. A data byte has been received while the TWS is in the master receiver mode.www.xinnovatech.com 211

XN12L6122. A data byte has been received while the TWS is in the addressed slave receiver mode.SI: Interrupt Flag.• This bit is set when the TWS state changes. However, entering state F8 does not set SI since there is nothing for aninterrupt service routine to do in that case. While SI is set, the low period of the serial clock on the SCL line isstretched, and the serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag. SI mustbe reset by software, by writing a 1 to the SIC bit in CONCLR register.STO: STOP flag.• Setting this bit causes the TWS interface to transmit a STOP condition in master mode, or recover from an errorcondition in slave mode. When STO is 1 in master mode, a STOP condition is transmitted on the TWS-bus. When thebus detects the STOP condition, STO is cleared automatically. In slave mode, setting this bit can recover from anerror condition. In this case, no STOP condition is transmitted to the bus. The hardware behaves as if a STOPcondition has been received and it switches to “not addressed” slave receiver mode. The STO flag is cleared byhardware automatically.STA: START flag.• Setting this bit causes the TWS interface to enter master mode and transmit a START condition or transmit aRepeated START condition if it is already in master mode. When STA is 1 and the TWS interface is not already inmaster mode, it enters master mode, checks the bus and generates a START condition if the bus is free. If the bus isnot free, it waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a halfclock period of the internal clock generator. If the TWS interface is already in master mode and data has beentransmitted or received, it transmits a Repeated START condition. STA may be set at any time, including when theTWS interface is in an addressed slave mode. STA can be cleared by writing 1 to the STAC bit in the CONCLRregister. When STA is 0, no START condition or Repeated START condition will be generated. If STA and STO areboth set, then a STOP condition is transmitted on the bus if it the interface is in master mode, and transmits a STARTcondition thereafter. If the TWS interface is in slave mode, an internal STOP condition is generated, but is nottransmitted on the bus.TWSEN: TWS Interface Enable.• When TWSEN is 1, the TWS interface is enabled. TWSEN can be cleared by writing 1 to the TWSENC bit in theTWSONCLR register. When TWSEN is 0, the TWS interface is disabled.• When TWSEN is “0”, the SDA and SCL input signals are ignored, the TWS block is in the “not addressed” slave state,and the STO bit is forced to “0”. TWSEN should not be used to temporarily release the TWS-bus since, when TWSENis reset; the TWS-bus status is lost. The AA flag should be used instead..12.3.2 TWS Status RegisterEach TWS Status register reflects the condition of the corresponding TWS interface. The TWS Status register is Read-Only.Table 12-4: TWS Status Register (STAT - 0x4000 0004) bit descriptionBit Symbol Description Reset value6:0 STATUS These bits give the actual status information about the TWS interface. For a0x1Fcomplete list of status codes, refer to tables from Table 12-12~Table 12-15.212 www.xinnovatech.com

XN12L6128 SLVADDMATCH Slave address matched. Write 1 to clear this bit. 09 SLVRXBUFFULL Slave receiver buffer is full. Read Data Register (offset: 0x08) to clear this bit. 010 SLVTXBUFEMPTY Slave transmitter buffer is empty. Write Data Register (offset: 0x08) to clear this0bit.31: 11 - Reserved NA12.3.3 TWS Data RegisterThis register contains the data to be transmitted or the data just received. The CPU can read and write to this register onlywhile it is not in the process of shifting a byte, when the SI bit is set. Data in DAT remains stable as long as the SI bit is set.Data in DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a byte has beenreceived, the first bit of received data is located at the MSB of TWSDAT.Table 12-5: TWS Data Register (DAT - 0x4000 0008) bit descriptionBit Symbol Description Reset value7:0 Data This register holds data values that have been received or are to be transmitted. 031: 8 - Reserved NA12.3.4 TWS Slave Address Register 0This register is readable and writable and is only used when a TWS interface is set to slave mode. In master mode, thisregister has no effect. The LSB of ADRn is the General Call bit. When this bit is set, the General Call address (0x00) isrecognized. Any of these registers which contain the bit 0 will be disabled and will not match any address on the bus. Thisregister will be cleared to this disabled state on reset.Table 12-6: TWS Slave Address Register 0 (ADR0- 0x4000 000C) bit descriptionBit Symbol Description Reset value0 GC General Call enable bit. 07:1 Address The TWS device address for slave mode. 0x0031: 8 - Reserved NA12.3.5 TWS HIGH Duty Cycle registerTable 12-7: TWS High Duty Cycle register (SCLH - address 0x4000 0010) bit descriptionBit Symbol Description Reset value15:0 SCLH Count for TWS high time period selection. 0x000431: 16 - Reserved -12.3.6 TWS Low Duty Cycle registerTable 12-8: TWS Low Duty Cycle register (SCLL - address 0x4000 0014) bit descriptionBit Symbol Description Reset value15:0 SCLL Count for TWS low time period selection. 0x000431: 16 - Reserved -www.xinnovatech.com 213

XN12L612Note:Software must set values for the registers SCLH and SCLL to select the appropriate data rate and duty cycle. SCLH defines the numberof TWS PCLK cycles for the TWS high time, SCLL defines the number of TWS PCLK cycles for the TWS low time. The frequency isdetermined by the following formula (TWS PCLK is the frequency of the peripheral bus APB):TWS bitfrequency = TWS_PCLK/(SCLH + SCLL)12.3.7 TWS Control Clear RegisterThe CONCLR registers control clearing of bits in the CONSET register that controls operation of the TWS interface. Writing aone to a bit of this register causes the corresponding bit in the TWS control register to be cleared. Writing a zero has noeffect.Table 12-7: TWS Control Clear Register (CONCLR - 0x4000 0018) bit descriptionBit Symbol Description Reset value0 TXRX TX/RX select Clear bit. Writing a 1 to this bit clears the TXRX bit in the TWSONSET register.NAWriting 0 has no effect.1 MASL Master/slave select Clear bit. Writing a 1 to this bit clears the TXRX bit in the TWSONSETregister. Writing 0 has no effect.2 AAC Assert acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the TWSONSETregister. Writing 0 has no effect.3 SIC Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the TWSONSET register. Writing 00has no effect.4 - Reserved. NA5 STAC START flag Clear bit. Writing a 1 to this bit clears the STA bit in the TWSONSET register.0Writing 0 has no effect.6 TWSENC TWS interface Disable bit. Writing a 1 to this bit clears the TWSEN bit in the TWSONSET0register. Writing 0 has no effect.31: 7 - Reserved NA12.3.8 TWS Slave Address RegistersThese registers are readable and writable and are only used when a TWS interface is set to slave mode. In master mode,this register has no effect. The LSB of ADRn is the General Call bit. When this bit is set, the General Call address (0x00) isrecognized. Any of these registers which contain the bit 00x will be disabled and will not match any address on the bus. Allfour registers (including the ADR0 register) will be cleared to this disabled state on reset.Table 12-9: TWS Slave Address Registers (ADR1 - 0x4000 0020, ADR2 - 0x4000 0024, ADR3 -0x4000 0028) bit descriptionBit Symbol Description Reset value0 GC General Call enable bit. 07:1 Address The TWS device address for slave mode. 0x0031: 8 - Reserved NA214 www.xinnovatech.com

XN12L61212.3.9 TWS Data Buffer RegisterTable 12-8: TWS Data Buffer Register (DATA_BUFFER - 0x4000 002C) bit descriptionBit Symbol Description Reset value7:0 Data This register holds contents of the 8 MSBs of the TWSDAT shift register. 031: 8 - Reserved NA12.3.10 TWS Mask RegistersThe four mask registers each contain seven active bits (7:1). Any bit in these registers which is set to ‘1’ will cause anautomatic compare on the corresponding bit of the received address when it is compared to the ADRn register associatedwith that mask register. In other words, bits in an ADRn register which are masked are not taken into account in determiningan address match. On reset, all mask register bits are cleared to ‘0’. The mask register has no effect on comparison to theGeneral Call address (“0000000”). Bits(31:8) and bit(0) of the mask registers are unused and should not be written to.These bits will always read back as zeros. When an address-match interrupt occurs, the processor will have to read thedata register (DAT) to determine what the received address was that actually caused the match.Table 12-9: TWS Mask Registers (MASK0 - 0x4000 0030, MASK1 - 0x4000 0034,MASK2 - 0x4000 0038, MASK3 - 0x4000 003C) bitdescriptionBit Symbol Description Reset value0 - Reserved. 07:1 MASK Mask bits. 0x0031: 8 - Reserved. 012.4 TWS OperationTo compatible I 2 C in a given application, the TWS block may operate as a master or a slave. In the slave mode, the TWShardware looks for any one of its four slave addresses and the General Call address. If one of these addresses is detected,an interrupt is requested. If the processor wishes to become the bus master, the hardware waits until the bus is free beforethe master mode is entered so that a possible slave operation is not interrupted.12.4.1 Master Transmitter ModeIn this mode data is transmitted from master to slave. Before the master transmitter mode can be entered, the CONSETregister must be initialized. MASL must be set to 1 to select master mode, TXRX must be set to 1 to enable transmit, thenTWSEN should be set to 1 to enable the TWS function. The STA, STO and SI bits must be 0. The SI bit is cleared by writing1 to the SIC bit in the CONCLR register. The STA bit should be cleared after writing the slave address.Table 12-10: TWS CONSET used to configure Master modeBit 7 6 5 4 3 2 1 0Symbol - TWSEN STA STO SI AA MASL TXRXValue - 1 0 0 0 0 1 1The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this modethe data direction bit (R/W) should be 0 which means Write. The first byte transmitted contains the slave address and Writewww.xinnovatech.com 215

XN12L612bit. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOPconditions are output to indicate the beginning and the end of a serial transfer. The TWS interface will enter mastertransmitter mode when software sets the STA bit. The TWS logic will send the START condition as soon as STA bit is set.After the START condition is transmitted, the SI bit is set, and the status code in the STAT register is 0x01. This status codeis used to vector to a state service routine which will load the slave address and Write bit to the DAT register, and then clearthe SI bit. SI is cleared by writing a 1 to the SIC bit in the CONCLR register.When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is setagain, and the status codes now are 0x0b, 0x4b or 0x14for the master mode. The appropriate actions to be taken for each ofthese status codes are shown in Table 12-12 to Table 12-15.S SLAVE ADDRESS RW=0 A DATA A DATA A/A# Pn bytes data transmittedfrom Master to Slavefrom Slave to MasterA = Acknowledge (SDA low)A# = Not acknowledge (SDA high)S = START conditionP = STOP conditionFigure 12-2: Format in the Master Transmitter mode216 www.xinnovatech.com

XN12L612successfultransmissionto a SlaveReceiverSSLA W A DATA A P01H0BH14Hnext transferstarted with aRepeated StartconditionSSLAWNotAcknowledgereceived afterthe SlaveaddressA# P R01H4BHNotAcknowledgereceived after aData byteA# P54Hto Masterreceivemode,entry= MRfrom Master to Slavefrom Slave to MasterDATAAany number of data bytes and their associated Acknowledge bitsnThis number (contained in STAT) corresponds to a defined state of the TWS busFigure 12-3: Format, and states in the Master Transmitter flow chart12.4.2 Master Receiver ModeIn the master receiver mode, data is received from a slave transmitter. The transfer is initiated in the same way as in themaster transmitter mode. When the START condition has been transmitted, the interrupt service routine must load the slaveaddress and the data direction bit to the TWS Data register (DAT), and then clear the SI bit. In this case, the data direction bit(R/W) should be 1 to indicate a read. When the slave address and data direction bit have been transmitted and anacknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, thepossible status codes are 0x0b, 0x4b, or 0x1d. For details, refer to Table 12-13. When the device needs to acknowledge areceived byte, the AA bit needs to be set accordingly prior to clearing the SI bit and initiating the byte read. When the deviceneeds to not acknowledge a received byte, the AA bit needs to be cleared prior to clearing the SI bit and initiating the byteread. Note that the last received byte is always followed by a "Not Acknowledge" from the device so that the master cansignal the slave that the reading sequence is finished and that it needs to issue a STOP or repeated START Command.www.xinnovatech.com 217

XN12L612Once the "Not Acknowledge has been sent and the SI bit is set, the device can send either a STOP (STO bit is set) or arepeated START (STA bit is set). Then the SI bit is cleared to initiate the requested operation.S SLAVE ADDRESS RW=1 A DATA A DATA A# Pn bytes data receivedfrom Master to Slavefrom Slave to MasterA = Acknowledge (SDA low)A# = Not acknowledge (SDA high)S = START conditionP = STOP conditionFigure 12-4: Format of Master Receiver modeAfter a repeated START condition, TWS may switch to the master transmitter mode.R SLA R A DATA A DATA A# Sr SLA W A DATA A Pn bytes data receivedfrom Master to Slavefrom Slave to MasterA = Acknowledge (SDA low)A# = Not acknowledge (SDA high)S = START conditionP = STOP conditionSLA = Slave AddressSr = Repeated START conditionFigure 12-5: A Master Receiver switches to Master Transmitter after sending repeated START218 www.xinnovatech.com

XN12L612MRsuccessfultransmissionto a SlavetransmitterSSLA R A DATA DATA A# P01H0BH1DH1DHnext transferstarted with aRepeated StartconditionSSLARNotAcknowledgereceived afterthe SlaveaddressA# P W21H22H4BHto Mastertransmitmode,entry= MTfrom Master to Slavefrom Slave to MasterDATAAany number of data bytes and their associated Acknowledge bitsnthis number (contained in STAT) corresponds to a defined state of the TWS busFigure 12-6: Format, and states in the Master Receiver flow chart12.4.3 Slave Receiver ModeIn the slave receiver mode, data bytes are received from a master transmitter. To initialize the slave receiver mode, write anyof the Slave Address registers (ADR0-3) and Slave Mask registers (MASK0-3) and write the TWS Control Set register(CONSET).Table 12-11: TWS CONSET used to configure Slave modeBit 7 6 5 4 3 2 1 0Symbol -I 2EN STA STO SI AA MASL TXRXValue - 1 0 0 0 1 0 0MASL must be clear and TWSEN must be set to 1 to enable the TWS function. AA bit must be set to 1 to acknowledge anyof its own slave addresses or the General Call address. The STA, STO and SI bits are set to 0. After ADR and CONSET areinitialized, the TWS interface waits until it is addressed by its any of its own slave addresses or General Call addressfollowed by the data direction bit. If the direction bit is 0 (W), it enters slave receiver mode. If the direction bit is 1 (R), it enterswww.xinnovatech.com 219

XN12L612slave transmitter mode. After the address and direction bit have been received, the SI bit is set and a valid status code canbe read from the Status register (STAT). Refer to Table 12-14 for the status codes and actions.S SLAVE ADDRESS RW=0 A DATA A DATA A/A# P/Srn bytes data receivedfrom Master to Slavefrom Slave to MasterA = Acknowledge (SDA low)A# = Not acknowledge (SDA high)S = START conditionP = STOP conditionSr = Repeated START conditionFigure 12-7: Format of Slave Receiver modereception of theown Slaveaddress and oneor more Databytes all areacknowledgedSSLAW A DATA A DATAAP PORSS01H0AH13H13H1DHLast data bytereceived is NotacknowledgedA# A P PORSS13Hreception of theGeneral Calladdress and oneor more DatabytesGENERAL CALL W A DATA A DATAAP PORSS0AH 13H 13H 1DHlast data byte isNot acknowledgedA# A P PORSS13Hfrom Master to Slavefrom Slave to MasterDATAAany number of data bytes and their associated Acknowledge bitsnthis number (contained in STAT) corresponds to a defined state of the TWS busFigure 12-8: Format, and states in the Slave Receiver flow chart220 www.xinnovatech.com

XN12L61212.4.4 Slave Transmitter ModeThe first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will be 1,indicating a read operation. Serial data is transmitted via SDA while the serial clock is input through SCL. START and STOPconditions are recognized as the beginning and end of a serial transfer. In a given application, TWS may operate as a masterand as a slave. In the slave mode, the TWS hardware looks for any of its own slave addresses and the General Call address.If one of these addresses is detected, an interrupt is requested.S SLAVE ADDRESS RW=1 A DATA A DATA A# Pn bytes data receivedfrom Master to Slavefrom Slave to MasterA = Acknowledge (SDA low)A# = Not acknowledge (SDA high)S = START conditionP = STOP conditionFigure 12-9: Format of Slave Transmitter modereception of theown Slaveaddress and oneor more Databytes all areacknowledgedSSLAR A DATA A DATA A# A P PORSS4AH5CH1CHfrom Master to Slavefrom Slave to MasterDATAAany number of data bytes and their associated Acknowledge bitsnthis number (contained in STAT) corresponds to a defined state of the TWS busFigure 12-10: Format, and states in the Transmitter flow chartwww.xinnovatech.com 221

XN12L61212.4.5 Detailed State TablesThe following tables show detailed state information for the four TWS operating modes.Table 12-12: Master Transmitter modeSTATStatus of the TWS busApplication software responseNext action taken by TWS hardwareStatusand hardwareTo/From DATTo CONCodeSTA TXRX STO SI AA0x01A START conditionLoad SLA+W;X 1 0 0 X SLA+W will be transmitted; ACK bit will behas been transmitted.clear STAreceived.0x01A repeated STARTLoad SLA+W or X 1 0 0 X As above.condition has beentransmitted.Load SLA+R;Clear STAX 1 0 0 X SLA+W will be transmitted; the TWS block will beswitched to MST/REC mode.0x0b0x4b0x140x54SLA+W has beentransmitted; ACK hasbeen received.SLA+W has beentransmitted; NOT ACKhas been received.Data byte in DAT hasbeen transmitted; ACKhas been received.Data byte in DAT hasbeen transmitted;NOT ACK has beenreceived.Load data byte 0 1 0 0 X Data byte will be transmitted; ACK bit will bereceived.No DAT action 1 1 0 0 X Repeated START will be transmitted.No DAT action 0 1 1 0 X STOP condition will be transmitted; STO flag willbe reset.No DAT action 1 1 1 0 X STOP condition followed by a START conditionwill be transmitted; STO flag will be reset.Load data byte 0 1 0 0 X Data byte will be transmitted; ACK bit will bereceived.No DAT action 1 1 0 0 X Repeated START will be transmitted.No DAT action 0 1 1 0 X STOP condition will be transmitted; STO flag willbe reset.No DAT action 1 1 1 0 X STOP condition followed by a START conditionwill be transmitted; STO flag will be reset.Load data byte 0 1 0 0 X Data byte will be transmitted; ACK bit will bereceived.No DAT action 1 1 0 0 X Repeated START will be transmitted.No DAT action 0 1 1 0 X STOP condition will be transmitted; STO flag willbe reset.No DAT action 1 1 1 0 X STOP condition followed by a START conditionwill be transmitted; STO flag will be reset.Load data byte 0 1 0 0 X Data byte will be transmitted; ACK bit will bereceived.No DAT action 1 1 0 0 X Repeated START will be transmitted.No DAT action 0 1 1 0 X STOP condition will be transmitted; STO flag willbe reset.No DAT action 1 1 1 0 X STOP condition followed by a START conditionwill be transmitted; STO flag will be reset.222 www.xinnovatech.com

XN12L612Table 12-13: Master Receiver modeSTATStatus of the TWS-busApplication software responseNext action taken by TWS hardwareStatusand hardwareTo/From DATTo CONCodeSTA TXRX STO SI AA0x010x220x0b0x4b0x1d0x5dA START conditionhas been transmitted.A repeated STARTcondition has beentransmitted.SLA+R has beentransmitted; ACK hasbeen received.SLA+R has beentransmitted; NOT ACKhas been received.Data byte has beenreceived; ACK hasbeen returned.Data byte has beenreceived; NOT ACKhas been returned.Load SLA+R X 1 0 0 X SLA+R will be transmitted; ACK bit will be received.Load SLA+R X 1 0 0 X As above.Load SLA+W X 1 0 0 X SLA+W will be transmitted; the TWS block will beswitched to MST/TRX mode.No DAT action 1 1 0 0 X A START condition will be transmitted when thebus becomes free.No DAT action 0 0 0 0 0 Data byte will be received; NOT ACK bit will bereturned.No DAT action 0 0 0 0 1 Data byte will be received; ACK bit will be returned.No DAT action 1 1 0 0 X Repeated START condition will be transmitted.No DAT action 0 1 1 0 X STOP condition will be transmitted; STO flag will bereset.No DAT action 1 1 1 0 X STOP condition followed by a START condition willbe transmitted; STO flag will be reset.Read data byte 0 0 0 0 0 Data byte will be received; NOT ACK bit will bereturned.Read data byte 0 0 0 0 1 Data byte will be received; ACK bit will be returned.Read data byte 1 1 0 0 X Repeated START condition will be transmitted.Read data byte 0 X 1 0 X STOP condition will be transmitted; STO flag will bereset.Read data byte 1 X 1 0 X STOP condition followed by a START condition willbe transmitted; STO flag will be reset.Table 12-14: Slave Receiver ModeSTATStatus of the TWS-busApplication software responseNext action taken by TWS hardwareStatusand hardwareTo/From DATTo CONCodeSTA TXRX STO SI AA0x0a0x0aOwn SLA+W has beenreceived; ACK has beenreturned.General Call address(0x00) has beenNo DAT action X 0 0 0 0 Data byte will be received and NOT ACK will bereturned.No DAT action X 0 0 0 1 Data byte will be received and ACK will bereturned.No DAT action X 0 0 0 Data byte will be received and NOT ACK will bereturned.www.xinnovatech.com 223

XN12L6120x130x130x13received; ACK has beenreturned.Previously addressedwith own SLA address;DATA has beenreceived; ACK has beenreturned.Previously addressedwith own SLA; DATAbyte has been received;NOT ACK has beenreturned.Previously addressedwith General Call; DATAbyte has been received;ACK has been returned.No DAT action X 0 0 0 1 Data byte will be received and ACK will bereturned.Read data byte X 0 0 0 0 Data byte will be received and NOT ACK will bereturned.Read data byte X 0 0 0 1 Data byte will be received and ACK will bereturned.Read data byte 0 0 0 0 0 Switched to not addressed SLV mode; norecognition of own SLA or General Call address.Read data byte 0 0 0 0 1 Switched to not addressed SLV mode; Own SLAwill be recognized; General Call address will berecognized if ADR[0] = logic 1.Read data byte 1 0 0 0 0 Switched to not addressed SLV mode; norecognition of own SLA or General Call address.A START condition will be transmitted when thebus becomes free.Read data byte 1 0 0 0 1 Switched to not addressed SLV mode; Own SLAwill be recognized; General Call address will berecognized if ADR[0] = logic 1. A STARTcondition will be transmitted when the busbecomes free.Read data byte X 0 0 0 0 Data byte will be received and NOT ACK will bereturned.Read data byte X 0 0 0 1 Data byte will be received and ACK will bereturned.0x1dA STOP condition orNo STDAT0 0 0 0 0 Switched to not addressed SLV mode; norepeated STARTactionrecognition of own SLA or General Call address.condition has been1 0 0 0 0 Switched to not addressed SLV mode; noreceived while stilladdressed as SlaveReceiver or SlaveNo STDATactionrecognition of own SLA or General Call address.A START condition will be transmitted when thebus becomes free.Transmitter.Table 12-15: Slave Transmitter modeSTATStatus of the TWS busApplication software responseNext action taken by TWS hardwareStatusCodeand hardwareTo/From DATTo CONSTA TXRX STO SI AA0x4aOwn SLA+R has beenreceived; ACK hasbeen returned.Load data byte X 0 0 0 XData byte will be transmitted; ACK will bereceived.224 www.xinnovatech.com

XN12L6120x5C0x1C0x1CData byte in DAT hasbeen transmitted; ACKhas been received.Data byte in DAT hasbeen transmitted; NOTACK has beenreceived.Last data byte in DAThas been transmitted(AA = 0); ACK has beenreceived.Load data byte X 1 0 0 0 Last data byte will be transmitted and ACK bitwill be received.Load data byte X 1 0 0 1 Data byte will be transmitted; ACK bit will bereceived.No DAT action 0 1 0 0 0 Switched to not addressed SLV mode; norecognition of own SLA or General Call address.No DAT action 0 1 0 0 1 Switched to not addressed SLV mode; Own SLAwill be recognized; General Call address will berecognized if ADR[0] = logic 1.No DAT action 1 1 0 0 0 Switched to not addressed SLV mode; norecognition of own SLA or General Call address.A START condition will be transmitted when thebus becomes free.No DAT action 1 1 0 0 1 Switched to not addressed SLV mode; Own SLAwill be recognized; General Call address will berecognized if ADR[0] = logic 1. A STARTcondition will be transmitted when the busbecomes free.No DAT action 0 X 0 0 X Switched to not addressed SLV mode; norecognition of own SLA or General Call address.No DAT action 1 X 0 0 X Switched to not addressed SLV mode; norecognition of own SLA or General Call address.A START condition will be transmitted when thebus becomes free.12.4.6 TWS State Service RoutinesThis section provides examples of operations that must be performed by various TWS state service routines. This includes:• Initialization of the TWS block after a Reset.• TWS Interrupt Service• The 13 state service routines providing support for all four TWS operating modes.12.4.6.1 Initialization RoutineExample to initialize TWS Interface as a Slave or Master.1. Load ADR with own Slave Address, enable General Call recognition if needed.2. Enable TWS interrupt.3. Write 0x42 to CONSET to set the EN and MASL bits, enabling Slave functions. For Master functions, write 0x40 toCONSET.12.4.6.2 Start Master Transmit FunctionBegin a Master Transmit operation by setting up the buffer, pointer, and data count, then initiating a START.www.xinnovatech.com 225

XN12L6121. 6 E Initialize Master data counter.2. Set up the Slave Address to which data will be transmitted, and add the Write bit.3. Write 0x20 to CONSET to set the STA bit.4. Set up data to be transmitted in Master Transmit buffer.5. Exit12.4.6.3 Start Master Receive FunctionBegin a Master Receive operation by setting up the buffer, pointer, and data count, then initiating a START.1. Initialize Master data counter.2. Set up the Slave Address to which data will be transmitted, and add the Read bit.3. Write 0x20 to CONSET to set the STA bit.4. Set up the Master Receive buffer.5. Exit12.4.6.4 TWS Interrupt RoutineDetermine the TWS state and which state routine will be used to handle it.• Read the TWS status from STA.• Use the status value to branch to one of 13 possible state routines.12.4.6.5 Non Mode Specific StatesState: 0x01A START condition has been transmitted. The Slave Address + R/W bit will be transmitted, an ACK bit will be received.1. Write Slave Address with R/W bit to DAT.2. Write 0x04 to CONSET to set the AA bit.3. Write 0x08 to CONCLR to clear the SI flag.4. Set up Master Transmit mode data buffer.5. Set up Master Receive mode data buffer.6. Initialize Master data counter.7. ExitState: 0x0bA Repeated START condition has been transmitted. The Slave Address R/W bit will be transmitted, an ACK bit will bereceived.1. Write Slave Address with R/W bit to DAT.2. Write to CONSET to set the AA bit and TXRX bit.3. Write 0x08 to CONCLR to clear the SI flag.226 www.xinnovatech.com

XN12L6124. Set up Master Transmit mode data buffer.5. Set up Master Receive mode data buffer.6. Initialize Master data counter.7. Exit12.4.6.6 Master Transmitter StatesState: 0x0bPrevious state was State 0x01, Slave Address Write has been transmitted, ACK has been received. The first data byte willbe transmitted, an ACK bit will be received.1. Load DAT with first data byte from Master Transmit buffer.2. Write 0x08 to CONCLR to clear the SI flag.3. Increment Master Transmit buffer pointer.4. ExitState: 0x4bSlave Address + Write has been transmitted, NOT ACK has been received. A STOP condition will be transmitted.1. Write 0x14 to CONSET to set the STO and AA bits.2. Write 0x08 to CONCLR to clear the SI flag.3. ExitState: 0x14Data has been transmitted, ACK has been received. If the transmitted data was the last data byte then transmit a STOPcondition, otherwise transmit the next data byte.1. Decrement the Master data counter, skip to step 5 if not the last data byte.2. skip to step 11 if willing to turn to receive data.3. Write 0x14 to CONSET to set the STO and AA bits.4. Write 0x08 to CONCLR to clear the SI flag.5. Exit6. Load DAT with next data byte from Master Transmit buffer.7. Write 0x04 to CONSET to set the AA bit.8. Write 0x08 to CONCLR to clear the SI flag.9. Increment Master Transmit buffer pointer10. Exit11. Set STA and MASL bit to CONSET12. Write slave address with read bit to Transmit bufferwww.xinnovatech.com 227

XN12L61213. Write 0x08 to CONCLR to clear the SI flag.State: 0x54Data has been transmitted, NOT ACK has been received. A stop condition will be transmit.1. Write 0x14 to CONSET to set the STO and AA bits.2. Write 0x08 to CONCLR to clear the SI flag.3. Exit12.4.6.7 Master Receive StatesState: 0x0bPrevious state was State 0x01. Slave Address + Read has been transmitted, ACK has been received. Data will be receivedand ACK returned.1. Write 0x09 to CONCLR to clear the SI flag and TXRX bit.2. ExitState: 0x1bSlave Address + Read has been transmitted, NOT ACK has been received. A STOP condition will be transmitted.1. Write 0x14 to CONSET to set the STO and AA bits.2. Write 0x08 to CONCLR to clear the SI flag.3. ExitState: 0x1dData has been received, ACK has been returned. Data will be read from DAT. Additional data will be received. If this is thelast data byte then NOT ACK will be returned, otherwise ACK will be returned.1. Read data byte from DAT into Master Receive buffer.2. Decrement the Master data counter, skip to step 5 if not the last data byte.3. Write 0x0C to CONCLR to clear the SI flag and the AA bit.4. Write 0x10 to CONSET to set STO bit5. Exit6. Write 0x08 to CONCLR to clear the SI flag.7. Increment Master Receive buffer pointer8. ExitState: 0x5dData has been received, NOT ACK has been returned. Data will be read from DAT. A STOP condition will be transmitted.1. Read data byte from DAT into Master Receive buffer.2. Write 0x14 to CONSET to set the STO and AA bits.228 www.xinnovatech.com

XN12L6123. Write 0x08 to CONCLR to clear the SI flag.4. Exit12.4.6.8 Slave Receiver StatesState: 0x0aOwn Slave Address + Write has been received, ACK has been returned. Data will be received and ACK returned.1. Write 0x08 to CONCLR to clear the SI flag.2. Set up Slave Receive mode data buffer.3. Initialize Slave data counter.4. ExitState: 0x0aGeneral call has been received, ACK has been returned. Data will be received and ACK returned.1. Write 0x08 to CONCLR to clear the SI flag.2. Set up Slave Receive mode data buffer.3. Initialize Slave data counter.4. ExitState: 0x13Previously addressed with own Slave Address. Data has been received and ACK has been returned. Additional data will beread.1. Read data byte from DAT into the Slave Receive buffer.2. Decrement the Slave data counter, skip to step 5 if not the last data byte.3. Write 0x0C to CONCLR to clear the SI flag and the AA bit.4. Exit.5. Write 0x08 to CONCLR to clear the SI flag.6. Increment Slave Receive buffer pointer.7. ExitState: 0x13Previously addressed with own Slave Address. Data has been received and NOT ACK has been returned.1. Write 0x08 to CONCLR to clear the SI flag.2. ExitState: 0x13Previously addressed with General Call. Data has been received, ACK has been returned. Received data will be saved. Onlythe first data byte will be received with ACK. Additional data will be received with NOT ACK.www.xinnovatech.com 229

XN12L6121. Read data byte from DAT into the Slave Receive buffer.2. Write 0x0C to CONCLR to clear the SI flag and the AA bit.3. ExitState: 0x1dA STOP condition or Repeated START has been received, while still addressed as a Slave. Data will not be saved.1. Write 0x08 to CONCLR to clear the SI flag.2. Exit12.4.6.9 Slave Transmitter StatesState: 0x4aOwn Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received.1. Load DAT from Slave Transmit buffer with first data byte.2. Write 0x09 to CONCLR to clear the SI flag and TXRX bit.3. Set up Slave Transmit mode data buffer.4. Increment Slave Transmit buffer pointer.State: 0x5cData has been transmitted, ACK has been received. Data will be transmitted, ACK bit will be received.1. Load DAT from Slave Transmit buffer with data byte.2. Write 0x08 to CONCLR to clear the SI flag.3. Increment Slave Transmit buffer pointer.4. ExitState: 0x1cData has been transmitted, NOT ACK has been received.1. Write 0x08 to CONCLR to clear the SI flag.2. Exit.230 www.xinnovatech.com

XN12L61213 RTC13.1 General DescriptionBy counting 1 Hz/1KHz clock from reference time, RTC timer is used to perform real time clock function. RTC features areshowed as:• Dedicated 32 kHz ultra low power oscillator.• Uses 1 Hz clock to count in one second intervals and 1KHz as one millisecond.• 32-bit RTC counter.• Alarm and wake up functions to system13.2 Pin DescriptionTable 13-1: RTS pin descriptionPin Type DescriptionRTCXIN Input Input to the 32 kHz oscillator circuit.RTCXOUT Output Output from the 32 kHz oscillator amplifier.13.3 RTC Register DescriptionTable 13-2: RTC register overview: (base address 0x4005 0000)Symbol Access Address offset Description Reset valueDR R 0x000 Data register 0x00MR R/W 0x004 Match register 0x00LR R/W 0x008 Load register 0x00CR R/W 0x00C Control register 0x00ICSC R/W 0x010 Interrupt control set/clear register 0x00RIS R 0x014 Raw interrupt status register 0x00MIS R 0x018 Masked interrupt status register 0x00ICR W 0x01C Interrupt clear register 0x0013.3.1 RTC Data RegisterTable 13-3: RTC Data Register (DR - address 0x4005 0000) bit descriptionBit Symbol Description Reset value31:0 DATA Returns the current RTC value. 0x0013.3.2 RTC Match RegisterTable 13-4: RTC Match Register (MR - address 0x4005 0004) bit descriptionBit Symbol Description Reset valuewww.xinnovatech.com 231

XN12L61231:0 MATCH RTC match register value. 0x0013.3.3 RTC Load RegisterTable 13-5: RTC Load Register (LR - address 0x4005 0008) bit descriptionBit Symbol Description Reset value31:0 LOAD RTC load register value. 0x0013.3.4 RTC Control RegisterThis register is a R/W register. Reads return the status of the RTC. Writes enable or disable the RTC. Once the RTC isenabled, any writes to bit 0 of this register will have no effect until after a system reset.Table 13-6: RTC Control Register (CR - address 0x4005 000C) bit descriptionBit Symbol Value Description Reset value0 RTCSTART Enables the RTC. Once the RTC is enabled through this bit, any writes to this0x0bit have no effect on the RTC until a power on reset (POR).0 RTC disabled.1 RTC enabled.31:1 - - Reserved. -13.3.5 RTC Interrupt Control Set/Clear RegisterThis register is a R/W register and controls the masking of the interrupt generated by the RTC. Writing sets or clears themask. Reading this register returns the current value of the mask on the RTC interrupt.Table 13-7: RTC Interrupt Mask Register (ICSC - address 0x4005 0010) bit descriptionBit Symbol Value Description Reset value0 RTCIC Interrupt control register. A read returns the current value of the RTC control0x0register.0 Writing 0 masks the interrupt.1 Writing 1 enables the interrupt.31:1 - - Reserved. 0x013.3.6 RTC Interrupt Status RegisterThis register is a RO register. Reading this register gives the current raw status value of the corresponding interrupt prior tomasking. A write has no effect.Table 13-8: RTC Interrupt Status Register (RIS - address 0x4005 0014) bit descriptionBit Symbol Description Reset value0 RTCRIS Raw interrupt event flag register. A read returns the state of the raw interrupt event flag. 0x031:1 - Reserved. Read as zero. 0x0232 www.xinnovatech.com

XN12L61213.3.7 RTC Masked Interrupt Status RegisterThis register is a RO register. Reading this register gives the current masked status value of the corresponding interrupt. Awrite has no effect.Table 13-9: RTC Masked Interrupt Status Register (MIS - address 0x4005 0018) bit descriptionBit Symbol Description Reset value0 RTCMIS Masked interrupt register status. A read returns the masked interrupt status as controlled0x0by the ICR register.31:1 Reserved. Read as zero. 0x013.3.8 RTC Interrupt Clear RegisterThis register is a WO register. Writing one clears the corresponding interrupt. Writing zero has no effect.Table 12-13-10: RTC Interrupt Clear Register (ICR - address 0x4005 001C) bit descriptionBit Symbol Description Reset value0 RTCICR Raw interrupt event flag clear register. Writing one clears the interrupt event flag.0x0Writing 0 has no effect.31:1 Reserved. Write as zero. 0x013.4 Functional DescriptionUsing the RTC in Deep-sleep or Power-down ModeThe RTC can be configured to wake up the chip from Deep-sleep or Power-down mode when the RTC interrupt is raised.Always select one of the outputs of the RTC oscillator as RTC clock input if the RTC is used to keep time in Deep-sleep orPower-down modes.Note: To obtain a valid RTC value after waking up from Power-down, first perform a “dummy” read on the RTC. The next read containsthe updated RTC value.www.xinnovatech.com 233

XN12L61214 ADC/DAC and On-chip Temperature Sensor14.1 General DescriptionXN12L612 provides three 12-bit ADCs, one 10-bit DAC and on-chip temperature sensor. The follow are major features:• Three 1M Hz 12-bit AD converter.• Input multiplexing among 8 pins.• Supports Power-down mode.• ADC Measurement range 0 to 3.3V.• Burst ADC conversion mode for single or multiple inputs.• Optional ADC conversion on transition on input pin or Timer Match signal.• Individual ADC result registers for each A/D channel to reduce interrupt overhead.• On-chip temperature sensor covers from -40°C to +120°C temperature range• Max 1M Hz 10-bit DA conversion rate14.2 Pin descriptionTable 14-1: ADC pin descriptionPin Type DescriptionAD0~AD7 Input Analog Inputs. The A/D converter cell can measure the voltage on any of these input signals. The inputsignal must not exceed ADC reference voltage (typically 3.3 V)DA0 Output Analog Output.V REF_ADC Input ADC reference voltage.14.3 Register DescriptionTable 14-2: Register overview of ADCs (ADC0: base address 0x4002 0000; ADC1: base address 0x4006 4000; ADC2: base address0x4006 8000)Name Access AddressoffsetDescriptionReset valueCR R/W 0x000 ADC Control Register. The CR register must be written to select theoperating mode before ADC conversion can occur.GDR R/W 0x004 ADC Global Data Register. Contains the result of the most recent ADC0x00000000NAconversion.- - 0x008 Reserved. NA234 www.xinnovatech.com

XN12L612INTEN R/W 0x00C ADC Interrupt Enable Register. This register contains enable bits that allowthe DONE flag of each ADC channel to be included or excluded from0x00000100contributing to the generation of an ADC interrupt.DR0 R/W 0x010 A/D Channel 0 Data Register. This register contains the result of the mostNArecent conversion completed on channel 0DR1 R/W 0x014 A/D Channel 1 Data Register. This register contains the result of the mostNArecent conversion completed on channel 1.DR2 R/W 0x018 A/D Channel 2 Data Register. This register contains the result of the mostNArecent conversion completed on channel 2.DR3 R/W 0x01C A/D Channel 3 Data Register. This register contains the result of the mostNArecent conversion completed on channel 3.DR4 R/W 0x020 A/D Channel 4 Data Register. This register contains the result of the mostNArecent conversion completed on channel 4.DR5 R/W 0x024 A/D Channel 5 Data Register. This register contains the result of the mostNArecent conversion completed on channel 5.DR6 R/W 0x028 A/D Channel 6 Data Register. This register contains the result of the mostNArecent conversion completed on channel 6.DR7 R/W 0x02C A/D Channel 7 Data Register. This register contains the result of the mostNArecent conversion completed on channel 7.Note: ADC1 DR7 is reserved for on-chip temperature sensor conversion.INTSTAT RO 0x030 ADC Status Register. This register contains DONE and OVERRUN flags for0all of the ADC channels, as well as the ADC interrupt flag.HILMT R/W 0x034 ADC High Limit Control Register. This register controls ADC high limit detect0function.LOLMT R/W 0x038 ADC Low Limit Control Register. This register controls ADC low limit detect0function.- - 0x03C Reserved. 0SSCR R/W 0x040 Software 0Table 14-3: Register overview of DAC (base address 0x4006 C180)Name Access AddressoffsetDescriptionReset valueDACCTL R/W 0x180 The D/A Control Register. 0DACBUF W 0x184 The DA converter data buffer. NA14.3.1 ADC Control RegisterThe ADC Control Register provides bits to select A/D channels to be converted, A/D timing, A/D modes, and the A/D starttrigger.Table 14-4: A/D Control Register (CR) bit descriptionBit Symbol Value Description Reset valuewww.xinnovatech.com 235

XN12L6127:0 SEL Selects which of the AD7:0 pins is (are) to be sampled and converted. For ADC, bit 00x0selects Pin AD0, and bit 7 selects pin AD7.15:8 CLKDIV The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the0x0A/D converter. The clock should be less than or equal to16MHz. Each ADCconversion requires 16 clocks. The ADC sample rate can be calculated with ADCclock divided by 16. In trigger mode, the trigger signal rate must less than ADC clockdivided by 16.16 BURST Burst mode control. 00 Trigger mode. Conversions are triggered by signal listed in START flied. In thismode, if more than one channel are selected in SEL field, each trigger just do onechannel conversion scanning loop from AD0 to AD7. The selected channel DR valuewill keep until next turn.1 Burst mode. The AD converter does repeated conversions up to 1MHz, scanning (ifnecessary) through the pins selected by 1s in the SEL field. The first conversion afterthe start corresponds to the least-significant 1 in the SEL field, then higher numbered1 bits (pins) if applicable. Repeated conversions can be terminated by clearing thisbit, but the conversion that’s in progress when this bit is cleared will be completed.Important: START bits must be 000 when BURST = 1 or conversions will not start.23:17 - - Reserved. 0x027:24 START Conversion starts control. When ADC in trigger mode, these bits control whether and0x0when an A/D conversion is started.0x0 No start (this value should be used when clearing PDN to 0).0x10x20x30x40x50x60x7Start conversion by software trigger.Start conversion when the edge selected by bit 28 occurs on CT16B0_CAP0.Start conversion when the edge selected by bit 28 occurs on CT16B0_CAP1.Start conversion when the edge selected by bit 28 occurs on CT32B0_MAT0.Start conversion when the edge selected by bit 28 occurs on CT32B1_MAT0.Start conversion when the edge selected by bit 28 occurs on CT16B0_MAT0.Start conversion when the edge selected by bit 28 occurs on CT16B1_MAT0.28 EDGE Edge control. This bit is significant only when the START field contains 010-111. 01 Start conversion on a falling edge on the selected CAP/MAT signal.0 Start conversion on a rising edge on the selected CAP/MAT signal.29 SCMODE ADC converter sample clock selection 00 Internal clock as sample clock1 External clock as sample clock. This bit must be set to1 when trigger mode selected.31:30 - - Reserved. 0x014.3.2 ADC Global Data RegisterThe ADC Global Data Register contains the result of the most recent AD conversion. This includes the data, DONE, andOVERRUN flags, and the number of the A/D channel to which the data relates.236 www.xinnovatech.com

XN12L612Table 14-5: A/D Global Data Register (GDR) bit descriptionBit Symbol Description Reset value11:0 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on the ADnXpin selected by the SEL field, divided by the voltage on the ADC reference V REF: Zero in thefield indicates that the voltage on the ADn pin was less than, equal to, or close to that on V SS,while 0xFFF indicates that the voltage on ADn was close to, equal to, or greater than that onV REF_ADC.14:12 CHN These bits contain the channel from which the RESULT bits were converted. 00015 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and0overwritten before the conversion that produced the result in the RESULT bits.16 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read0and when the CR is written. If the CR is written while a conversion is still in progress, this bitis set and a new conversion is started.31:17 - Reserved NA14.3.3 ADC Interrupt Enable RegisterThis register allows control over which A/D channels generate an interrupt when a conversion is complete. For example, itmay be desirable to use some A/D channels to monitor sensors by continuously performing conversions on them. The mostrecent results are read by the application program whenever they are needed. In this case, an interrupt is not desirable at theend of each conversion for some A/D channels.Table 14-6:: A/D Interrupt Enable Register (INTEN) bit descriptionBit Symbol Description Reset value7:0 INTEN These bits allow control over which A/D channels generate interrupts for conversion0x00completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generatean interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generatean interrupt, etc.8 GINTEN When 1, enables the global DONE flag in ADC DR to generate an interrupt. When 0, only1the individual A/D channels enabled by INTEN 7:0 will generate interrupts.31:9 - Reserved. NA14.3.4 ADC Data RegistersThe ADC Data Register hold the result when an A/D conversion is complete, and also include the flags that indicate when aconversion has been completed and when a conversion overrun has occurred.Table 14-7: A/D Data Registers (DR0 to DR7) bit descriptionBit Symbol Description Reset value11:0 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on the ADnXpin selected by the SEL field, divided by the voltage on the ADC V REF_ADC: Zero in the fieldindicates that the voltage on the ADn pin was less than, equal to, or close to that on V SS,while 0xFFF indicates that the voltage on ADn was close to, equal to, or greater than thaton V REF_ADC.www.xinnovatech.com 237

XN12L61229:12 - Reserved. 0x030 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and0overwritten before the conversion that produced the result in the RESULT bits. This bit iscleared by reading this register.31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is0read.14.3.5 ADC Interrupt Status RegisterThe A/D Status Register allows checking the status of all A/D channels simultaneously. The DONE and OVERRUN flagsappearing in the ADC DRn register for each A/D channel are mirrored in ADC STAT. The interrupt flag (the logical OR of allDONE flags) is also found in ADC STAT.Table 14-8: A/D Status Register (STAT) bit descriptionBit Symbol Description Reset value7:0 DONE These bits mirror the DONE status flags that appear in the result register for each A/D0channel.15:8 OVERRUN These bits mirror the OVERRRUN status flags that appear in the result register for each0A/D channel. Reading ADC STAT allows checking the status of all A/D channelssimultaneously.16 ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags0is asserted and enabled to contribute to the A/D interrupt via the ADC INTEN register.17 HILMTFLAG0 High limit 0 status. Set when the channel’s value greater than high limit 0, cleared by write a01 to this bit18 HILMTFLAG1 High limit 1 status. Set when the channel’s value greater than high limit 1, cleared by write a01 to this bit19 LOLMTFLAG0 Low limit 0 status. Set when the channel’s value less than low limit 0, cleared by write a 1 to0this bit20 LOLMTFLAG1 Low limit 1 status. Set when the channel’s value less than low limit 1, cleared by write a 1 to0this bit21 ADCRDY The bit value 1 indicates ADC converter is ready to use after ADC is enable. 031:22 - Reserved. 0x014.3.6 High Limit Control RegisterThe High Limit Control Register is used to set the high limit value and which channel to be compared with this value. Whenthe channel which is selected greater than the limit value, a flag is set and an interrupt can be generated. There are two highlimit comparators in each ADC.Table 14-9: High Limit Control Register(HILMT) bit descriptionBit Symbol Value Description Reset value11:0 HILMT0 0~0xFFF High Limit value 0. 014:12 CHNSEL0 0~7 Select which channel to compare with the high limit value 0 which is set in bit 0238 www.xinnovatech.com

XN12L61211:0.15 INTEN0 This bit allows an interrupt to be generated when the channel’s voltage is0higher than limit.0 Disable interrupt1 Enable interrupt27:16 HILMT1 0~0xFFF High Limit value 1. 030:28 CHNSEL1 0~7 Select which channel to compare with the high limit value 1 which is set in bit027:16.31 INTEN1 This bit allows an interrupt to be generated when the channel’s voltage is0higher than limit.0 Disable interrupt1 Enable interrupt14.3.7 Low Limit Control RegisterThe Low Limit Control Register is used to set the low limit value and which channel to be compared with this value. When thechannel which is selected less than the limit value, a flag is set and an interrupt can be generated. There are two low limitcomparators in each ADC.Table 14-10: Low Limit Control Register(LOLMT) bit descriptionBit Symbol Value Description Reset value11:0 LOLMT0 0~0xFFF Low Limit value 0. 014:12 CHNSEL0 0~7 Select which channel to compare with the high limit value 0 which is set in bit011:0.15 INTEN0 This bit allows an interrupt to be generated when the channel’s voltage is0higher than limit.0 Disable interrupt1 Enable interrupt27:16 LOLMT1 0~0xFFF Low Limit value 1. 030:28 CHNSEL1 0~7 Select which channel to compare with the high limit value 1 which is set in bit027:16.31 INTEN1 This bit allows an interrupt to be generated when the channel’s voltage is0higher than limit.0 Disable interrupt1 Enable interrupt14.3.8 Software Sample Control RegisterThe Software Sample Control Register is used to trigger one time ADC conversionTable 14-11: Software Sample Control Register(SSCR) bit descriptionBit Symbol Value Description Reset value0 ADCTRIG - Set this bit to trigger ADC to do one time conversion. 0www.xinnovatech.com 239

XN12L61231:2 - - Reserved. 014.3.9 D/A Control RegisterThe D/A Control Register provides bits to select DA conversion mode and rate.Table 14-12: D/A Control Register (DACCTL) bit descriptionBit Symbol Value Description Reset value7:0 DACDIVIDER DACDIVIDER is used to control DA conversion rate. The DAC conversion rate0shall not more than 1MHz.Conversion rate=PCLK/DACDIVIDER8 DACMODE DA converter supports two modes: burst mode and single mode. When DAC0is in burst mode, DAC data to be converted will be put in pinpang buffer first,then DAC take data from buffer out as presetting conversion rate. Each ofbuffer is able to hold 4 data. If DAC was set in single mode, DAC will convertDA data right away.0 DAC in Single mode.1 DAC in Burst mode9 DACCLR This bit is used to clear data in DAC pingpang buffer0When this bit is set from LOW to HIGH, the buffer is clear. Reset this bit toLOW, the pingpang buffer back to normal.10 DACINTEN Enable ADC interrupt when DACBUFSTAT change to 1. 00x00x1Disable interruptEnable interrupt11 DACDMAEN Enable ADC DMA operation. If ADC DMA is enabled and DACBUFSTATchange to 1, the DAC will issue DMA request.0x00x1Disable DMAEnable DMA12 DACEN DAC enable0x00x1Disable DAC conversionEnable DAC conversion14:13 - Reserved NA15 DACBUFSTAT DAC Buffer state 01 When one of pinpang buffer is empty.0 Pingpang buffer is not empty.31:16 - Reserved. 014.3.10 D/A Data RegisterTable 14-13: D/A Data Register (DACBUF) bit descriptionBit Symbol Description Reset value240 www.xinnovatech.com

XN12L6129:0 DACBUF 10-bit DA converter data buffer 031:10 - Reserved. 014.4 Operation14.4.1 Select ADC Converter for Each AD Input ChannelThe device is built in three scaling and cyclic converter. Each converter is able to scan up to 8 AD input channel. The user isallowed to select which ADC converter for AD input channel. All ADC converters have duplicated control, flags andconversion results registers. The user must pick up their data properly from the related ADC converter.14.4.2 ADC Hardware-Triggered ConversionOnce an ADC conversion is started, it cannot be interrupted. A new software writes to launch a new conversion or a newedge-trigger event will be ignored while the previous conversion is in progress.If the BURST bit in the ADC CR is 0 and the START field contains 010-111, the ADC will start a conversion when a transitionoccurs on a selected pin or Timer Match signal. The choices include conversion on a specified edge of any of 4 Matchsignals, or conversion on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad or theselected Match signal, XORed with ADC CR bit 27, is used in the edge detection logic.14.4.3 InterruptsAn interrupt request is asserted to the NVIC when the one of DONE bit is 1. Software can use the Interrupt Enable bit for theA/D Converter in the NVIC to control whether this assertion results in an interrupt. DONE is negated when the ADC DRn isread. The user interrupt handler for ADC must do query to ADC registers to identify interrupt source and process properly.14.4.4 ADC DMA ControlA DMA transfer request is generated from the ADC interrupt request line. To generate a DMA transfer, the same conditionsmust be met as the conditions for generating an interrupt.Note: If the DMA is used, the ADC interrupt must be disabled in the NVIC. For DMA transfers, the transfer size can be set toone in the DMA channel control structure or to the number of ADC channels that are converted. The DMA transfer sizedetermines when a DMA interrupt is generated.14.4.5 DAC DMA ControlA DMA transfer request is generated from the DAC interrupt request line. To generate a DMA transfer, the same conditionsmust be met as the conditions for generating an interrupt.Note: If the DMA is used, the DAC interrupt must be disabled in the NVIC. For DMA transfers, the transfer size can be set toone in the DMA channel control structure or to the number of DAC channels that are converted. The DMA transfer sizedetermines when a DMA interrupt is generated.www.xinnovatech.com 241

XN12L61214.4.6 On-chip Temperature SensorThe on-chip temperature sensor measures the junction temperature of the device. The sensor output can be sampled withthe ADC1 on channel 7 and return ADC value with ADC1 DR7.The temperature sensor output and the resulting ADC values increase with increasing junction temperature. The offset isdefined as the 0 ºC LSB crossing as illustrated in Figure 14-1. This information can be used to convert the ADC sensorsample into a temperature unit. The transfer function to determine a temperature is defined as:Temperature = (sensor - Offset) * SlopeTemperatureOffset(0°C LSB ValueSlope(°C LSB ValueOffset(0°C LSB Value`LSBFigure 14-1: On-chip temperature sensor transfer functionFor XN62L:• 0x xxxxx- Slope (ºC / LSB, fixed-point Q15 format)• 0x xxxxx - Offset (0 ºC LSB value)The values listed are assuming a 3.3v full scale range. Using the internal reference mode automatically achieves this fixedrange, but if using the external mode, the temperature sensor values must be adjusted accordingly to the external referencevoltages. There are three steps to using the temperature sensor:1. Configure the ADC to sample the temperature sensor2. Sample the temperature sensor242 www.xinnovatech.com

XN12L6123. Convert the result into a temperature unit, such as ºC.www.xinnovatech.com 243

XN12L61215 Comparator15.1 General DescriptionTwo embedded comparators are incorporated on-chip to compare the voltage levels on external pins or against internalvoltages/DA output. Up to six voltages on external pins and two internal reference voltages or DA output are selectable oneach comparator. Additionally, four of the external input voltages can be selected to drive an input common on bothcomparators in case identical voltages are required on both comparators. The major features as the following:• Up to six selectable external sources per comparator; fully configurable on either positive or negative comparator inputchannels.• 10-bit DA output and internal reference voltage selectable on both comparators; configurable on either positive ornegative comparator input channels.• 32-stage voltage ladder internal reference to V DD(3V3) voltage on both comparators; configurable on either positive ornegative comparator input channels.• Voltage ladder can be separately powered down for applications only requiring the comparator function.• Individual comparator interrupts connected to I/O pins, common interrupt connected to NVIC.• Edge and level comparator outputs connect to two timers allowing edge tick counting while a level match has beenasserted.AN ALOGLOGICCMPn_LEVELVDD(3V3)32+-DIGITAL LOGICC0_OUTCMP0_LEVELC0_IN[0:5]DA OutputC1_IN[0:5]66+-C1_OUTCMP1_LEVELsyncINT14APB REGISTERS6CMP_REG7edge detectCMP0_EDGECMP1_EDGEVLAD_REGAPB INTERFACEPCLKFigure 15-1: Comparator block diagram244 www.xinnovatech.com

XN12L61215.2 Pin DescriptionTable 15-1: Comparator pin descriptionPin Type DescriptionACMP0_I[3:0] input Comparator 0 input sources (ACMP0_I[0] and ACMP0_I[1] can be programmed for Comparator 1inputs)ACMP1_I[3:0] input Comparator 1 input sources (ACMP1_I[0] and ACMP1_I[1] can be programmed for Comparator 0inputs)ACMP0_O output Comparator 0 outputACMP1_O output Comparator 1 output15.3 Register DescriptionTable 15-2: Register overview: Comparator (base address 0x4005 4000)Symbol Access Address offset Description Reset valueCCR R/W 0x00 Comparator control register 0VLAD R/W 0x04 Voltage ladder register 0- - 0x08 Reserved NAINTSTA R/W 0x0C Interrupt status 015.3.1 Comparator Control RegisterThis register enables the comparators, configures the interrupts, and controls the input multiplexer to both comparators.Table 15-3: Comparator Control Register (CCR, address 0x4005 4000) bit descriptionBit Symbol Value Description Reset value0 CMP0_EN Enable Comparator 0. 00 Comparator 0 disabled.1 Comparator 0 enabled.1 CMP1_EN Enable Comparator 1. 00 Comparator 1 disabled.1 Comparator 1 enabled.2 CMPIL Selects level interrupt. 00 High level triggered.1 Low level triggered.3 CMPIEV Select edge triggered interrupt to be active on either high or low0transitions.0 Interrupt active on rising edges.1 Interrupt active on falling edges.4 CMPBE Select interrupt source. 00 Edge triggered.1 Level triggered.5 CMP1_INTEN Comparator 1 interrupt enable 0www.xinnovatech.com 245

XN12L6126 CMP0_INTEN Comparator 0 interrupt enable 07 CMPSA Select async/sync output of the comparator 0/1. 00 The comparator output is used directly.1 The comparator output is synchronized with the bus clock for output toother modules.10:8 CMP0_VP_CTRL Selection of comparator 0, positive voltage input channel. 0000x00x10x20x30x40x50x60x7Voltage ladder outputACMP0_I0ACMP0_I1ACMP0_I2ACMP0_I3ACMP1_I0ACMP1_I1DA output13:11 CMP0_VM_CTRL Selection of comparator 0, negative voltage input channel. 0000x00x10x20x30x40x50x60x7Voltage ladder outputACMP0_I0ACMP0_I1ACMP0_I2ACMP0_I3ACMP1_I0ACMP1_I1DA output16:14 CMP1_VP_CTRL Selection of comparator 1, positive voltage input channel. 0000x00x10x20x30x40x50x60x7Voltage ladder outputACMP1_I0ACMP1_I1ACMP1_I2ACMP1_I3ACMP0_I0ACMP0_I1DA output19:17 CMP1_VM_CTRL Selection of comparator 1, negative voltage input channel. 0000x00x10x20x30x40x50x6Voltage ladder outputACMP1_I0ACMP1_I1ACMP1_I2ACMP1_I3ACMP0_I0ACMP0_I1246 www.xinnovatech.com

XN12L6120x7DA output21:20 - - Reserved NA22 CMP0_DMAEN - Comparator 0 DMA enable 023 CMP1_DMAEN - Comparator 1 DMA enable 024 CMP0_PO - Comparator 0 output polarity control 025 CMP1_PO - Comparator 1 output polarity control 027:26 - - Reserved NA28 CMP0_RLT - Comparator 0 output 029 CMP1_RLT - Comparator 1 output 031:30 - - Reserved. 015.3.2 Voltage Ladder RegisterThis register enables the voltage ladder for the comparator reference input. The reference input V REF is programmable in 32levels from V SS to 1.8V/3.3 V.Table 15-4: Voltage Ladder Register (VLAD, address 0x4005 4004) bit descriptionBit Symbol Value Description Reset value0 VLADEN Voltage ladder enable 00 Voltage ladder disabled.1 Voltage ladder enabled.5:1 VSEL Voltage ladder value. The reference voltage VLADREF depends on the0setting of bit 6 in this register:00000 = V SS00001 = 1 × VLADREF /3100010 = 2 × VLADREF /31...11111 = VLADREF6 VLADREF Voltage ladder input select 00 Internal 1.8v1 V DD(3V3) pin7 - - Reserved 015:8 DIV Comparator clock divider 00 Comparator is disabled1~255 Comparator working frequency31:16 - - Reserved NA15.3.3 Interrupt Status RegisterTable 15-5: Interrupt Status Register (INTSTA, address 0x4005 400C) bit descriptionBit Symbol Description Reset value0 CMP0_INT Comparator 0 interrupt flag. 0www.xinnovatech.com 247

XN12L612Write 1 to clear interrupt flag.1 CMP1_INT Comparator 1 interrupt flag.0Write 1 to clear interrupt flag.31:2 - Reserved NA15.4 Functional Description15.4.1 Input MultiplexerThe two comparators each have 8 inputs multiplexed separately to both their positive and negative inputs. The multiplexersfor each comparator (both positive and negative inputs) are all controlled by the comparator register CMP. Bit 0 of thepositive and negative inputs on each comparator can be selected to derive from a programmable voltage ladder output. Bit 7of the positive and negative inputs on each comparator can be selected that drives from the on-chip bandgap voltage. Theremaining 6 comparator inputs for the positive and negative sides of the comparators come from external chip IO pins.However due to a limitation on availability, only four IO pins are dedicated for each comparator. The two remaining inputs foreach comparator can be selected from alternate comparators inputs if desired; ACMP0_I0 and ACMP0_I1 can be selectedfor ACMP1_I4 and ACMP1_I5 input sources respectively, similarly ACMP1_I0 and ACMP1_I1 can selected for ACMP0_I4and ACMP0_I5 input sources respectivelyVDD(3V3)C0_IN0C0_IN1AN ALOGLOGICC0_IN2C0_IN332+-C1_IN0C1_IN16666+-C1_IN2C1_IN4C1_IN5C1_IN3Output From DAFigure 15-2: Comparator inputs248 www.xinnovatech.com

XN12L61215.4.2 InterruptsThe interrupt can be selected to be edge or level style. If level is selected, the interrupt leaving this block is synchronized firstto the peripheral clock domain to prevent an asynchronous interrupt path crashing the CPU. If edge level interrupts areselected, a choice of active high, active low or active both edges can be selected. Interrupts are cleared by the CPU writingCLINT high. The combined interrupts of comparator0 and comparator1 are routed to the NVIC for ISR purposes using theCPU.15.4.3 Comparator OutputsThe two comparator level outputs are routed to external pins. The level and edge comparator outputs are also internallyconnected to the capture inputs of the two 16-bit timers. The outputs can be selected in synchronous or asynchronousmodes:• For internal connection to the timer capture inputs, synchronous or asynchronous modes can be selected.• When the asynchronous outputs are routed to external pins, the comparators can be used without clocking PCLK to savepower once the device is configured.• When the comparator is configured to wake up the part from Deep-sleep mode, the asynchronous mode must beselected. In addition, the status of each comparator output can be observed through the comparator status register bitsThe level and edge outputs of each comparator are routed to the two 16-bit timers internally as listed below:• 16-bit timer 0 (CT16B0):– capture input 3: comparator 0 edge– capture input 2: comparator 0 level• 16-bit timer 1 (CT16B1):– capture input 3: comparator 1 edge– capture input 2: comparator 1 levelThis feature allows tick-counting on comparator output transitions on either the positive edge, the negative edge, or bothedges (depending on the comparator register configuration), if the edge capture is chosen. If the timer level capture ischosen, the counter can run while the comparator output is in a given state.www.xinnovatech.com 249

XN12L61216 DMA16.1 General DescriptionThe DMA controller is a very low-gate-count DMA compatible with the AMBA. AHB-Lite protocol for DMA transfers. The DMAregisters are programmed through the APB interface. The DMA Features are as the following:• Single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit data bus.• 26 DMA channels.• Dedicated handshake signals and programmable priority level for each channel.• Each priority level arbitrates using a fixed priority that is determined by the DMA channel number.• Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers.• Supports multiple DMA cycle types and multiple DMA transfer widths.• Each DMA channel can access a primary and an alternate channel control data structure.• The channel control data is stored in system memory in little-endian format.• Performs all DMA transfers using single AHB-Lite transfers. Burst transfers are not supported.• The destination data width is equal to the source data width.• The number of transfers in a single DMA cycle can be programmed from 1 to 1024.• The transfer address increment can be greater than the data width.16.2 OperationsThe DMA controller contains an APB register interface, the AHB-Lite master interface to the AHB multi-layer matrix, and theDMA control block.DMAconfigurationcontrolAPB BUSAPBREGISTERINTERFACErequestsDMA stallDMACONTROLAHB-LiteMASTERINTERFACEAPB BUSDMA datatransfermodeactive channelchannel doneerrorFigure 16-1: DMA controller block diagram250 www.xinnovatech.com

XN12L612The DMA controller supports data transfer sizes of 8, 16, or 32 bit (byte, half-word, or word), configured through the channelcontrol data structure. The source data transfer size and the destination data transfer size must be the same. The controlleralways uses 32-bit data transfers when it accesses a channel control data structure.The DMA control block contains the control logic that performs the following tasks:• Arbitrates the incoming requests.• Indicates which channel is active.• Indicates when a channel is complete.• Indicates when an error has occurred on the AHB-Lite interface.• Enables slow peripherals to stall the completion of a DMA cycle.• Waits for a request to clear before completing a DMA cycle.• Performs multiple or single DMA transfers for each request.• Performs the following types of DMA transfers:– memory-to-memory– memory-to-peripheral– peripheral-to-memory– peripheral-to- peripheral16.3 Memory Regions Accessible By the Micro DMA ControllerThe DMA channel control data structure is written to and updated in SRAM. Memory-to-memory DMA transfers aresupported as software-controlled transfers.16.3.1 DMA System ConnectionsThe type of connection between the DMA and the supported peripheral devices depends on the DMA functions implementedin those peripherals. SPI uses single transfer and transfer requests, UART and ADC use transfer requests allowing one ormore transfers.Table 16-1: DMA connectionsPeripheral DMA channel single DMA transfer request DMA transfer requestUART0 Tx 0 yes yesUART0 Rx 1 yes yesUART1 Tx 2 yes yesUART1 Rx 3 yes yesSPI Tx 4 yes yesSPI Rx 5 yes yesADC 0 6 yes yesRTC 7 yes yes32-bit Timer 0 match 0 8 yes yes32-bit Timer 0 match 1 9 yes yeswww.xinnovatech.com 251

XN12L61232-bit Timer 1 match 0 10 yes yes32-bit Timer 1 match 1 11 yes yes16-bit Timer 0 match 0 12 yes yes16-bit Timer 1 match 0 13 yes yesComparator 0 14 yes yesComparator 1 15 yes yesPIO 0 16 yes yesPIO 1 17 yes yesPIO 2 18 yes yesDAC 19 yes yesReserved 20 - -Reserved 21 - -ADC1 22 yes yesADC2 23 yes yesUART2 TX 24 yes yesUART2 RX 25 yes yesUART3 TX 26 yes yesUART3 RX 27 yes yes16.4 Clocking and Power ControlThe clock to the DMA controller is provided by the system clock, which is controlled by the SYSAHBCLKDIV register. TheDMA controller can be disabled through the System AHB clock control register bit 12 for power savings.Table 16-2: Register overview: DMA (base address 0x4004 C000)Symbol Access Address offset Description Reset valueDMA_STATUS RO 0x000 DMA status register -DMA_CFG WO 0x004 DMA configuration register -CTRL_BASE_PTR R/W 0x008 Channel control base pointer register 0x0000 0000- - 0x00C-0x010 - -CHNL_SW_REQUEST WO 0x014 Channel software request register -CHNL_USEBURST_SET R/W 0x018 Channel useburst set register 0x0000 0000CHNL_USEBURST_CLR WO 0x01C Channel useburst clear register -CHNL_REQ_MASK_SET R/W 0x020 Channel request mask set register 0x0000 0000CHNL_REQ_MASK_CLR WO 0x024 Channel request mask clear register -CHNL_ENABLE_SET R/W 0x028 Channel enable set register 0x0000 0000CHNL_ENABLE_CLR WO 0x02C Channel enable clear register -- - 0x030- 0x034 Reserved. -CHNL_PRIORITY_SET R/W 0x038 Channel priority set register 0x0000 0000CHNL_PRIORITY_CLR WO 0x03C Channel priority clear register -252 www.xinnovatech.com

XN12L612- - 0x040 - 0x07C Reserved -CHNL_IRQ_STATUS R/W 0x080 Channel DMA interrupt status register 0x0000 0000- - 0x084 Reserved -CHNL_IRQ_ENABLE R/W 0x088 Channel DMA interrupt enable register 0x0000 000016.4.1 DMA Status RegisterThis register is a read-only register and returns the status of the micro DMA controller. This register cannot be read when themicro DMA controller is in the reset state.Table 16-3: DMA Status Register (DMA_STATUS, address 0x4004 C000) bit descriptionBit Symbol Description Reset value0 MASTER_EN Enable status of the controller:0 = controller disabled.1 = controller enabled.3:1 - Reserved.7:4 STATE Current state of the control state machine. State can be one of thefollowing:0000 = idle0001 = reading channel controller data0010 = reading source data end pointer0011 = reading destination data end pointer0100 = reading source data0101 = writing destination data0110 = waiting for DMA request to clear0111 = writing channel controller data1000 = stalled1001 = done1010 = peripheral scatter-gather transition1011-1111 = undefined5:31 - Reserved. NA16.4.2 DMA Configuration RegisterThis register is a write-only register and configures the micro DMA controller.Table 16-4: DMA Configuration Register (DMA_CFG, address 0x4004 C004) bit descriptionBit Symbol Value Description Reset value0 MASTER_EN Enable for the DMA controller. -0 Disables the controller.1 Enables the controller.31:1 - - Reserved. Write as zero. -www.xinnovatech.com 253

XN12L61216.4.3 Channel Control Base Pointer RegisterThis register is a read/write register and configures the base pointer. The base pointer must point to a location in the MCU’sSRAM because the micro DMA controller provides no internal memory for storing the channel control data structure. Theregister cannot be read when the micro DMA controller is in the reset state.Table 16-5: Channel Control Base Pointer Register (CTRL_BASE_PTR, address 0x4004 C008)bit descriptionBit Symbol Description Reset value31:0 CTRL_BASE_PTR Pointer to the base address of the primary data structure. 0x016.4.4 Channel Wait on Request Status RegisterThis register is a read-only register and returns the status of the dma_waitonreq[c] signal for a channel c (c = 0 to 27). Theregister cannot be read when the DMA controller is in the reset state.Table 16-6: Channel Wait on Request Status Register (DMA_WAITONREQ_STATUS, address 0x4004 C010) bit descriptionBit Symbol Description Reset value27:0 DMA_WAITONREQ_STATUSChannel c wait-on-request status (c = 0 to 27):Bit c = 0: dma_waitonreq[c] is LOW.Bit c = 1: dma_waitonreq[c] is HIGH.-31:28 - Reserved. -16.4.5 Channel Software Request RegisterThis is a write-only register and enables the generation of a software DMA request for a channel c (c = 0 to 27). Writing to abit where a DMA channel is not implemented does not create a DMA request for that channel.Table 16-7: Channel software request register (CHNL_SW_REQUEST, address 0x4004 C014) bit descriptionBit Symbol Description Reset value27:0 DMA_SW_ REQUEST Set the appropriate bit to generate a software DMA request on the-corresponding DMA channel. Write as:Bit [c] = 0: Does not create a DMA request for channel c.Bit [c] = 1: Creates a DMA request for channel c.31:28 - Reserved. -16.4.6 Channel Useburst Set RegisterThis register is a read/write register and disables the single DMA request (dma_sreq[c]) input for a channel c (c = 0 to 27)from generating requests. Therefore, only the dma_req[c] signal generates requests.Note: Reading this register returns the Useburst status. Writing to a bit where a DMA channel is not implemented has noeffect.254 www.xinnovatech.com

XN12L612Table 16-8: Channel Useburst Set Register (CHNL_USEBURST_SET, address 0x4004 C018) bit descriptionBit Symbol Description Reset value27:0 DMA_USEBURST_SETReturns the useburst status for channel c (c = 0 to 27) or disables dma_sreq[c]from generating DMA requests.Read as:Bit [c] = 0: DMA channel c responds to requests that it receives on dma_sreq[c].The controller performs single, bus transfers.Bit [c] = 1: DMA channel c respond to requests that it receives on dma_sreq[c].The controller only responds to dma_req[c] requests and performs 2 R transfers.Write as:Bit [c] = 0: No effect. Use the CHNL_USEBURST_CLR register to set bit [c] to 0.Bit [c] = 1: Disables dma_sreq[C] from generating DMA requests. The controllerperforms 2 R transfers.0x031:28 - Reserved. -16.4.7 Channel Useburst Clear RegisterThis register is a write-only register and enables the DMA single request for a channel c (c = 0 to 27, dma_sreq[c]) togenerate requests. Writing to a bit where a DMA channel is not implemented has no effect.Table 16-9: Channel Useburst Clear Register (CHNL_USEBURST_CLR, address 0x4004 C01C) bit descriptionBit Symbol Description Reset value27:0 CHNL_USEBURST_ CLR Set the appropriate bit to enable dma_sreq[c] to generate requests.-Write as:Bit [c] = 0: No effect. Use the chnl_useburst_set Register to disabledma_sreq[c] from generating requests.Bit [c] = 1: Enables dma_sreq[c] to generate DMA requests.31:28 - Reserved. -16.4.8 Channel Request Mask Set RegisterThis register is a read/write register and disables a HIGH on the DMA request signal for a channel c (c = 0 to 27) (dma_req[c]signal), or the single DMA request signal (dma_sreqc[c]), from generating a request. Reading the register returns the requestmask status for dma_req[c] and dma_sreq[c]. Writing to a bit where a DMA channel is not implemented has no effect.Table 16-10: Channel Request Mask Set Register (CHNL_REQ_MASK_SET, address 0x4004 C020) bit descriptionBit Symbol Description Reset valuewww.xinnovatech.com 255

XN12L61227:0 CHNL_REQ_ MASK_SET Returns the request mask status of dma_req[c] and0x0dma_sreq[c], or disables the corresponding channel from generatingDMA requests.Read as:Bit [c] = 0: External requests are enabled for channel c.Bit [c] = 1: External requests are disabled for channel c.Write as:Bit [c] = 0: No effect. Use the CHNL_REQ_MASK_CLR Register toenable DMA requests.Bit [c] = 1: Disables dma_req[c] and dma_sreq[c] from generating DMArequests.31:28 Reserved. -16.4.9 Channel Request Mask Clear RegisterThis register is a write-only register and for a channel c (c = 0 to 27) enables a HIGH on dma_req[c], or dma_sreq[c], togenerate a request. Writing to a bit where a DMA channel is not implemented has no effect.Table 16-11: Channel Request Mask Clear Register (CHNL_REQ_MASK_CLR, address 0x4004 C024) bit descriptionBit Symbol Description Reset value27:0 CHNL_REQ_ MASK_CLR Set the appropriate bit to enable DMA requests for the channel-corresponding to dma_req[c] and dma_sreq[c].Write as:Bit [c] = 0: No effect. Use the chnl_req_mask_set Register to disabledma_req[c] and dma_sreq[c] from generating requests.Bit [c] = 1: Enables dma_req[c] or dma_sreq[c] to generate DMArequests.31:28 Reserved. -16.5 Channel Enable Set RegisterThis register is a read/write register and enables a DMA channel c (c = 0 to 27). Reading the register returns the enablestatus of the channels. Writing to a bit where a DMA channel is not implemented has no effect.Table 16-12: Channel Enable Set Register (CHNL_ENABLE_SET, address 0x4004 C028) bit descriptionBit Symbol Description Reset value27:0 CHNL_ENABLE_ SET Returns the enable status of the channels, or enables the0x0corresponding channels.Read as:Bit [c] = 0: Channel c is disabled.Bit [c] = 1 Channel c is enabled.Write as:256 www.xinnovatech.com

XN12L612Bit [c] = 0: No effect. Use the CHNL_ENABLE_CLR Register todisable a channel.Bit [c] = 1: Enables channel c.31:24 Reserved. -16.5.1 Channel Enable Clear RegisterThis register is a write-only register and disables a DMA channel. Writing to a bit where a DMA channel is not implementedhas no effect.Note: The controller disables a channel by setting the appropriate bit when either:• The controller completes the DMA cycle.• The controller reads a channel_cfg memory location which has cycle_ctrl = 000.• An error occurs on the AHB-Lite bus.Table 16-13: Channel Enable Clear Register (CHNL_ENABLE_CLR, address 0x4004 C02C) bit descriptionBit Symbol Description Reset value23:0 CHNL_ENABLE_ CLR Set the appropriate bit to disable the corresponding DMA channel.-Write as:Bit [c] = 0: No effect. Use the CHNL_ENABLE_SET Register to enableDMA channels.Bit [c] = 1 Disables channel c.31:24 - Reserved. -16.5.2 Channel Priority Set RegisterThis register is read/write register and configures a DMA c (c = 0 to 27) channel to use the high priority level. Reading theregister returns the status of the channel priority mask. Writing to a bit where a DMA channel is not implemented has noeffect.Table 16-14: Channel Priority Set Register (CHNL_PRIORITY_SET, address 0x4004 C038) bit descriptionBit Symbol Description Reset value27:0 CHNL_PRIORITY_SET Returns the channel priority mask status, or sets the channel0x0priority to high.Read as:Bit [c] = 0: DMA channel c is using the default priority level.Bit [c] = 1: DMA channel c is using a high priority level.Write as:Bit [c] = 0: No effect. Use the CHNL_PRIORITY_CLR Register to setchannel c to the default priority level.Bit [c] = 1: Channel c uses the high priority level.31:28 - Reserved. -www.xinnovatech.com 257

XN12L61216.5.3 Channel Priority Clear RegisterThis register is a write-only register and configures a DMA channel c (c = 0 to 27) to use the default priority level. Writing to abit where a DMA channel is not implemented has no effect.Table 16-15: Channel Priority Clear Register (CHNL_PRIORITY_CLR, address 0x4004 C03C) bit descriptionBit Symbol Description Reset value27:0 CHNL_PRIORITY_CLR Set the appropriate bit to select the default priority level for the specified-DMA channel. Write as:Bit [c] = 0: No effect. Use the CHNL_PRIORITY_SET Register to setchannel c to the high priority level.Bit [c] = 1: Channel c uses the default priority level.31:28 - Reserved. -16.5.4 Channel DMA Interrupt Status RegisterThis register is a read/write register and shows the DMA done interrupt status for each DMA channel c (c = 0 to 27). Writing aone clears the status bit. Writing to a bit where a DMA channel is not implemented has no effect.Table 16-16: Channel DMA Interrupt Status Register (CHNL_IRQ_STATUS, address 0x4004 C080) bit descriptionBit Symbol Description Reset value27:0 CHNL_IRQ_STAT Returns the status of the DMA done interrupt for each channel.0x0Read as:Bit [c] = 0: DMA done interrupt not asserted.Bit [c] = 1: DMA transfer complete for Channel c.Write as:Bit [c] = 0: No effect.Bit [c] = 1: Clears the DMA done status for Channel c.31:28 - Reserved.16.5.5 Channel DMA Interrupt Enable RegisterThis register is a read/write register and enables the completion of a DMA transfer to create an interrupt for DMA channel c(c = 0 to 27). Writing to a bit where a DMA channel is not implemented has no effect.Table 16-17: Channel DMA Interrupt Enable Register (CHNL_IRQ_ENABLE, address 0x4004 C088) bit descriptionBit Symbol Description Reset value27:0 CHNL_IRQ_ENABLE Enables the DMA done (dma_done[c]) signal to0x0create an interrupt. Write as:Bit[c] = 0: DMA done interrupt disabled for channel c.Bit[c] = 1: DMA done interrupt enabled for channel c.31:28 - Reserved. -258 www.xinnovatech.com

XN12L61216.6 Functional Description16.6.1 DMA Control SignalsThe DMA control signals for DMA transfers and for providing the handshake inside peripheral and memory transfers arelisted in the following table.Table 16-18: DMA control signalsSignal Name Source/ destination DescriptionDMAdma_req[c]Peripheral/The peripheral asserts dma_req[c] when it has one or more datachannelcontrollertransfers that require servicing. The controller services the request byrequestperforming the DMA cycle using 2 R DMA transfers with possiblearbitration between transfers depending on the setting of R_power. Thedma_req[c] signal stays HIGH until the transfer for channel c is complete.Then the request is deasserted. All peripherals wait for a transfer requestto clear before starting the next transfer.DMA singledma_sreq[c]Peripheral/The peripheral asserts dma_sreq when it has one data transfer thatchannelcontrollerrequires servicing. The controller services the request by performing therequestDMA cycle using one single DMA transfer. The dma_sreq[c] signal staysHIGH until the transfer for channel c is complete. Then the request isdeasserted. All peripherals wait for a transfer request to clear beforestarting the next transfer.16.6.2 DMA ArbitrationThe controller can be configured to perform arbitration during a DMA cycle before and after a programmable number oftransfers. This reduces the latency for servicing a higher priority channel. The controller uses four bits in the channel controldata structure that configure how many AHB bus transfers occur before the controller re-arbitrates. These bits are known asthe R_power bits because the value R is raised to the power of two and this determines the arbitration rate. For example, if R= 4 then the arbitration rate is 2 4 , that is, the controller arbitrates every 16 DMA transfers.Note: Do not assign a low-priority channel with a large R_power value because this prevents the controller from servicinghigh-priority requests until it re-arbitrates. When N > 2 R and is not an integer multiple of 2 R then the controller alwaysperforms sequences of 2 R transfers until N < 2 R remain to be transferred. The controller performs the remaining N transfers atthe end of the DMA cycle.16.6.3 DMA PriorityEach channel can be configured to use either the default priority level or a high priority level by setting theCHNL_PRIORITY_SET Register. When the controller arbitrates, it determines the next channel to service by using thefollowing information:• Priority level (default or high) assigned to the channelwww.xinnovatech.com 259

XN12L612• Channel number: Channel number zero has the highest priority and as the channel number increases, the priority of achannel decreases. The controller services all enabled channels with high priority first in increasing order of theirchannel number and then all channels with default priority.Table 16-19: DMA channel priorityChannel number Priority level setting Arbitration priority in descending order0 High Highest1 High Next highest... ... ...27 High ...0 Default ...1 Default ...... ... ...27 Default Lowest16.6.4 DMA Cycle TypesThe cycle_ctrl bits in the channel control data structure control how the DMA controller performs a cycle. The controller usesfour cycle types described in this manual:• Invalid• Basic• Single modeFor all cycle types, the controller arbitrates after 2 R DMA transfers. If a low-priority channel is set to a large 2 R value then itprevents all other channels from performing a DMA transfer until the low-priority DMA transfer completes. Therefore, theuser must take care when setting the R_power bit in the channel_cfg data structure, that the latency for high-prioritychannels is not significantly increased.Invalid CycleAfter the controller completes a DMA cycle, it sets the cycle type to invalid to prevent it from repeating the same DMA cycle.Basic CycleIn this mode, after the channel is enabled and the controller receives a request for this channel, the flow for the basic cycle isas follows:1. The controller performs 2R transfers. If the number of transfers remaining is zero the flow continues at step 3.2. The controller arbitrates:a) If a higher-priority channel is requesting service then the controller services that channel.b) If the peripheral or software signals a request to the controller then it continues at step 1.260 www.xinnovatech.com

XN12L6123. The controller sets dma_done[c] signal for this channel HIGH for one system clock cycle. This indicates to the hostprocessor that the DMA cycle is complete.Single Mode CycleIn this mode, after the channel is enabled and the controller receives a request for this channel, the flow for the basic cycle isas follows:1. The controller perform a single sample transfer. If the number of transfers remaining is zero the flow continues at step 3.2. The controller stop and wait for next dma_sreq. When next dma_sreq happened, then it continues at step 1.3. The controller sets dma_done[c] signal for this channel HIGH for one system clock cycle. This indicates to the hostprocessor that the DMA cycle is complete.16.6.5 DMA ControlThe controller uses the SRAM to enable it to access two pointers and the control information that it requires for each channel.The channel control information is contained in the channel control data structure, and the source and destination addressesfor the DMA transfer are defined by the source end and destination end pointers. The DMA channel control data structuremust be programmed in the device SRAM memory. The base address of the primary channel control data structure in SRAMmust be between 0x1000 0000 and 0x1000 3F00. The pointer to the base address of the channel control data structure isprogrammed in the CTRL_BASE_PTR register.Note: The user memory (SRAM) is not accessed by the DMA controller unless the channel is enabled and a transfer isstarted for this channel.1GBalternate channel 20...alternate channel 1alternate channel 0primary channel 20...primary channel 1primary channel 00x2A00x2B00x1700x1600x1500x1400x0200x0100x000unusedchannel control datadestination end pointersource end pointer0x00C0x0080x0040x000Figure 16-2: Memory map for DMA channel control data structurewww.xinnovatech.com 261

XN12L612Source Data End PointerThe src_data_end_ptr memory location contains a pointer to the end address of the source data. Before the controller canperform a DMA transfer, this memory location must be programmed with the end address of the source data. The controllerreads this memory location when it starts a 2 R DMA transfer. During a DMA transfer cycle, the controller counts down fromthe end address, and before each arbitration, the channel control data structure is updated with the number of remainingtransfers.Note: The controller does not write to this memory location.Table 16-20: src_data_end_ptr bit assignmentsBit Name Description31:0 src_data_end_ptr Pointer to the end address of the source dataDestination Data End PointerThe dst_data_end_ptr memory location contains a pointer to the end address of the destination data. Before the controllercan perform a DMA transfer, this memory location must be programmed with the end address of the destination data. Thecontroller reads this memory location when it starts a 2 R DMA transfer, and before each arbitration the channel control datastructure is updated with the number of remaining transfers.Note: The controller does not write to this memory location.Table 16-21: dst_data_end_ptr bit assignmentsBit Name Description31:0 dst_data_end_ptr Pointer to the end address of the destination data16.6.5.1 Control Data ConfigurationFor each DMA transfer, the channel_cfg memory location provides the control information for the controller. At the start of aDMA cycle, or 2 R DMA transfer, the controller fetches the channel_cfg word from SRAM memory. After the controllerperforms 2 R , or N, transfers, it stores the updated channel_cfg word in SRAM. The controller does not support a dst_sizevalue that is different from the src_size value. If the controller detects a mismatch in these values, it uses the src_size valuefor source and destination, and when it next updates the n_minus_1 field, it also sets the dst_size field to the same value asthe src_size field.After the controller completes the N transfers, it sets the cycle_ctrl field to 000 to indicate that the channel_cfg data is invalid.At this point, the channel configuration is overwritten in SRAM. This prevents the controller from repeating the same DMAtransfer.Note: The controller updates the channel control data structure in SRAM after each arbitration.262 www.xinnovatech.com

XN12L612Table 16-22: channel_cfg bit assignmentsBit Name Description2:0 cycle_ctrl The operating mode of the DMA cycle. The modes are:000: Stop. Indicates that the data structure is invalid.001: Basic. The controller must receive a new request, prior to it entering the arbitrationprocess, to enable the DMA cycle to complete.010 - 111: not used.3 reserved13:4 n_minus_1 Prior to the DMA cycle commencing, these bits represent the total number of DMA transfersthat the DMA cycle contains. These bits must be set according to the size of DMA cycle. The10-bit value indicates the number of DMA transfers, minus one. The possible values are:000000000 = 1 DMA transfer000000001 = 2 DMA transfers000000010 = 3 DMA transfers000000011 = 4 DMA transfers000000100 = 5 DMA transfers...111111111 = 1024 DMA transfers.The controller updates this field immediately prior to it entering the arbitration process. Thisenables the controller to store the number of outstanding DMA transfers that are necessary tocomplete the DMA cycle.17:14 R_power Set these bits to control how many DMA transfers can occur before the controller re-arbitrates.The possible arbitration rate settings are: 0000: Arbitrates after each DMA transfer.0001: Arbitrates after 2 DMA transfers.0010: Arbitrates after 4 DMA transfers.0011: Arbitrates after 8 DMA transfers.0100: Arbitrates after 16 DMA transfers.0101: Arbitrates after 32 DMA transfers.0110: Arbitrates after 64 DMA transfers.0111: Arbitrates after 128 DMA transfers.1000: Arbitrates after 256 DMA transfers.1001: Arbitrates after 512 DMA transfers.1010-1111: Arbitrates after 1024 DMA transfers. This means that no arbitration occurs duringthe DMA transfer because the maximum transfer size is 1024.23:18 - -25:24 src_size Set the bits to match the size of the source data:00 = byte01 = half-word10 = word11 = reservedwww.xinnovatech.com 263

XN12L61227:26 src_inc Set the bits to control the source address increment. The address increment depends on thesource data width as follows:Source data width = byte00 = byte.01 = half-word.10 = word.11 = no increment. Address remains set to the value that the src_data_end_ptr memorylocation contains.Source data width = half-word00 = reserved.01 = half-word.10 = word.11 = no increment. Address remains set to the value that the src_data_end_ptr memorylocation contains.Source data width = word00 = reserved.01 = reserved.10 = word.11 = no increment. Address remains set to the value that the src_data_end_ptr memorylocation contains.29:28 dst_size Destination data size. Must be set to the same value as source data size.31:30 dst_inc Destination address increment. The address increment depends on the source data width asfollows:Source data width = byte00 = byte.01 = half-word.10 = word.11 = no increment. Address remains set to the value that the dst_data_end_ptr memorylocation contains.Source data width = half-word00 = reserved.01 = half-word.10 = word.11 = no increment. Address remains set to the value that the dst_data_end_ptr memorylocation contains.Source data width = word00 = reserved.01 = reserved.10 = word.11 = no increment. Address remains set to the value that the dst_data_end_ptr memorylocation contains.264 www.xinnovatech.com

XN12L61217 Flash/SRAM memory and ISP/IAP FunctionsXN12L612 has 88 KB flash and 16 KB SRAM for user application. The flash supports both In-System-Programming (ISP)and In-Application-Programming (IAP). The user can call ISP/IAP functions via Xinnova XN12L612 bootloader interface.XN12L612 also provides 128-bit password for configurable A/B area memory security mechanism.17.1 Flash/Boot ROM Organization and Access SpeedXN12L612 flash sector size is 1K bytes and total up to 88 sectors resided in flash memory. The user flash start address ismapped to 0x0.The boot ROM is 8KB size and used to store MCU bootloader. The boot loader start address is mapped to 0x1FFF0000.Reserved0x1FFF 20000x1FFF 0000Boot LoaderReserved0x0001 60000x0001 5FFF0x0001 5C00Sector 87User App.0x0000 08000x0000 04000x0000 0000Sector 1Sector 0Figure 17-1: User application code and system boot loader mapping diagramTo speed up flash memory access and lowest cost to achieve system highest performance, XN12L612 implements MemoryAcceleration Module(MAM) to take flash 64bits data bus advantage.www.xinnovatech.com 265

XN12L612Flash ControlAddressAddressM0 Core32bits Data BusMAM64bits Data BusOn Chip FlashRdy/BsyFigure 17-2: Memory Acceleration Module (MAM) diagram17.2 Flash Configuration/Control RegisterTable 17-1: Flash IAP registers summary ( base address: 0x5006 0000)Symbol Offset Access Description Reset Value~ 0x00~0x24 ~ ReservedFLASH_RDCYC 0x28 R/W Flash read cycle 0x0000 0000DID 0x2C RO Chip Device ID data. 0xxxxx xxxxVERID 0x30 RO Chip Version ID data. 0xxxxx xxxxUNIQUEID 0x34 RO Chip Unique ID data. 0xxxxx xxxx17.2.1 Flash Access Cycle RegisterDepending on the system clock frequency, access to the flash memory can be configured with various access times bywriting to the FLASH_RDCYC register.Table 14-2: Flash Access Cycle Register (FLASH_RDCYC, address 0x5006 0028) bit descriptionBit Symbol Value Description Reset value1:0 CYCLES Flash read cycle time 0000 One cycle time when system clock frequency is less than 30MHz.01 Two cycles time when system clock frequency is between 30MHz and60MHz.10 Three cycles time Two cycles time when system clock frequency isbetween 60MHz and 90MHz.11 Four cycles time Two cycles time when system clock frequency isgreater than 90MHz31:2 - - - 0x017.2.2 Device ID RegisterTable 14-3: Device ID Register (DID, address 0x5006 002C) bit descriptionBit Symbol Description Reset value266 www.xinnovatech.com

XN12L61215:0 DID Microcontroller device ID 0x126C31:16 MID Microcontroller manufacture ID 0x00BA17.2.3 Device Hardware Version RegisterTable 14-4: Device Version ID Register (VERID, address 0x5006 0030) bit descriptionBit Symbol Description Reset value15:0 MINOR Microcontroller hardware minor version Device dependent31:16 MAJOR Microcontroller hardware major version Device dependent17.2.4 Device Unique Serial No RegisterTable 117-5: Device Unique ID Register (UNIQUEID, address 0x5006 0034) bit descriptionBit Symbol Description Reset value31:0 SID Device unique serial no. Device dependent17.3 Flash Memory SecurityXN12L612 offers 128 bits password security feature to prevent unauthorized users from writing/reading the contents of theflash memory array. Further, the user application memory, flash and SRAM, can be configurable to two areas and protectedby different 128 bits password.0x0001 5FFFFlash Memory(88KB)0x10003000SRAM(16KB)Access Control byB AreaB AreaPassword B (128 bits)0x000x xxxx0x1000 xxxxOpen AreaA Area0x1000 0000Password A (128 bits)0x0000 0000Figure 17-3: Password security mechanismAs described in Figure 17-3, A area and B area memory access via SWD, software are controlled by 128 bits A and B password infollowing rules under password protection:1. Software running on B area is able to read A/B/open area and write B area/open area.2. Software running on A area is able to call function that is stored in B area, but no read/write.3. Software running on A area is able to read/write A and open area.4. No SWD.www.xinnovatech.com 267

XN12L612The password scheme allows user to split both flash and SRAM memory to two segments area and protect by different A, Bpassword. By default, the whole user flash memory is reserved to memory A and protect by A password. The user can onlyset B segment area start address once via ISP/IAP command. If the B segment start address is set for flash/SRAM memory,the user must do power down and up to active setting, and no further change any more. See detail for ISP/IAP command.Note: The user must reserve 2K SRAM size for open area. And the start address must be in flash sector boundary.17.3.1 Enable Password ProtectionAll set up changing (except password verification) related to password protection must be active by chip POR reset(powerdown and up). Software reset and hardware reset will not infect to password protection status.17.3.2 Protection SummaryTable 17-2: A area protection functionMemory Access Operation ProtectionRead Software running in B/A/open area and ISP read A area Operation OKSWD read A area Operation Prohibited, SWD isdisabledFlash erase/programRead A area via DMASoftware running in B/A/open area and ISP write A areaOperation OKOperation Prohibitedand RAM writeSWD write A area Operation Prohibited, SWD isdisabledExecute Call function stored in A area Operation OKTable 17-3: B area protection functionMemory Access Operation ProtectionRead Software running in B read B area Operation OKSoftware running in A/open area read B areaOperation ProhibitedSWD read B area Operation Prohibited, SWD isdisabledFlash erase/programand RAM writeISP read B areaRead B area via DMASoftware running in B/A/open area and ISP/IAP erase/program B areaflashSoftware running in B area write B area SRAMSWD write A areaWrite B area SRAM via DMAOperation ProhibitedOperation ProhibitedOperation ProhibitedOperation OKOperation Prohibited, SWD isdisabledOperation ProhibitedExecute Call function stored in B area Operation OK268 www.xinnovatech.com

XN12L61217.4 ISP Protocol and CommandThe ISP Protocol describes the communication protocol in software level between host and XN series MCU via URAT0.• For UART data format, default setup are: 1 start bit, 8data bits, 1 stop bit, no parity and no flow control.The software Protocol applies binary data format to achieve higher communication performance. The command/data framestructure is as follows:Command frame structure:Frame Head(two bytes 0x55AA)Length(one byte)Type(one byte)Command(one byte)Status(one byte)Serial No(2 Bytes)Parameters(if any, multiple by 4 bytes)CRC16Data frame structure:Data(if any, multiple by 4 bytes)CRC16Figure 17-4: ISP communication frame structure• Frame head: Start flag of frame. two bytes, value: 0x55AA• Frame length: one byte. From Frame Head to CRC• Frame type: 1- Request; 0- Answer.• Command: See command table.• Status: value 0, command executed successful. None zero value means error code.• Serial No: Two bytes frame sequence no.• Parameters/Data string: see detail in each command.• CRC: 2 bytes CRC16(seed:0xFFFF) value of frame.17.4.1 ISP Command ListISP commands are categorized to four types: Memory command, Interface command, Status Access command andmiscellaneous command. ISP command is one byte data. The high 4-bits represents command type and low 4-bits is usedfor command code. The command type code is listed as the following:• Memory Related Command: #01H• Status Related Command: #03H• miscellaneous: #04HTable 17-4: ISP command code listCommand Type Command CommandCommandNo ofLength ofDataCodeParameterParameterMemory Sector Erase #01H #11H 2 8 NoSector blank check #02H #12H 2 8 NoWrite data to SRAM #04H #14H 2 8 YesCopy data from SRAM to flash #05H #15H 3 12 NoCompare two memory area data #06H #16H 3 12 NoRead memory data #07H #17H 2 8 NoChip Erase #08H #18H 0 0 Nowww.xinnovatech.com 269

XN12L612Status Read device ID #01H #31H 0 0 NoRead Boot Loader Version #02H #32H 0 0 NoMiscellaneous Jump and run user specific address code #02H #42H 0 0 NoVerify password #0AH #4AH 1 16 NoSet new password #0BH #4BH 2 32 NoSet B boundary #0CH #4CH 2 20 No17.4.2 Command Return CodeWhen ISP communication frame is received, the ISP command will be executed and the result of execution is return. If erroroccurs, the following error type will be returned in high 4-bits return command:Frame error: #08HCommand error: #09HParameter Error:Data Error:#0AH#0BHTable 17-5: Return command list when ISP commands execute successfullyCommandCommandCommandReturnNo ofLength ofDataTypeCodeCommandParameterParameterSector Erase #11H #11H 0 0 NoSector blank check #12H #12H 0 0 NoWrite data to SRAM #14H #14H 0 0 NoMemoryCopy data from SRAM to flash #15H #15H 0 0 NoCompare two memory area data #16H #16H 0 0 NoRead memory data #17H #17H CommanddependsCommanddependsNoChip Erase #18H #18H 0 0 NoStatusRead device ID #31H #31H 3 12 NoRead Boot Loader Version #32H #32H 2 8 Nomiscellaneous Jump and run user specific address code #42H #42H 0 0 NoVerify password #4AH #4AH 0 0 NoSet new password #4BH #4BH 0 0 NoSet B boundary #4CH #4CH 0 0 NoTable 17-6: ISP error code listCommand Type Command CommandReturnNo ofLength ofDataCodeCommandParameterParameterFrame Error Frame head error #01H #81H 0 0 NoFrame time out #02H #82H 0 0 NoFrame serial no error #03H #83H 0 0 NoFrame CRC error #04H #84H 0 0 No270 www.xinnovatech.com

XN12L612Command Error Invalid command #01H #91H 0 0 NoFlash busy #02H #92H 0 0 NoFlash operation failure #03H #93H 1 4 NoParameter Error Parameter 1 error #01H #A1H 0 0 NoParameter 2 error #02H #A2H 0 0 NoParameter 3 error #03H #A3H 0 0 NoData Error Missing data #01H #B1H 0 0 No17.4.2.1 Erase Sector(s)Command: 0x11HParameters:Start Sector AddressEnd Sector Address– Start Sector address: Flash address 0~Max flash address– End Sector address: Start Sector address ~ Max flash addressReturn Code: 0x11HParameters:If erase failed ,Return error address17.4.3 Sector Blank CheckCommand: 0x12HParameters:Start AddressEnd Address– Start Address: Flash address 0 ~ Max flash address– End Address: Start Sector address ~ Max flash addressReturn Code: 0x12HParameters:If blank check failed ,Return error address17.4.3.1 Write Data to RAM Memory1.Command: 0x14HParameters:Start AddressNumber of Data– Start Address : SRAM address=0x10000400– Number of Data: 0~1024 bytes2.Return Code: 0x14H with Status value equal 0xFF3.Data string:www.xinnovatech.com 271

XN12L612Number of Data String4.Return Code: 0x14H with Status value equal 0x0017.4.3.2 Copy RAM Data to FlashCommand: 0x15HParameters:Flash Address(32bits) SRAM Address(32bits) Number of bytes(32bits)– Flash Address : Destination flash address– SRAM Address: Source SRAM Address=0x10000400– Number of Bytes: Number of data to be copied to flashReturn Code: 0x15HParameters:If flash program failed ,Return error address17.4.3.3 Compare Memory DataCommand: 0x16HParameters:DST Address(32bits) SRC Address(32bits) Number of bytes(32bits)– DST Address: Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.– SRC Address Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.– Number of Bytes: Number of bytes to be compared; should be a multiple of 4.Return: 0x16HParameters:If memory compare failed ,Return error address17.4.3.4 Read Data from MemoryCommand: 0x17HParameters:Address(32bits)Number of bytes(32bits)– Address : Memory address– Number of Bytes: Number of data to be readReturn: 0x17HParameters:Data String– Data String: Data read from MCU272 www.xinnovatech.com

XN12L61217.4.3.5 Chip EraseCommand: 0x18HReturn: 0x18HIf flash program failed ,Return error address17.4.3.6 Retrieve Device IDCommand: 0x31HReturn Code: 0x31HParameters:Chip ID(32bits) Chip Version(32bits) Unique Serial No(32bites) Flash Size(32bits) SRAM Size(32bites)– Chip ID: 16 bits Manufacture ID + 16 bits Device ID– Chip Version: Chip mask version– Unique Serial No.: 32bits– Flash Size: size in byte– SRAM Size: size in byte17.4.3.7 Retrieve BSL VersionCommand: 0x32HReturn Code: 0x32HMajor Version(16bits) Minor Version(16bits) Date and Time(32bits)Major Version: 1~255Minor Version:1~255Date and Time: Seconds since 197017.4.3.8 Run Specific Address CodeCommand: 0x42HMemory AddressVector Table Type– Memory Address: Flash or RAM address from which the code execution is to be started. This address should be on aword boundary.– Vector Table Type: 0: Flash; 1: Boot LoaderReturn Code: 0x42H17.4.3.9 Password VerificationCommand: 0x4AHwww.xinnovatech.com 273

XN12L612Parameters:AB Selection(32bits)Password(128bits)– AB Selection: 0: A; 1: B.– Password: 128bits password stringReturn Code: 0x4AHParameters:AB Selection(32bits)17.4.3.10 Set New PasswordCommand: 0x4BHParameters:AB Selection(32bits) Old Password(128bits) New Password(128bits)– AB Selection: 0: A; 1: B.– Old Password: 128bits password string– New Password: 128bits password stringReturn Code: 0x4BHParameters:AB Selection(32bits)17.4.3.11 Set B BoundaryCommand: 0x4CHParameters:AB Selection(32bits) Password(128bits) Flash Boundary(32bits) SRAM Boundary(32bits)– AB Selection: equal 1– Password: 128bits password string– Flash Boundary: 32bits boundary address– SRAM Boundary: 32bits boundary addressReturn Code: 0x4CHParameters:AB Selection(32bits)17.4.3.12 Password StatusCommand: 0x4DHReturn Code: 0x4DHParameters:274 www.xinnovatech.com

XN12L612Password A Status (32bits) Password B Status (32bits) B Area Flash Boundary(32bits) B Ares SRAM Boundary(32bits)– Password A Status: 0: Unlocked; None zero: Locked– Password B Status: 0: Unlocked; None zero: Locked– Flash Boundary: 32bits boundary address– SRAM Boundary: 32bits boundary address17.5 IAP Command and Entry AddressThe BSL implements all IAP command functions and reserves an entry address (0x1FFF 1000) in thumb code for userapplication to call. The register R0 is used to pass a pointer parameter pointing memory (RAM) containing command codeand parameters. The result of the IAP command is returned in the result table pointed to by register r1. The user can reusethe command table for result by passing the same pointer in registers r0 and r1. The parameter table should be big enoughto hold all the results in case if number of results is more than number of parameters. Parameter passing is illustrated in thefollowing IAP command table. The number of parameters and results vary according to the IAP command.COMMAND CODEPARAMETER 1commandparameter tablePARAMETER 2ARM REGISTER r0ARM REGISTER r1PARAMETER nSTATUS CODERESULT 1commandresult tableRESULT 2RESULT nFigure 17-5: IAP parameter passingThe IAP function could be called in the following way using C.Define the IAP location entry point. Since the 0th bit of the IAP location is set there will be a change to Thumb instruction setwhen the program counter branches to this address.#define IAP_LOCATION 0x1fff1001Define data structure or pointers to pass IAP command table and result table to the IAP function:unsigned long command[10];unsigned long result[5];orunsigned long * command;www.xinnovatech.com 275

XN12L612unsigned long * result;command=(unsigned long *) 0x……result= (unsigned long *) 0x……Define pointer to function type, which takes two parameters and returns void. Note the IAP returns the result with the baseaddress of the table residing in R1.typedef void (*IAP)(unsigned int [],unsigned int[]);IAP iap_entry;Setting function pointer:iap_entry=(IAP) IAP_LOCATION;Whenever you wish to call IAP you could use the following statement.iap_entry (command, result);Table 17-7: IAP command listIAPRegister R0 PointingRegister R1 PointingCommanCommandParameterParameterParameter3~6 Parameter5~9 StatusResult1 Result2 Result3 Result4dCode12CodeRead BSLVersion0x11 - - - - Status Major&MinorDateTime - -Erase0x15Sector- - - Status - - - -sectorAddressProgram 0x31 Address Data - - Status - - - -Verify0x4AA/B128 bit password - Status - - - -passwordselectionSet new0x4BA/BOld passwordNewStatus - - - -passwordselectionpasswordSet B0x4CA/BPassword B boundary Status FlashSRAM- -boundaryselectionBoundarBoundaryy SetupSetupStatusStatusPassword0x4D Status ABB FlashB SRAMStatusPassworPasswordBoundaryBoundaryd statusstatusStatus code list of IAP execution:1. CMD_SUCC 0x002. INVALID_ADDR 0x013. ERASE_FAILED 0x024. PROG_FAILED 0x035. NOT_BLANK 0x04276 www.xinnovatech.com

XN12L6126. INVALID_CMD 0x057. INVALID_PWD 0x068. IRC_NOT_POWERED 0x07www.xinnovatech.com 277

XN12L61218 SWD18.1 General DescriptionXN12L612 provides SWD interface which supports standard ARM Serial Wire Debug mode. It allows:• Direct debug access to all memories, registers, and peripherals.• No target resources are required for the debugging session.• Four breakpoints. Four instruction breakpoints, which can also be used to remap instruction addresses for code patches.Two data comparators which can be used to remap addresses for patches to literal values.• Two data watch points, which can also be used as trace triggers.18.2 Pin DescriptionTable 18-1: Serial Wire Debug pin descriptionPin Name Type DescriptionSWCLK Input Serial Wire Clock. This pin is the clock for debug logic when in the Serial Wire Debug mode(SWDCLK).SWDIO Input / Output Serial wire debug data input/output. The SWDIO pin is used by an external debug tool tocommunicate with and control the ARM Cortex-M0 CPU.18.3 Debug OperationSWD pins share pin with other function pin. However, the pins is set default as SWD function when power up. To use thosepin in user application, user must do pin configuration.SWD debug function works only when the user code protection is not active. To enable code protected device, user musterase chip first to remove code protection.The following diagram shows SWD connection to device:XN12L612signals from SWD connectorSWDIOSWCLKnSRSTGNDGndSWDIOSWCLKRESET#PIO0_12ISP entryFigure 18-1: Connecting the SWD pins to a standard SWD connector278 www.xinnovatech.com

XN12L61219 Revision HistoryRevision Description Date1.0 Initial Release. Apr. 20121.1 Revised ADC, ISP/IAP sections. Aug. 2012www.xinnovatech.com 279