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XN62Lxxx 

32 

IC 

ARM + xDSP , 88K Flash,16K RAM 

 

1 

1.1 

XN62L ARM Cortex M0 32 

ARM+xDSP 

100MHz xDSP 32 CORDIC 

 

24 

PWM 

 

ARM XN62L 

XN62L 

12 ADC1210 DAC 2 

 

UART SPI/QSPI TWS 

WDT 4 / 

32 RTC 1% 

 

55 

1.2 

• ARM + xDSP 

• 100Mhz ARM Cortex-M0 

• xDSP 32CRCSin 

CosArctan 

• 88KB Flash 16KB SRAM 

• DMA 

• Serial Wire Debug (SWD) 

• 

PWM 

• 3 PWM 

• 2 4PWM 

• 

• 

• PWMADC 

• 

• 21282 

 

• 

• 

• 

bootloader 

• F lashIn -System-Program (ISP) In-Application-Program (IAP) 

• 

ª 2010 Xinnova Technology Ltd. All rights reserved. The Xinnova logo is ed trademarks of Xinnova Technology Ltd. This Datasheet may be 

 

revised by subsequent versions or modifications without prior notice.

XN62Lxxx 

– 

0.5MHz 16MHz 

– 1% 20MHz 

– PLL 100MHz 

– 32K (RTC) 

• 

/ 

– 2 16 / 2 32 / 

– / / 

– 

AB 

• 

– 3 12 1MHz ADC 12 

– 10 DAC1MHz 

– 2 

– -40°C ~ +120°C 

• 

– 4 

UART – SP Iflash 

QSPI 

– TWS 

• / 

– 55 / 

• 

– 

– 12 

– 

– BOD 

 

– POR 

– PMU 

• 

– (-40°C ~ +85°C) 

• 

• 3.3 V 

• 64 48 

LQFP 

2 www.xinnovatech.com

XN62Lxxx 

2 

 

. 

Flash 

(bytes) 

SRAM 

(bytes) 

RTC 

UART 

SPI/ 

QSPI 

TWS ADC PWM DAC 

 

DMA °C 

 

 

CRC 

 

32- 

CORDIC PMU PLL T/C GPIO 

 

XN62L912 88K 16K √ 4 2 1 

12ch 

ADC0,1,2 

22ch 

PWM0,1,2 

8fault 

√ 2 √ √ √ √ √ √ √ √ 4 

55 

GPIO0,1,2 

XN62L408 64K 12K √ 4 2 1 

8ch 

ADC0,1 

14ch 

PWM0,1 

8fault 

√ 2 √ √ √ √ √ √ √ √ 4 

39 

GPIO0,1 

www.xinnovatech.com 3

XN62Lxxx 

3 

3.1 

XN62L LQFP 64 LQFP 48 

IO 

 


XN62Lxxx 

www.xinnovatech.com 5 

3.2 LQFP 64 

(XN62L912) 

LQFP64 

PIO0_23/ACMP1_I0/CT32B1_CAP0/CT32B1_MAT0/PWM_FAULT2 

16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

5 

6 

4 

3 

1 

2 

PIO0_17/MOSI/RXD3 

PIO0_16/MISO/CT16B1_CAP1/CT16B1_MAT1/TXD3 

PIO0_15/SSEL/CT16B1_CAP0/CT16B1_MAT0/RXD2 

VDD(IO) 

PIO2_11/CT32B1_CAP3/CT32B1_MAT3/RXD1/AD11 

PIO2_10/CT32B1_CAP2/CT32B1_MAT2/TXD1/AD10 

PIO2_9/CT32B1_CAP1/CT32B1_MAT1/PWM2_7/AD9 

PIO2_8/CT32B1_CAP0/CT32B1_MAT0/PWM2_6/AD8 

VDD(3V3) 

PIO1_5/AD7/CT16B1_CAP0/CT16B1_MAT0 

VSS 

RTCXOUT 

PIO1_6/CT16B1_CAP1/CT16B1_MAT1/PWM_FAULT1 

PIO1_4/AD6/PWM0_5/PWM1_5 

VSSIO 

PIO1_3/AD5 

PIO1_2/SWDIO/AD4 

R/PIO1_1/AD3/PWM0_4/PWM1_4 

RTCXIN 

49 

50 

51 

52 

53 

54 

55 

56 

57 

58 

60 59 

61 

62 

64 63 

R/PIO0_31/AD1/PWM1_7 

R/PIO0_30/AD0 

PIO0_18/SWCLK/CT32B0_CAP0/CT32B0_MAT0 

PIO0_14/SCK/TXD2/CLKOUT 

RESET/PIO0_13/WAKEUP 

PIO0_12/CLKOUT/CT16B0_CAP1/CT16B0_MAT1/PWM1_6 

PIO0_11/SDA/CT16B0_CAP0/CT16B0_MAT0 

PIO0_10/SCL 

R/PIO1_0/AD2 

PIO2_7/CT32B0_CAP3/CT32B0_MAT3/PWM2_5/RXD2 

PIO2_6/CT32B0_CAP2/CT32B0_MAT2/PWM2_4/TXD2 

PIO2_5/CT32B0_CAP1/CT32B0_MAT1/PWM1_5 


33 

34 

35 

36 

37 

38 

39 

40 

41 

42 

44 

43 

45 

46 

48 

47 


PIO0_0/PWM0_0/QSPI_CS 

PIO0_1/RXD0/CT32B0_CAP0/CT32B0_MAT0 

PIO0_2/TXD0/CT32B0_CAP1/CT32B0_MAT1 

PIO0_3/CT32B0_CAP2/CT32B0_MAT2/PWM0_1/PWM1_4/QSPI_CLK 

PIO0_4/CT32B0_CAP3/CT32B0_MAT3/PWM0_2/PWM1_5/QSPI_WP 

PIO0_5/PWM0_3/QSPI_HOLD 

PIO0_6/CT32B1_CAP0/CT32B1_MAT0/PWM0_4/PWM1_2/QSPI_DI 

PIO0_7/CT32B1_CAP1/CT32B1_MAT1/PWM0_5/PWM1_3/QSPI_DO 

PIO0_8/RXD1/CT32B1_CAP2/CT32B1_MAT2/PWM0_6 

PIO0_9/TXD1/CT32B1_CAP3/CT32B1_MAT3/PWM0_7 

PIO0_28/ACMP1_O/DA0/CT16B0_CAP0/CT16B0_MAT0 


PIO2_1/CT16B0_CAP1/CT16B0_MAT1/RXD0/PWM_FAULT2/PWM1_1 

PIO2_2/CT16B1_CAP0/CT16B1_MAT0/TXD0/PWM_FAULT3/PWM1_2 


32 

31 

30 

29 

28 

27 

26 

25 

24 

23 

21 22 

20 

19 

17 18 

XTALOUT 

VREF_ADC 

PIO0_19/ACMP0_I0/CT32B0_CAP1/CT32B0_MAT1 


PIO0_21/ACMP0_I2/CT32B0_CAP3/CT32B0_MAT3/PWM1_0 

PIO0_22/ACMP0_I3/PWM1_1 


SWDIO/ACMP1_I2/CT32B1_CAP2/CT32B1_MAT2/PIO0_25 

SWCLK/ACMP1_I3/CT32B1_CAP3/CT32B1_MAT3/PIO0_26 

PIO0_27/ACMP0_O/DA0/PWM_FAULT0 

XTALIN 

PIO2_12/RXD1/PWM2_0 

PIO2_13/TXD1/PWM2_1 

PIO2_14/PWM2_2/TXD3 

PIO2_15/PWM2_3/RXD3

XN62Lxxx 

3.3 LQFP 48 (XN62L408) 

VSSIO 

VDD(IO) 

RTCXIN 

RTCXOUT 

VDD(3V3) 

VSS 

PIO1_6/CT16B1_CAP1/CT16B1_MAT1/PWM_FAULT1 

PIO1_5/AD7/CT16B1_CAP0/CT16B1_MAT0 

PIO1_4/AD6/PWM0_5/PWM1_5 

PIO1_3/AD5 

PIO1_2/SWDIO/AD4 

R/PIO1_1/AD3/PWM0_4/PWM1_4 

48 47 46 45 44 43 42 41 40 39 38 37 

XTALIN 

1 

36 

R/PIO1_0/AD2 

XTALOUT 

2 

35 

R/PIO0_31/AD1/PWM1_7 

VREF_CMP 

3 

34 

R/PIO0_30/AD0 


4 

33 

PIO0_18/SWCLK/CT32B0_CAP0/CT32B0_MAT0 


5 

32 

PIO0_17/MOSI/RXD3 

PIO0_21/ACMP0_I2/CT32B0_CAP3/CT32B0_MAT3/PWM1_0 

PIO0_22/ACMP0_I3/PWM1_1 

6 

7 

QFP48 

31 

30 

PIO0_16/MISO/CT16B1_CAP1/CT16B1_MAT1/TXD3 

PIO0_15/SSEL/CT16B1_CAP0/CT16B1_MAT0/RXD2 


8 

29 

PIO0_14/SCK/TXD2/CLKOUT 


9 

28 

RESET/PIO0_13/WAKEUP 

SWDIO/ACMP1_I2/CT32B1_CAP2/CT32B1_MAT2/PIO0_25 

10 

27 

PIO0_12/CLKOUT/CT16B0_CAP1/CT16B0_MAT1/PWM1_6 

SWCLK/ACMP1_I3/CT32B1_CAP3/CT32B1_MAT3/PIO0_26 

11 

26 

PIO0_11/SDA/CT16B0_CAP0/CT16B0_MAT0 

PIO0_27/ACMP0_O/DA0/PWM_FAULT0 

12 

13 14 15 16 17 18 19 20 21 22 23 24 

25 

PIO0_10/SCL 

PIO0_28/ACMP1_O/DA0/CT16B0_CAP0/CT16B0_MAT0 


PIO0_0/PWM0_0/QSPI_CS 

PIO0_1/RXD0/CT32B0_CAP0/CT32B0_MAT0 

PIO0_2/TXD0/CT32B0_CAP1/CT32B0_MAT1 

PIO0_3/CT32B0_CAP2/CT32B0_MAT2/PWM0_1/PWM1_4/QSPI_CLK 

PIO0_4/CT32B0_CAP3/CT32B0_MAT3/PWM0_2/PWM1_5/QSPI_WP 

PIO0_5/PWM0_3/QSPI_HOLD 

PIO0_6/CT32B1_CAP0/CT32B1_MAT0/PWM0_4/PWM1_2/QSPI_DI 

PIO0_7/CT32B1_CAP1/CT32B1_MAT1/PWM0_5/PWM1_3/QSPI_DO 

PIO0_8/RXD1/CT32B1_CAP2/CT32B1_MAT2/PWM0_6 

PIO0_9/TXD1/CT32B1_CAP3/CT32B1_MAT3/PWM0_7 


XN62Lxxx 

3.4 

Table 3-1: 

 

QFP64 

QFP48 

 

 

 

 

 

PIO0_0/ 

PWM0_0/ 

QSPI_CS 

PIO0_1/ 

RXD0/ 

CT32B0_CAP0/ 

CT32B0_MAT0 

PIO0_2/ 

TXD0/ 

CT32B0_CAP1/ 

CT32B0_MAT1 

PIO0_3/ 

CT32B0_CAP2/ 

CT32B0_MAT2/ 

PWM0_1/ 

PWM1_4/ 

QSPI_CLK 

PIO0_4/ 

CT32B0_CAP3/ 

CT32B0_MAT3/ 

PWM0_2/ 

PWM1_5/ 

QSPI_WP 

PIO0_5/ 

PWM0_3/ 

QSPI_HOLD 

PIO0_6/ 

CT32B1_CAP0/ 

CT32B1_MAT0/ 

PWM0_4/ 

PWM1_2/ 

QSPI_DI 

PIO0_7/ 

CT32B1_CAP1/ 

19 15 yes I/O I; PU PIO0_0 —/ 

- O - PWM0_0 — PWM 0 , 0 

- O - QSPI_CS —QSPI 

20 16 yes I/O I; PU PIO0_1 —/ 

- I - RXD0 —UART0 

- I - CT32B0_CAP0 —32 0 

0 

- O - CT32B0_MAT0 — 32 0 

0 

21 17 yes I/O I; PU PIO0_2 — 

/ 

- O - TXD0 —UART0 

- I - CT32B0_CAP1 —32 0 

1 

- O - CT32B0_MAT1 —32 0 

1 

22 18 yes I/O I; PU PIO0_3 — 

/ . 

- I - CT32B0_CAP2 —32 0 

2 

- O - CT32B0_MAT2 —32 0 

2 

- O - PWM0_1 — PWM 0 , 1 

- O - PWM1_4 — PWM 1 , 4 

- O - QSPI_CLK —QSPI 

23 19 yes I/O I; PU PIO0_4 — 

/ 

- I - CT32B0_CAP3 —32 0 

3 

- O - CT32B0_MAT3 —32 0 

3 

- O - PWM0_2 — PWM 0 , 2 

- O - PWM1_5 — PWM 1 , 5 

- I/O - QSPI_WP —QSPI IO2 

24 20 yes I/O I; PU PIO0_5 — 

/ 

- O - PWM0_3 — PWM 0 , 3 

- I/O - QSPI_HOLD —QSPI IO3 

25 21 yes I/O I; PU PIO0_6 — 

/ 

- I - CT32B1_CAP0 —32 1 

0 

- O - CT32B1_MAT0 —32 1 

0 

- O - PWM0_4 — PWM 0 , 4 

- O - PWM1_2 — PWM 1 , 2 

- I/O - QSPIDI —QSPI 

IO0 

26 22 yes I/O I; PU PIO0_7 — 

/ 

- I - CT32B1_CAP1 —32 1 

1 


XN62Lxxx 

 

QFP64 

QFP48 

 

 

 

 

 

CT32B1_MAT1/ 

PWM0_5/ 

PWM1_3/ 

QSPI_DO 

PIO0_8/ 

RXD1/ 

CT32B1_CAP2/ 

CT32B1_MAT2/ 

PWM0_6 

PIO0_9/ 

TXD1/ 

CT32B1_CAP3/ 

CT32B1_MAT3/ 

PWM0_7 

PIO0_10/ 

SCL 

PIO0_11/ 

SDA/ 

CT16B0_CAP0/ 

CT16B0_MAT0 

PIO0_12/ 

CLKOUT/ 

CT16B0_CAP1/ 

CT16B0_MAT1 

PWM1_6 

RESET/ 

PIO0_13/ 

WAKEUP 

PIO0_14/ 

SCK/ 

CLKOUT/ 

TXD2 

PIO0_15/ 

SSEL/ 

CT16B1_CAP0/ 

CT16B1_MAT0/ 

RXD2 

- O - CT32B1_MAT1 —32 1 

1 

- O - PWM0_5 — PWM 0 , 5 

- O - PWM1_3 — PWM 1 , 3 

- I/O - QSPI_DO —QSPI IO1 

27 23 yes I/O I; PU PIO0_8 — 

/ 


- I - CT32B1_CAP2 —32 1 

2 

- O - CT32B1_MAT2 —32 1 

2 

- O - PWM0_6 — PWM 0 , 6 

28 24 yes I/O I; PU PIO0_9 — 

/ 


- I - CT32B1_CAP3 —32 1 

3 

- O - CT32B1_MAT3 —32 1 

3 

- O - PWM0_7 — PWM 0 , 7 

37 25 yes I/O I; IA PIO0_10 — 

/ 

- I/O - SCL —TWS / 

38 26 yes I/O I; IA PIO0_11 — 

/ 

- I/O - SDA —TWS 

/ 

- I - CT16B0_CAP0 —16 0 

0 

- O - CT16B0_MAT0 —16 0 

0 

39 27 - I/O I; PU PIO0_12 — 

/ 

- O - CLKOUT — 

- I - CT16B0_CAP1 —16 0 

1 

- O - CT16B0_MAT1 —16 0 

1 

- O - PWM1_6 — PWM 1 , 6 

40 28 - I I; PU RESET — 

- I/O - PIO0_13 — 

/ 

- I - WAKEUP — 

41 29 - I/O I; PU PIO0_14 — 

/ 

- I/O - SCK —SPI 

- O - CLKOUT — 


42 30 - I/O I; PU PIO0_15 — 

/ 

- I/O - SSEL — SPI 

- I - CT16B1_CAP0 —16 1 

0 

- O - CT16B1_MAT0 —16 1 

0 


PIO0_16/ 43 31 - I/O I; PU PIO0_16 — 

/ 


XN62Lxxx 

 

QFP64 

QFP48 

 

 

 

 

 

MISO/ 

CT16B1_CAP1/ 

CT16B1_MAT1/ 

TXD3 

PIO0_17/ 

MOSI/ 

RXD3 

PIO0_18/ 

SWCLK/ 

CT32B0_CAP0/ 

CT32B0_MAT0 

PIO0_19/ 

ACMP0_I0/ 

CT32B0_CAP1/ 

CT32B0_MAT1 

PIO0_20/ 

ACMP0_I1/ 

CT32B0_CAP2/ 

CT32B0_MAT2 

PIO0_21/ 

ACMP0_I2/ 

CT32B0_CAP3/ 

CT32B0_MAT3 

PIO0_22/ 

ACMP0_I3 

PIO0_23/ 

ACMP1_I0/ 

CT32B1_CAP0/ 

CT32B1_MAT0 

PIO0_24/ 

ACMP1_I1/ 

CT32B1_CAP1/ 

CT32B1_MAT1 

SWDIO/ 

ACMP1_I2/ 

CT32B1_CAP2/ 

CT32B1_MAT2/ 

PIO0_25 

- I/O - MISO — SPI 

- I - CT16B1_CAP1 —16 1 

1 

- O - CT16B1_MAT1 —16 1 

1 


44 32 - I/O I; PU PIO0_17 — 

/ 

- I/O - MOSI —SPI 


45 33 - I/O I; PU PIO0_18 — 

/ 

- I - SWCLK — SWD 

- I - CT32B0_CAP0 —32 0 

0 

- O - CT32B0_MAT0 —32 0 

0 

4 4 - I/O I; PU PIO0_19 — 

/ 

- I - ACMP0_I0 — 0 0 

- I - CT32B0_CAP1 —32 0 

1 

- O - CT32B0_MAT1 —32 0 

1 

5 5 - I/O I; PU PIO0_20 — 

/ 

- I - ACMP0_I1 — 0 1 

- I - CT32B0_CAP2 —32 0 

2 

- O - CT32B0_MAT2 —32 0 

2 

6 6 - I/O I; PU PIO0_21 — 

/ 

- I - ACMP0_I2 — 0 2 

- I - CT32B0_CAP3 —32 0 

3 

- O - CT32B0_MAT3 —32 0 

3 

7 7 - I/O I; PU PIO0_22 — 

/ 

- I - ACMP0_I3 — 0 3 

8 8 - I/O I; PU PIO0_23 — 

/ 

- I - ACMP1_I0 — 1 0 

- I - CT32B1_CAP0 —32 1 

0 

- O - CT32B1_MAT0 —32 1 

0 

9 9 - I/O I; PU PIO0_24 — 

/ 

- I - ACMP1_I1 — 1 1 

- I - CT32B1_CAP1 —32 1 

1 

- O - CT32B1_MAT1 —32 1 

1 

10 10 - I/O I; PU SWDIO —SWD 

- I - ACMP1_I2 — 1 2 

- I - CT32B1_CAP2 —32 1 

2 

- O - CT32B1_MAT2 —32 1 

2 

- I/O - PIO0_25 — 

/ 


XN62Lxxx 

 

QFP64 

QFP48 

 

 

 

 

 

SWCLK/ 

ACMP1_I3/ 

CT32B1_CAP3/ 

CT32B1_MAT3/ 

PIO0_26 

PIO0_27/ 

ACMP0_O/ 

DA0 

PIO0_28/ 

ACMP1_O/ 

CT16B0_CAP0/ 

CT16B0_MAT0 

PIO0_29/ 

CT16B0_CAP1/ 

CT16B0_MAT1 

R/ 

PIO0_30/ 

AD0 

R/ 

PIO0_31/ 

AD1/ 

PWM1_7 

R/ 

PIO1_0/ 

AD2 

R/ 

PIO1_1/ 

AD3/ 

PWM0_4/ 

PWM1_4 

PIO1_2/ 

SWDIO/ 

AD4 

PIO1_3/ 

AD5/ 

PIO1_4/ 

AD6/ 

PWM0_5/ 

11 11 - I I; PU SWCLK —SWD 

- I - ACMP1_I3 — 1 3 

- I - CT32B1_CAP3 —32 1 

3 

- O - CT32B1_MAT3 —32 1 

3 

- I/O PIO0_26 — 

/ 

12 12 - I/O I; PU PIO0_27 — 

/ 

- O - ACMP0_O — 0 

- O - DA0 — DA 

17 13 - I/O I; PU PIO0_28 — 

/ . 

- O - ACMP1_O — 1 

- I - CT16B0_CAP0 —16 0 

0 

- O - CT16B0_MAT0 —16 0 

0 

18 14 - I/O I; PU PIO0_29 — 

/ . 

- I - CT16B0_CAP1 —16 0 

1 

- O - CT16B0_MAT1 —16 0 

1 

46 34 - I I; PU R — 

- I/O - PIO0_30 — 

/ 

- I - AD0 —A/D 

0 

47 35 - I I; PU R — 

- I/O - PIO0_31 — 

/ 

- I - AD1 —A/D 

1 

- O - PWM1_7 — PWM 1 , 7 

48 36 - I I; PU R — 

- I/O - PIO1_0 — 

/ 

- I - AD2 —A/D 

2 

49 37 - I I; PU R — 

- I/O - PIO1_1 — 

/ 

- I - AD3 —A/D 

3 

- O - PWM0_4 — PWM 0 , 4 

- O - PWM1_4 — PWM 1 , 4 

50 38 - I/O I; PU PIO1_2 — 

/ 

- I/O - SWDIO —SWD 

- I - AD4 —A/D 

4 

51 39 - I/O I; PU PIO1_3 — 

/ 

- I - AD5 —A/D 

5 

52 40 - I/O I; PU PIO1_4 — 

/ 

- I - AD6 —A/D 

6 

- O - PWM0_5 — PWM 0 , 5 


XN62Lxxx 

 

QFP64 

QFP48 

 

 

 

 

 

PWM1_5 - O - PWM1_5 — PWM 1 , 5 

PIO1_5/ 

AD7/ 

CT16B1_CAP0/ 

CT16B1_MAT0/ 

PWM_FAULT1 

PIO1_6/ 

CT16B1_CAP1/ 

CT16B1_MAT1 

PIO2_0/ 

CT16B0_CAP0/ 

CT16B0_MAT0/ 

PWM1_0 

PIO2_1/ 

CT16B0_CAP1/ 

CT16B0_MAT1/ 

RXD0/ 

PWM_FAULT2/ 

PWM1_1 

PIO2_2/ 

CT16B1_CAP0/ 

CT16B1_MAT0/ 

TXD0/ 

PWM_FAULT3/ 

PWM1_2 

PIO2_3/ 

CT16B1_CAP1/ 

CT16B1_MAT1/ 

PWM1_3 

PIO2_4/ 

CT32B0_CAP0/ 

CT32B0_MAT0/ 

PWM1_4 

PIO2_5/ 

CT32B0_CAP1/ 

CT32B0_MAT1/ 

PWM1_5 

53 41 - I/O I; PU PIO1_5 — 

/ 

- I - AD7 —A/D 

7 

- I - CT16B1_CAP0 —16 1 

0 

- O - CT16B1_MAT0 —16 1 

0 

- I - PWM_FAULT1 — PWM 1 

54 42 - I/O I; PU PIO1_6 — 

/ 

- I - CT16B1_CAP1 —16 1 

1 

- O - CT16B1_MAT1 —16 1 

1 

29 - - I/O I; PU PIO2_0 — 

/ 

- I - CT16B0_CAP0 —16 0 

0 

- O - CT16B0_MAT0 —16 0 

0 

- O - PWM1_0 — PWM 1 , 0 

30 - - I/O I; PU PIO2_1 — 

/ 

- I - CT16B0_CAP1 —16 0 

1 

- O - CT16B0_MAT1 —16 0 

1 



- O - PWM1_1 — PWM 1 , 1 

31 - - I/O I; PU PIO2_2 — 

/ 

- I - CT16B1_CAP0 —16 1 

0 

- O - CT16B1_MAT0 —16 1 

0 



- O - PWM1_2 — PWM 1 , 2 

32 - - I/O I; PU PIO2_3 — 

/ 

- I - CT16B1_CAP1 —16 1 

1 

- O - CT16B1_MAT1 —16 1 

1 

- O - PWM1_3 — PWM 1 , 3 

33 - - I/O I; PU PIO2_4 — 

/ 

- I - CT32B0_CAP0 —32 0 

0 

- O - CT32B0_MAT0 —32 0 

0 

- O - PWM1_4 — PWM 1 , 4 

34 - - I/O I; PU PIO2_5 — 

/ 

- I - CT32B0_CAP1 —32 0 

1 

- O - CT32B0_MAT1 —32 0 

1 

- O - PWM1_5 — PWM 1 , 5 

PIO2_6/ 35 - - I/O I; PU PIO2_6 — 

/ 


XN62Lxxx 

 

QFP64 

QFP48 

 

 

 

 

 

CT32B0_CAP2/ 

CT32B0_MAT2/ 

TXD2/ 

PWM2_4 

PIO2_7/ 

CT32B0_CAP3/ 

CT32B0_MAT3/ 

RXD2/ 

PWM2_5 

PIO2_8/ 

CT32B1_CAP0/ 

CT32B1_MAT0/ 

PWM2_6/ 

AD8 

PIO2_9/ 

CT32B1_CAP1/ 

CT32B1_MAT1/ 

PWM2_7/ 

AD9 

PIO2_10/ 

CT32B1_CAP2/ 

CT32B1_MAT2/ 

TXD1/ 

AD10 

PIO2_11/ 

CT32B1_CAP3/ 

CT32B1_MAT3/ 

RXD1/ 

AD11 

PIO2_12/ 

RXD1/ 

PWM2_0 

PIO2_13/ 

TXD1/ 

PWM2_1 

PIO2_14/ 

TXD3/ 

PWM2_2 

- I - CT32B0_CAP2 —32 0 

2 

- O - CT32B0_MAT2 —32 0 

2 


- O - PWM2_4 — PWM 2 , 4 

36 - - I/O I; PU PIO2_7 — 

/ 

- I - CT32B0_CAP3 —32 0 

3 

- O - CT32B0_MAT3 —32 0 

3 


- O - PWM2_5 — PWM 2 , 5 

59 - - I/O I; PU PIO2_8 — 

/ 

- I - CT32B1_CAP0 —32 1 

0 

- O - CT32B1_MAT0 —32 1 

0 

- O - PWM2_6 — PWM 2 , 6 

- I - AD8 —A/D 

8 

60 - - I/O I; PU PIO2_9 — 

/ 

- I - CT32B1_CAP1 —32 1 

1 

- O - CT32B1_MAT1 —32 1 

1 

- O - PWM2_7 — PWM 2 , 7 

- I - AD9 —A/D 

9 

61 - - I/O I; PU PIO2_10 — 

/ 

- I - CT32B1_CAP2 —32 1 

2 

- O - CT32B1_MAT2 —32 1 

2 


- I - AD10 —A/D 

10 

62 - - I/O I; PU PIO2_11 — 

/ 

- I - CT32B1_CAP3 —32 1 

3 

- O - CT32B1_MAT3 —32 1 

3 


- I - AD11 —A/D 

11 

13 - - I/O I; PU PIO2_12 — 

/ 


- O - PWM2_0 — PWM 2 , 0 

14 - - I/O I; PU PIO2_13 — 

/ 


- O - PWM2_1 — PWM 2 , 1 

15 - - I/O I; PU PIO2_14 — 

/ 


- O - PWM2_2 — PWM 2 , 2 


XN62Lxxx 

 

QFP64 

QFP48 

 

 

 

 

 

PIO2_15/ 

RXD3/ 

PWM2_3 

16 - - I/O I; PU PIO2_15 — 

/ 


- O - PWM2_3 — PWM 2 , 3 

RTCXIN 58 46 - O - 32 KHz 

RTCXOUT 57 45 - I - 32 KHz 

XTALIN 1 1 - I - 

XTALOUT 2 2 - O - 

V REF_ADC 3 3 - I - ADC 

V DD(IO) 63 47 - I - IO 

V DD(3V3) 56 44 - I - 3.3V 

V SSIO 64 48 - I - 

V SS 55 43 - I - 

3.5 

MCU 

IOCONFIG 

SWD RESET 

 

GPIO 

Table 3-2: 

 

PWM PWM0_0 O PIO0_0 

PWM0_1 O PIO0_3 







PWM1_0 O PIO0_21 PIO2_0 











XN62Lxxx 







PWM_FAULT0 I PIO0_27 

PWM_FAULT1 I PIO1_6 

PWM_FAULT2 I PIO0_23 PIO2_1 

PWM_FAULT3 I PIO0_24 PIO2_2 

ACMP0_I0 I PIO0_19 




ACMP0_O O PIO0_27 





ACMP1_O O PIO0_28 

ADC AD0 I PIO0_30 

AD1 I PIO0_31 

AD2 I PIO1_0 

AD3 I PIO1_1 

AD4 I PIO1_2 

AD5 I PIO1_3 

AD6 I PIO1_4 

AD7 I PIO1_5 

AD8 I PIO2_8 

AD9 I PIO2_9 

AD10 I PIO2_10 

AD11 I PIO2_11 

DAC DA0 O PIO0_27 

CT16B0 CT16B0_CAP0 I PIO0_11 PIO0_28 PIO2_0 

CT16B0_CAP1 I PIO0_12 PIO0_29 PIO2_1 

CT16B0_MAT0 O PIO0_11 PIO0_28 PIO2_0 






XN62Lxxx 


















UART0 RXD0 I PIO0_1 PIO2_1 

TXD0 O PIO0_2 PIO2_2 

UART1 RXD1 I PIO0_8 PIO2_11 PIO2_12 

TXD1 O PIO0_9 PIO2_10 PIO2_13 





SPI SCK I/O PIO0_14 

MISO I/O PIO0_16 

MOSI I/O PIO0_17 

SSEL I/O PIO0_15 

TWS SCL I/O PIO0_10 

SDA I/O PIO0_11 

SWD SWCLK I PIO0_26 PIO0_18 

SWDIO I/O PIO0_25 PIO1_2 

QSPI QSPI_CLK O PIO0_3 

QSPI_CS O PIO0_0 

QSPI_DI(IO 0) I/O PIO0_6 

QSPI_DO(IO 1) I/O PIO0_7 

QSPI_WP(IO 2) I/O PIO0_4 

QSPI_HOLD(IO 3) I/O PIO0_5 


XN62Lxxx 

4 

SWD 

XTALIN 

XTALOUT RESET 

TEST/DEBUG 

INTERFACE 

IRC, OSILLATORS 

BOD 

POR 

CLOCK 

GENERATION, 

POWER CONTROL 

SYSTEM 

FUNCTION 

CLKOUT 

ARM 

Cortex-M0 

DMA 

CONTROLLER 

88K/64K 

APP. FLASH 

8K 

BOOT 

16K/12K 

SRAM 

AHB-LITE BUS 

xDSP 

(CRC/Sin/Cos/Arctan/ 

Filter/32-bit Divider) 

AHB-APB 

BRIDGE 

Temperature 

Sensor 

HIGH speed 

GPIO 

GPIO_port 

SPI 

12-bit ADC0 

QSPI 

12-bit ADC1 

12-bit ADC2 (1) 

AD[11:0] 

UART0 

PWM0 

PWM0[7:0] 

UART1 

PWM1 

PWM1[7:0] 

UART2 

PWM2 (1) 

PWM2[7:0] 

UART3 

TWS 

10-bit DAC 

DA 

RTCLKIN 

RTCLKOUT 

WATCHDOG 

32KHz 

OSCILLATOR 

RTC 

COMPARATOR0/1 

ACMP0_I[3:0] 

ACMP1_I[3:0] 

ACMP0_O 

ACMP1_O 

SYSTEM CONTROL 

32-bit 

COUNTER/TIMER 

4xMAT 

4xCAP 

32-bit 

COUNTER/TIMER 

4xMAT 

4xCAP 

16-bit 

COUNTER/TIMER 

2xMAT 

2xCAP 

16-bit 

COUNTER/TIMER 

2xMAT 

2xCAP 

(1): XN62L912 only. 

FFigu 

re 4-1: XN62L 


XN62Lxxx 

5 

5.1 ARM Cortex-M0 

Cortex M0 32 

RISC 

AMBA-Lite 

 

Thumb Cortex-M Thread 

Handler 

Handler Handler 

Thread Thread 

 

M0 

Power 

Management 

Interface 

Connection to 

Debugger 

Wakeup Interrupt 

Controller 

SWD Debug 

Interface 

Interrupt 

Request and 

NMI 

Nested Vector 

Interrupt Controller 

(NVIC) 

Cortex-M0 

Processor Core 

Debug Subsystem 

Internal Bus System 

AHB LITE Bus 

Interface 

Cortex-M0 

Memory and 

Peripherals 

ARM Cortex-M0 : 

• ARMv6-M Thumb 

• Thumb-2 

• ARMv6-M 24- SysTick 

• 32- 

Figure 5-1: Cortex M0 


XN62Lxxx 

• little 

-endian 

• 

• 

• CC 

-ABIARMv6 -MC 

• 

WFI 

WFE 

• NVIC: 

– 32 

4 

– NMI 

– 

– (WIC), 

 

• 

– 

– 

– PCSR 

– 

• : 

– 32AMBA- 

3 ABH-Lite. 

– DAP(Debug Access Port) 32. 

5.2 

XN62L 

4GB F 

lash SRAM APB 

AHB 

 

M0 AHB 2M 

128 GPIO 

xDSP DMA AHB APB 

512K 

APB 16K 

word 

 

8KB ISP 

IAP XN62L Flash 88KBSRAM 

16KBFlashSRAM 

32 

XN62L 


XN62Lxxx 

Private peripheral 

Reserved 

0xE010 0000 

4GB 

Reserved 

Private peripheral 

Reserved 

AHB peripheral 

Reserved 

APB peripheral 

Reserved 

8KB Boot rom 

Reserved 

Reserved 

16KB SRAM 

Reserved 

88KB On-chip 

0xFFFF FFFF 

0xE010 0000 

0xE000 0000 

0x5008 0000 

0x5000 0000 

0x4008 0000 

0x4000 0000 

0x1FFF 2000 

0x1FFF 0000 

0x1FFE 0000 

0x1000 4000 

0x1000 0000 

0x0001 6000 

0x0000 0000 

Interrupt vectors 

0x0000 00C0 

0x0000 0000 

SCB 

NVIC 

System Tick 

Reserved 

AHB peripheral 

xDSP 

Flash 

Reserved 

GPIO PIO2 

GPIO PIO1 

GPIO PIO0 

APB peripheral 

Reserved 

QSPI 

UART3 

UART2 

DAC0 

ADC2 

ADC1 

PWM2 

PWM1 

PWM0 

Comparator 0/1 

RTC 

DMA 

System control 

IO config 

SPI 

Reserved 

PMU 

Reserved 

0xE000 EE00 

0xE000 ED00 

0xE000 E100 

0xE000 E000 

0xE000 0000 

0x5008 0000 

0x5007 0000 

0x5006 0000 

0x5003 0000 

0x5002 0000 

0x5001 0000 

0x5000 0000 

0x4008 0000 

0x4007 C000 

0x4007 8000 

0x4007 4000 

0x4007 0000 

0x4006 C180 

0x4006 8000 

0x4006 4000 

0x4006 0000 

0x4005 C000 

0x4005 8000 

0x4005 4000 

0x4005 0000 

0x4004 C000 

0x4004 8000 

0x4004 4000 

0x4004 0000 

0x4003 C000 

0x4003 8000 

ADC0 

32-bit timer/counter 




UART1 

UART0 

WDT 

TWS 

0x4002 4000 

0x4002 0000 

0x4001 C000 

0x4001 8000 

0x4001 4000 

0x4001 0000 

0x4000 C000 

0x4000 8000 

0x4000 4000 

0x4000 0000 

Figure 5-2: 


XN62Lxxx 

Table 5-1: 

 

0x00000000 ~ 0x00015FFF Flash 

0x10000000 ~ 0x10003FFF 

SRAM 

0x10004000 ~ 0x1FFEFFFF 

0x1FFF0000 ~ 0x1FFF1FFF 

0x40000000 ~ 0x40003FFF 

Boot 

loader 

TWS 

0x40004000 ~ 0x40007FFF 

0x40008000 ~ 0x4000BFFF 

0x4000C000 ~ 0x4000FFFF 

0x40010000 ~ 0x40013FFF 

0x40014000 ~ 0x40017FFF 

0x40018000 ~ 0x4001BFFF 

0x4001C000 ~ 0x4001FFFF 

0x40020000 ~ 0x40023FFF 

UART 0 

UART 1 

16- 0 

16- 1 

32- 0 

32- 1 

ADC0 

0x40024000 ~ 0x40037FFF 

0x40038000 ~ 0x4003BFFF 

PMU 

0x4003C000 ~ 0x4003FFFF 

0x40040000 ~ 0x40043FFF 

0x40044000 ~ 0x40047FFF 

SPI 

IOCONFIG 

0x40048000 ~ 0x4004BFFF 

0x4004C000 ~ 0x4004FFFF DMA 

0x40050000 ~ 0x40053FFF 

0x40054000 ~ 0x40057FFF 

Real Timer Clock 

0,1 

0x40058000 ~ 0x4005BFFF PWM 0 

0x4005C000 ~ 0x4005FFFF PWM 1 

0x40060000 ~ 0x40063FFFF 

0x40064000 ~ 0x40067FFFF 

0x40068000 ~ 0x4006BFFFF 

0x4006C000 ~ 0x4006FFFFF 

0x40070000 ~ 0x40073FFFF 

0x40074000 ~ 0x40077FFFF 

0x40078000 ~ 0x40078BFFF 

PWM2 

ADC1 

ADC2 

DAC 

UART 2 

UART 3 

QSPI 

0x4007C000 ~ 0x4FFFFFFF 

0x50000000 ~ 0x5000FFFF GPIO 0 

0x50010000 ~ 0x5001FFFF GPIO 1 

0x50020000 ~ 0x5002FFFF GPIO 2 

0x50030000 ~ 0x5006FFFF 

0x50070000 ~ 0x5007FFFF 

xDSP 

0x50080000 ~ 0xFFFFFFFF 


XN62Lxxx 

0xE000E000 ~ 0xE000E0FF 

0xE000E100 ~ 0xE000E4FF 

0xE000ED00 ~ 0xE000EE00 

System Tick Timer 

NVIC 

M0 SCB 


XN62Lxxx 

5.3 Cortex-M0 

5.3.1 

Cortex-M0 

(SCB) M0 

SCB 

Table 5-2: Cortex M0 SCB ( 0xE000-ED00) 

 

CPUID RO 0x00 M0 0x410CC200 

ICSR RW 0x04 NMI 0x00000000 

AIRCR RW 0x0C 0xFA050000 

SCR RW 0x10 0x00000000 

CCR RO 0x14 0x00000204 

SHPR2 RW 0x1C 2 0x00000000 

SHPR3 RW 0x20 

3 0x00000000 

5.3.2 CPUID 

CPUID M0 

Table 5-3: CPUID (CPUID, 0xE000-ED00) 

 

3:0 REVISION 

15:4 PARTNO : 0xC20 -M0 = Cortex 

19:16 CONSTANT :, 0xC -M = ARMv6 

23:20 - 

31:24 IMPLEMENTER : 0x41 = ARM 

5.3.3 

(ICSR) 

 

Table 5-4: (ICSR, 

0xE000-ED04) 

 

5:0 VECTACTIVE RO : 

11:6 - - . 

0 = Thread 

0 = 

. 

: 16 CMSIS IRQ 

 


XN62Lxxx 

17:12 VECTPENDING RO 

 

: 

21:18 - - . 

0 = 

0 =. 

22 ISRPENDING RO 

NMI : 

24:23 - - . 

0 = 

1 = 

. 

25 PENDSTCLR WO SysTick 

: 

0 = 

1 = 

 

26 PENDSTSET RW SysTick 

 

. 

: 

0 = 

1 = 

SysTick 

 

: 

0 = 

SysTick 

1 = 

SysTick 

. 

27 PENDSVCLR WO PendSV 

: 

0 = 

1 = PendSV . 

28 PENDSVSET RW PendSV 

. 

: 

0 = 

1 = PendSV 

 

: 

30:29 - - . 

0 = PendSV 

1 = PendSV 

. 

31 NMIPENDSET RW NMI 

. 

: 

0 = 

1 = NMI 

: 

0 = NMI 

1 = NMI 

 

NMI 

1 

 

1 NMI 


XN62Lxxx 

5.3.4 

(AIRCR) 

 

Table 5-5: (AIRCR, 

0xE000-ED0C) 

0 - - . 

1 VECTCLRACTIVE WO 

0 CPU 

2 SYSRESETREQ WO : 

0 = 

14:3 - - 

1 = 

. 

15 ENDIANESS RO 

: 

0 = Little 

-endian 

1 = Big 

-endian. 

31:16 VECTKEY WO 

0x05FA VECTKEY 

 

5.3.5 

(SCR) 

/ 

 

Table 5-6: (SCR, 

0xE000- ED10) 

 

0 - 

1 SLEEPONEXIT 

Handler Thread 

0 = 

Thread 1 = (ISR) 

Thread 1 

 

2 SLEEPDEEP : 

0 = 

3 - . 

1 = . 

4 SEVONPEND 

: 

31:5 - 

0 = 

1 = 

WFE 

WFESEV 

5.3.6 

(CCR) 

 

Cortex-M0 


XN62Lxxx 

Table 5-7: (CCR, 

0xE000-ED14) 

 

2:0 - . 

3 UNALIGN_TRP 1 

HardFault 8:4 - . 

9 STKALIGN 1 

8 

PSR [9] 

31:10 - . 

 

5.3.7 

 

Cortex Microcontroller Software Interface Standard (CMSIS) SCB 

CMSIS 

SHPR2-SHPR3 . 

Table 5-8: SHPR2 ( 0xE000-ED1C) 

 

29:0 - . 

31:30 PRI_11 11 – SVCall 

“0” 

“3” 

Table 5-9: SHPR3 ( 0xE000-ED20) 

 

21:0 - . 

23:22 PRI_14 14 – PendSV 

29:24 - . 

“0” 

“3” 

31:30 PRI_15 15 – SysTick 

“0” 

“3” 

5.4 

(NVIC) 

5.4.1 NVIC 

(NVIC 

)Cortex-M0 

CPU 

• . 

• . 

• 32 . 

• . 

• . 

• (NMI). 


XN62Lxxx 

 

1 

Table 5-10: 

IRQ 

 

0x00 SP 

1 0x04 Reset -3 

2 -14 0x08 NMI -2 

3 -13 0x0C HardFault -1 

10~4 0x10~0x28 

11 -5 0x2C SVCall (1) 

13~12 0x30~0x34 

14 -2 0x38 PendSV (1) 

15 -1 0x3C SysTick (1) 

16 0 0x40 0 (2) 

PIO0_0~PIO0_11 

17 1 0x44 QSPI (2) 

18 2 0x48 

19 3 0x4C 

20 4 0x50 PWM 0 

(2) 

21 5 0x54 PWM 1 

(2) 

22 6 0x58 PWM 2 

(2) 

23 7 0x5C PWM2 (2) 

24 8 0x60 ADC1 (2) A/D 

25 9 0x64 ADC2 (2) 

26 10 0x68 UART 2 (2) (THRE) 

 

(THROE) 

(RBRS) 

(RBROE) 

27 11 0x6C UART 3 (2) (THRE) 

(THROE) 

(RBRS) 

(RBROE) 

28 12 0x70 TWS (2) TWS SI 

29 13 0x74 CT16B0 (2) 0~3 

0~1 

30 14 0x78 CT16B1 (2) 0~3 

0~1 

31 15 0x7C CT32B0 (2) 0~3 

0~3 

32 16 0x80 CT32B1 (2) 0~3 


XN62Lxxx 

0~3 

33 17 0x84 SPI (2) Tx FIFO Rx FIFO 

Rx 

Rx 

34 18 0x88 UART0 (2) (THRE) 

(THROE) 

(RBRS) 

(RBROE) 

35 19 0x8C UART1 (2) (THRE) 

(THROE) 

(RBRS) 

(RBROE) 

36 20 0x90 (2) 0/1 

37 21 0x94 ADC0 (2) A/D 

38 22 0x98 WDT (2) (WDINT) 

39 23 0x9C BOD (2) 

40 24 0xA0 PWM0 (2) 

41 25 0xA4 PIO0 (2) GPIO 0 

42 26 0xA8 PIO1 (2) GPIO 1 

43 27 0xAC PIO2 (2) GPIO 2 

44 28 0xB0 PWM1 (2) 

45 29 0xB4 DMA (2) DMA 

46 30 0xB8 RTC (2) RTC 

47 31 0xBC DAC (2) D/A 

: 

(1) SCB SHPR2-SHPR3. 

(2) NVIC IPR0~IPR7. 

5.4.2 

(NVIC) 

NVIC 

IRQ0~IRQ31, 

Table 5-11: NVIC 

 

INTNMI R/W 0x4004 8174 

(NMI) 

0x00000000 

ISER R/W 0xE000 E100 0x00000000 

ICER R/W 0xE000 E180 0x00000000 

ISPR R/W 0xE000 E200 

ICPR R/W 0xE000 E280 

IPR0 R/W 0xE000 E400 

IPR0 

IPR1 R/W 0xE000 E404 

IPR1 

0x00000000 

0x00000000 

0x00000000 

0x00000000 


XN62Lxxx 

IPR2 R/W 0xE000 E408 

IPR2 

IPR3 R/W 0xE000 E40C 

IPR3 

IPR4 R/W 0xE000 E410 

IPR4 

IPR5 R/W 0xE000 E414 

IPR5 

IPR6 R/W 0xE000 E418 

IPR6 

IPR7 R/W 0xE000 E41C 

IPR7 

0x00000000 

0x00000000 

0x00000000 

0x00000000 

0x00000000 

0x00000000 

5.4.3 

(ISER) 

Table 5-12: (ISER, 

0xE000 E100) 

 

31:0 SETENA IRQ0~IRQ31 

. 

0x00000000 

: 

0 = 

1 = 

: 

0 = 

1 = 

NVIC 

 

 

NVIC 

5.4.4 

(ICER) 

 

Table 5-13: (ICE 

R, 0xE000 E180) 

 

31:0 CLRENA IRQ0~IRQ31 

0x00000000 

: 

0 = 

1 = 

: 

0 = 

1 = 

5.4.5 

(ISPR) 

 

Table 5-14: 

(ISPR, 0xE000 E200) 

 


XN62Lxxx 

31:0 SETPEND IRQ0~IRQ31 . 

0x00000000 

: 

0 = 

1 = 

: 

0 = 

1 = 

5.4.6 

(ICPR) 

 

Table 5-15: ( 

(ICPR, 0xE000 E280) 

 

31:0 CLRPEND IRQ0~IRQ31 

. 

0x00000000 

: 

0 = 

1 = 

 

: 

0 = 

1 = 

5.4.7 

 

IPR0-IPR7 

(IRQ0~IRQ31)2 4 

4 31 24 23 16 15 8 7 0 

IPR7 

PRI_31 PRI_30 PRI_29 PRI_28 

. 

. 

. 

. 

. 

. 

IPRn 

PRI_(4n+3) PRI_(4n+2) PRI_(4n+1) PRI_(4n) 

. 

. 

. 

. 

. 

. 

IPR0 

PRI_3 PRI_2 PRI_1 PRI_0 

Figure 5-3: IPR 

Table 5-16: IPRn (IPR0~7, 0xE000 E400~0xE000 E41C) 

 

7:0 , 0 

7 6 

0x00 

15:8 , 1 

0-3. 

0x00 

23:16 , 2 

0x00 

31:24 , 3 5~0 0 

0x00 


XN62Lxxx 

 

M IPR : 

• IPR , N, N = M DIV 4 

• IPR 

M MOD 4, : 

– 0 

7:0 

– 1 

15:8 

– 2 

23:16 

– 3 

31:24 

5.4.7.1 NMI 

 

ARM Cortex-M0 (NMI). 

Table 5-17: NMI (INTNMI, 

0x4004 8174) 

 

5:0 NMISRC NMI 

. - 

0 ~ 3 wake 

-up 0~3 

4 PWM 0 

5 PWM 1 

6 PWM 2 

7 PWM2 

8 ADC1 

9 ADC2 

10 UART2 

11 UART3 

12 TWS 

13 CT16B0 

14 CT16B1 

15 CT32B0 

16 CT32B1 

17 SPI 

18 UART0 

19 UART1 

20 

21 ADC0 

22 WDT 

23 BOD 

24 PWM0 

25 PIO0 

26 PIO1 

27 PIO2 


XN62Lxxx 

28 PWM1 

29 DMA 

30 RTC 

31 DAC 

32~62 

63 NMI 

31:6 - - 0x0 

5.5 

(SysTick) 

Cortex-M0 

10 

 

Cortex-M0 

Cortex-M0 

• RTOS 

100Hz 

(SysTick) 

• . 

• 

• / 

COUNTFLAG 

 

 

• 24 

• 

• 

Table 5-18: 

( 0xE000 E000) 

 

SYST_CSR R/W 0x010 0x0000 0000 

SYST_RVR R/W 0x014 

0x0000 0000 

SYST_CVR R/W 0x018 

0x0000 0000 

5.5.1 

 

Cortex-M0 Table 5-18: 

(SYST_CSR - 0xE000 E010) 

 

0 ENABLE 0 

0 

1 

1 TICKINT 0 

0 

1 


XN62Lxxx 

15:2 - . NA 

16 COUNTFLAG - 

0 1 0 

31:17 - - NA 

5.5.2 

 

0 

Table 5-19: (SYST_RVR 

- 0xE000 E014) 

 

23:0 RELOAD 

0 0 

31:24 - NA 

5.5.3 

 

Table 5-20: (SYST_CVR 

- 0xE000 E018) 

23:0 CURRENT 

0 

 

STCTRL COUNTFLAG 31:24 NA 

5.5.4 

 

24 

0 10ms 

CPU SYST 

CPU 20Mhz10ms 

: 

1. SYST_RVR RELOAD 

RELOAD = ( 

× 10 ms) −1 

= (20MHz ×10 ms) −1 

= 200000−1 

= 199999 

= 0x00030D3F 

2. SYST_CVR 

3. SYST_SCR 0x7 

5.6 

XN62L 

• 


XN62Lxxx 

• 

• 

• 

• 

Table 5-21: 

 

PMUBase:0x4003 8000 

PCON R/W 0x000 0x0000 0000 

GPREG0 R/W 0x004 0 0x0000 0000 

GPREG1 R/W 0x008 1 0x0000 0000 

GPREG2 R/W 0x00C 2 0x0000 0000 

GPREG3 R/W 0x010 3 0x0000 0000 

SYSCFG R/W 0x014 

(RTC WAKEUP 0x0000 0000 

Base:0x4004 8000 

) 

SYSMEMREMAP R/W 0x000 0x0000 0000 

PRESETCTRL R/W 0x004 0x000F FFFF 

SYSPLLCTRL R/W 0x008 PLL 0x0000 0000 

SYSPLLSTAT R 0x00C PLL 0x0000 0000 

- - 0x010 - 0x01C - 

SYSOSCCTRL R/W 0x020 

0x0000 0000 

WDTOSCCTRL R/W 0x024 

0x0000 0000 

IRCCTRL R/W 0x028 IRC 

0x0000 0080 

- - 0x02C - 

SYSRESSTAT R/W 0x030 0x0000 0000 

- - 0x034 - 0x03C - 

SYSPLLCLKSEL R/W 0x040 PLL 

0x0000 0000 

SYSPLLCLKUEN R/W 0x044 PLL 

0x0000 0000 

- - 0x048 - 0x06C - 

MAINCLKSEL R/W 0x070 0x0000 0000 

MAINCLKUEN R/W 0x074 

0x0000 0000 

SYSAHBCLKDIV R/W 0x078 AHB 0x0000 0001 

- - 0x07C - 

SYSAHBCLKCTRL R/W 0x080 AHB 

0xFFFF FFFF 

- - 0x084 - 0x094 - 

UART0CLKDIV R/W 0x098 UART0 0x0000 0000 

UART1CLKDIV R/W 0x09C UART1 0x0000 0000 

- - 0x0A0- 0x0DC - 

CLKOUTCLKSEL R/W 0x0E0 CLKOUT 0x0000 0000 


XN62Lxxx 

CLKOUTUEN R/W 0x0E4 CLKOUT 

0x0000 0000 

CLKOUTDIV R/W 0x0E8 CLKOUT 0x0000 0000 

- - 0x0EC -0x0FC - 

PIOPORCAP0 R 0x100 PIO 0 



- - 0x 10C - 0x130 - 

IOCONFIGCLKDIV6 R/W 0x134 IO 6 0x0000 0000 


IOCONFIGCLKDIV4 R/W 0x13C IO 4 0x0000 0000 




IOCONFIGCLKDIV0 R/W 0x14C IO 0 0x0000 0000 

BODCTRL R/W 0x150 BOD 0x0000 0000 

- - 0x154 - 0x1FC - 

DSWAKECTL R/W 0x200 0x0000 0000 

DSWAKEEN R/W 0x204 

0x0000 0000 

DSWAKECLR W 0x208 

0x0000 0000 

DSWAKE R 0x20C 0x0000 0000 

- - 0x210 - 0x22C - 

PDSLEEPCFG R/W 0x230 

0x0000 0003 

PDAWAKECFG R/W 0x234 

0x0000 EFF0 

PDRUNCFG R/W 0x238 0x0000 0000 

- - 0x22C 



SYSAHBCLKCTRL PDRUNCFG 

bootloader 

5.6.1 

: 

• (POR) 

• RESET# 

• 

• 

(BOD) 

• 

• 


XN62Lxxx 

RESET#Schmitt 

trigger 

15us 

IRC 

PORBOD 

• IRC 

IRC 

• ROM 

 

0 

5.6.1.1 

F 

lash SRAM ARM 

Table 5-22: ( 

SYSMEMREMAP, 0x4004 8000) 

 

1:0 MAP 00 

0x0 

0x1 

0x2 

 

 

SRAM 

 

SRAM Flash 

Flash 0 31:2 - - 0x00 

5.6.1.2 

SYSRSTSTAT 

 

1 POR 

0 

EXTRST POR 

Table 5-23: (SYSRESSTAT, 

0x4004 8030) 

 

0 POR POR 0 

0 POR 

1 POR 

1 EXTRST 0 

0 RESET 

1 RESET 

2 WDT 0 

0 WDT 

1 WDT 

3 BOD BOD 0 

0 BOD 

1 BOD 

4 SYSRST 

 

RESET# 0 

0 


XN62Lxxx 

1 

31:5 - - 0x00 

5.6.1.3 PIO POR 

PIO POR 

3 PIOPORCAP0 PIO 0 

Table 5-24: 

0 (PIOPORCAP0, 0x4004 8100) 

 

31:0 PIO0_STAT PIO0_0 ~ PIO0_31 

 

PIOPORCAP1 PIO 1 

Table 5-25: 

1 (PIOPORCAP1, 0x4004 8104) 

 


 

31:7 - NA 

PIOPORCAP2 PIO 2 

Table 5-26: 

2 (PIOPORCAP2, 0x4004 8108) 

 


 

31:16 - NA 

5.6.1.4 

 

AIRCR SYSRESETREQ 

SCB 5.6.1.5 POR 

POR 

 

POR Cortex-M0 

5.6.1.6 BOD 

BOD 

 

1. 

2.624V 

0.135V 

2. BOD 

2.828V 

0.101V 

Table 5-27: BOD (BODCTRL, 0x4004 8150) 

 

3:0 - - 0x0 

4 BODRSTEN BOD 0 

0 BOD 

1 BOD 


XN62Lxxx 

5 - - 0x0 

6 BODINTCLR - 1 BOD 

NA 

31:5 - - 0x0 

5.6.2 

5.6.2.1 

MCU XN62L 

 

XN62L 

XTALIN 

XTALOUT 

SYS_OSC 

SYS_OSC_CLK 

SYS_PLLCLK_IN 

PLL 

System AHB 

CLK DIVIDER 

System Clk 

ARM Core 

Peripheral 

PCLK 

SYS_OSC_BYPASS 

SYS_PLLCLKIN_SEL 

MAIN_CLK 

IRC_OSC 

IRC_OSC_CLK 

MAINCLK_SEL 

SYSAHBCLKCTRL 

WDT_CLK 

WDT_OSC 

WDT_OSC_CLK 

WDT_CLK_SEL 

INTERNAL 

CLOCK 

DIVIDERS 

UART0/1, 

RTC, 

SysTick 

PCLK 

RTCXIN 

RTCXOUT 

RTC_OSC 

1Hz 

1KHz 

RTC 

Timer 

RTC 

DIVIDER 

RTC_SEL 

CLOCKOUT 

DIVIDER 

CLOCKOUT 

Outside-Chip-Inside 

CLOCKOUT_SEL 

Inside-Chip-Outside 

Figure 5-4: 

 

XN62L IRC 

 

SYSAHBCLKCTRL UART0/1 

/2/3 

lock 

 

WDT main main clock IRC 

clock 

 

CLKOUT 

5.6.2.2 

 


XN62Lxxx 

Table 5-28: 

(SYSOSCCTRL, 0x4004 8020) 

 

0 BYPASS 0 

0 

1 

PLL (sys_osc_clk) XTALIN 

 

1 FREQRANGE 0 

0 0.4 - 3MHz 

1 3 - 16MHz 

31:2 - 0x00 

5.6.2.3 

 

 

 

clkana) 

(F 

clkana) 

WDT_CLK (F 

clkana) FRWQSEL 320KHz 2.2MHz 

 

DIVSEL 

WDT_CLK 

 

WDT_CLK = F clkana/(4 × (1 + DIVSEL)) = 1.25K Hz ~ 550K Hz (). 

: FREQSEL F clkana ± 

20% 

 

IRC 

: 

Table 5-29: (WDTOSCCTRL, 

0x4004 8024) 

 

4:0 DIVSEL F clkana 

0x0 

8:5 FREQSEL 

(F clkana). 0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

0x7 

0x8 

0x9 

0xA 

0xB 

0xC 

0xD 

0xE 

0xF 

0.32Hz 

0.6MHz 

0.85MHz 

1.04MHz 

1.16MHz 

1.28MHz 

1.43MHz 

1.52MHz 

1.63MHz 

1.7MHz 

1.8MHz 

1.92MHz 

2MHz 

2.08MHz 

2.2MHz 


XN62Lxxx 

31:9 - - 0x0 

5.6.2.4 

 

20MHz 

Table 5-30: (IRCCTRL, 

0x4004 8028) 

9:0 TRIM 0xxxx 

31:10 - 0x00 

5.6.2.5 

PLL 

XN62L PLL 

 

M[7:0] 

VCO_OUT 

FIN 

FCK 

UP 

VCTR 

N[6:0] PFD CP VCO ODSEL[1:0] 

RCK 

DN 

FOUT 

UP 

DN 

LKDT 

LKDT 

Figure 5-5: PLL 

PLL 

FIN 

2MHz 50MHz 

PFD 

/ 

 

(VCO) 

VCO 

 

12.5 MHz 500 MHz 

2xOD 

M 

PLL 

 

OD M PLL 

FOUT 100 MHz 

(LKDT) 

 

” 

 

 

 

 

PLL PLL 

 

SYSPLL_PD 1 


XN62Lxxx 

 

PLL 

SYSPLL_PD 0 PLL 

 

 

 

• 

 

ODSEL 

ODSEL 2 OD 

50% 

• 

 

M PLL 

M 1PLL 

 

• 

PLL 

M ODSEL 

 

PLL PLL 

 

PLL : 

Table 5-31: PLL 

 

FIN 

VCO 

FOUT 

OD 

M 

N 

PLL 

PLL 

sys_pllclkin SYSPLLCLKSEL 

(VCO); 12.5MHz 500MHz. 

PLL 

sys_pllclkout. FOUT100MHz. 

PLL 

SYSPLLCTRL ODSEL 

PLL SYSPLLCTRL 

M 

SYSPLLCTRL N 

PLL 

50% 

FOUT=FIN X 

M 

N 

X 

1 

OD 

= 

VCD 

2 X OD 

 

MOD 

1. FIN 

2. M 

M = FOUT / FIN 

3. VCO = 2 × OD × FOUT. 

4. 

5. FOUT 100MHz. 


PLL (FIN) 

(FOUT) N M ODSEL 

( 

OD) VCO 

12MHz 24MHz 1 8 10 () 4 192MHz 


XN62Lxxx 

12MHz 50MHz 6 100 01 () 2 200MHz 

5.6.2.5.1 PLL 

 

PLL 

PLL 

2MHz 20MHz PLL 

CPU 

Table 5-33: PLL (SYSPLLCTRL, 0x4004 8008) 

 

7:0 M 

2M255 

14:8 N 

1N127 

0x0 

0x0 

16:15 ODSEL 

OD 00 

0x0 OD = 1 

0x1 OD = 2 

0x2 OD = 4 

0x3 OD = 8 

31:17 - 0x0 

5.6.2.5.2 PLL 

 

PLL Table 5-34: PLL (SYSPLLSTAT, 0x4004 800C) 

 

0 LOCK PLL 0 

0 PLL 

1 PLL 

31:1 - - 0x00 

5.6.2.5.3 PLL 

 

PLL 

SYSPLLCLKUEN 

PLL 


(SYSPLLCLKSEL, 0x4004 8040) 

 

1:0 SEL PLL 00 

0x0 

0x1 

0x2 

0x3 

IRC 

 

 

 

31:2 - - 0x00 

5.6.2.5.4 PLL 

 

SYSPLLCLKSEL 

SYSPLLUEN 0 1 


XN62Lxxx 


(SYSPLLCLKUEN, 0x4004 8044) 

 

0 ENA PLL 0 

0 

1 PLL 

31:1 - - 0x00 

5.6.2.6 

5.6.2.6.1 

 

PLL 

 

MAINCLKUEN 0 1 

Table 5-37: 

(MAINCLKSEL, 0x4004 8070) 

 

1:0 SEL 00 

0x0 

0x1 

0x2 

0x3 

 

PLL 

 

PLL 

31:2 - - 0x00 

5.6.2.6.2 

 

MAINCLKSEL 

MAINCLKUEN 0 1 

Table 5-38: (MAINC 

LKUEN, 0x4004 8074) 

 

0 ENA 0 

0 

1 

31:1 - - 0x00 

5.6.2.7 AHB 

5.6.2.7.1 AHB 

 

DIV 0 Table 5-39: AHB (SYSA 

HBCLKDIV, 0x4004 8078) 

 


XN62Lxxx 

7:0 DIV AHB 

0 0x01 

1: 1. 

 

255: 255. 

31:8 0x00 

5.6.2.7.2 AHB 

AHBCLKCTRL 

0 AHB 

APB AHB ARM Cortex-M0 SYSCON PMU 

 

bootloader 

 

Table 5-40: AHB (SYSAHBCLKCTRL, 

0x4004 8080) 

 

0 SYS AHB APB AHB ARM Cortex-M0 SYSCON 1 

0 

1 

PMU 

1 - NA 

2 RAM RAM . 1 

0 

1 

4:3 - - NA 

5 TWS TWS 1 

0 

1 

6 XDSP xDSP 1 

0 

1 

7 CT16B0 16 0 1 

0 

1 

8 CT16B1 16 1 1 

0 

1 

9 CT32B0 32 0 1 

0 

1 

10 CT32B1 32 1 1 

0 

1 

11 SPI SPI 1 


XN62Lxxx 

0 

1 

12 UART0 UART0 1 

0 

1 


0 

1 

14 ADC0 TWS 1 

0 

1 

15 WDT WDT 1 

0 

1 

16 IOCON IO 1 

0 

1 

17 DMA DMA 1 

0 

1 

18 QSPI QSPI 1 

0 

1 

19 RTC RTC 1 

0 

1 

20 CMP 1 

0 

1 

21 PWM0 PWM0 1 

0 

1 


0 

1 


0 

1 

24 ADC1 ADC1 1 

0 


XN62Lxxx 

1 

25 ADC2 ADC2 1 

0 

1 

26 DAC DAC 1 

0 

1 


0 

1 


0 

1 

29 GPIO0 GPIO0 1 

0 

1 


0 

1 


0 

1 

5.6.2.8 UART 

UART 

UART0/1/2/3 

UARTn_PCLK DIV 0 

Table 5-41: UARTn 

(UART0CLKDIV, 0x4004 8098; UART1CLKDIV, 0x4004 809C; UART2CLKDIV, 

0x4004 8240; UART3CLKDIV, 0x4004 8244) 

 

7:0 DIV UARTn 0x0 

0x00 

0x01 

UARTn 

1 

~ ~ 

0xFF 

255. 

31:8 - 0x00 

5.6.2.9 CLKOUT 

5.6.2.9.1 CLKOUT 

 

CLKOUT clkout_clk IRC 

WDT 

RTC clkout_clk CLKOUTCLKUEN 


XN62Lxxx 

Table 5-42: CLKOUT 

(CLKOUTCLKSEL, 0x4004 80E0) 

 

1:0 SEL CLKOUT 00 

0x0 

0x1 

0x2 

0x3 

0x4 

IRC 

 

 

 

RTC 

31:2 - - 0x00 

5.6.2.9.2 CLKOUT 

 

CLKOUTCLKSEL 

CLKCLKUEN 0 1 

Table 5-43: CLKOUT (CLKOUTUEN, 

0x4004 80E4) 

 

0 ENA CLKOUT 0 

0 

1 

31:1 - - 0x00 

5.6.2.9.3 CLKOUT 

 

CLKOUT clkout_clk 

Table 5-44: CLKOUT 

(CLKOUTDIV, 0x4004 80E8) 

 

7:0 DIV 0 

0x00 

0x01 

 

1 

~ ~ 

0xFF 

255. 

31:8 - - 0x00 

5.6.2.10 

7 

IO 

DIV 0 Table 5-45: IOCONFIG 

0 ~ 6(IOCONFIGCLKDIV0 ~ IOCONFIGCLKDIV6, 4004 8014C 4004 80134) 

 

7:0 DIV 

1~255 0 

0x00 

 


XN62Lxxx 

0x01 

0x03 

~ 

0xFF 

1 

3 

~ 

255 

31:8 - - 0x00 

5.6.3 

XN62L 

 

 

 

SWD 

 

Table 5-46: 

 

 

M0 - 

SRAM - 

FLASH - 

IRCOUT - PDRUNCFG - PDRUNCFG - - 

IRC - PDRUNCFG - PDRUNCFG - - 

BOD - PDRUNCFG - PDRUNCFG - PDSLEEPCFG - 

ADC0 - PDRUNCFG - PDRUNCFG - - 

DAC - PDRUNCFG - PDRUNCFG - - 

SYSOSC - PDRUNCFG - PDRUNCFG - - 

WDTOSC - PDRUNCFG - PDRUNCFG - PDSLEEPCFG - 

SYSPLL - PDRUNCFG - PDRUNCFG - - 



RTCOSC - PDRUNCFG - PDRUNCFG - PDSLEEPCFG - PDRUNCFG 

COMP - PDRUNCFG - PDRUNCFG - - 

TWS AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

xDSP AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

CT16B0 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 




SPI AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

UART0,1, 

AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

2,3 

ADC0,1,2 

AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

/DAC 

WDT AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 


XN62Lxxx 

IOCON AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

DMA AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

RTC AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

CMP AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

 

PWM0,1,2 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 

GPIO0 AHBCLKCTRL AHBCLKCTRL AHBCLKCTRL - 



WAKEUP - - - - - - - 

5.6.3.1 

 

ARM Cortex-M0 

 

 

Table 5-47: 

(PCON, 0x4003 8000) 

 

0 - - . 0 

1 DPDEN 0 

0 ARM WFI 

ARM Cortex-M0 

1 ARM WFI 

7:2 - - . 0x0 

8 SLEEPFLAG 0 

0 : 

: . 

1 : 

: 1 SLEEPFLAG 

10:9 - - . 00 

11 DPDFLAG 0 

0 : 

: . 

1 : 

: 

31:12 - - . 0x0 

5.6.3.2 

0~3 

V 

DD(3V3) 

Table 5-48: 

0 ~3 (GPREG0 - GPREG3, 0x4003 8004 ~ 0x4003 8010) 

 

31:0 GPDATA 0x0 


XN62Lxxx 

5.6.3.3 RTC 

 

RTC 32 1 kHz RTC 

1kHz 

Hz 

RTC 

RTC RTC 

RTC 

SYSAHBCLKCTRL 

RTC 

 

Table 5-49: (SYSCFG, 

0x4003 8014) 

 

10:0 - - . 0x0 

12:11 RTCCLK RTC 0000 

00 1 Hz 

01 IRC 

10 1 kHz 

11 RTC PCLK 

31:15 - - . 0x0 

5.6.3.4 

 

RTC BOD (WD 

T) BOD 

WDT WDMODE WDLOCKCLK 

Table 5-50: (PDSLEEPCFG, 

0x4004 8230) 

 

2:0 - . 011 

3 BOD_PD 

BOD 0 

0 

1 

5:4 - . 00 

6 WDTOSC_PD 

WDMODE 0 

0 

1 

WDLOCKCLK 1 

11:7 - - 00000 

12 RTCOSC_PD 

RTC 0 

0 

1 

15:13 - - 00 

31:16 - - 0x00 

5.6.3.5 

 

Table 5-51: (PDAWAKECFG, 

0x4004 8234) 


XN62Lxxx 

 

0 IRCOUT_PD IRC 0 

0 

1 

1 IRC_PD IRC 0 

0 

1 

2 - - 0 

3 BOD_PD BOD 0 

0 

1 

4 ADC0_PD ADC0 1 

0 

1 

5 SYSOSC_PD 1 

0 

1 

6 WDTOSC_PD 

1 

0 

1 

7 SYSPLL_PD PLL 1 

0 

1 

8 - - 1 


0 

1 


0 

1 

11 DAC_PD DAC 1 

0 

1 

12 RTCOSC_PD RTC 0 

0 

1 

14:13 - - 11 

15 COMP_PD 1 

0 


XN62Lxxx 

1 

31:16 - - 0 

5.6.3.6 

PDRUNCFG 

 

bootloader : 2 

WDT 

• 

WDT 

MOD 

5 

PDRUNCFG 6 

. 

• IRC WDT 

MOD 

5 

PDRUNCFG 0 1 . 

Table 5-52: (PDRUNCFG 

, 0x4004 8238) 

 

0 IRCOUT_PD IRC 0 

0 

1 

1 IRC_PD IRC 0 

0 

1 

2 - - 0 

3 BOD_PD BOD 0 

0 

1 


0 

1 

5 SYSOSC_PD 0 

0 

1 

6 WDTOSC_PD 0 

0 

1 

7 SYSPLL_PD PLL 0 

0 

1 

8 - - 0 


0 

1 



XN62Lxxx 

0 

1 

11 DAC_PD DAC 0 

0 

1 

12 RTCOSC_PD RTC 0 

0 

1 

14:13 - - 00 

15 COMP_PD 0 

0 

1 

31:16 - - 0 

5.6.3.7 

 

ARM Cortex-M0 system clock 

 

PDRUNCFG SYSAHBCLKCTRL 

PDRUNCFG 


 

• SYSAHBCLKCTRL 

• PDRUNCFGPLL 

ADCBOD 

, 

• system clockIRC 

• system clockSYSPLLCTRL 

SYSAHBCLKDIV 

• (UART0/1 /2/3, WDT) 

 

5.6.3.8 

ARM -M0 

Cortex 

 

 

 


 

 

 

 

• 

• system clock 

• 

 


XN62Lxxx 

 

1. 

PCON DPDEN 0 

2. ARM Cortex-M0 SCR SLEEPDEEP 0 

3. ARM Cortex-M0 Wait-For-Interrupt (WFI) 

 

 

PDRUNCFG SYSAHBCLKDIV 

 

5.6.3.9 

system BOD 

clock 

RTC 

BOD 

RTC 

PDSLEEPCFG RTC 

 

 

RTC 

 

 

 

PDSLEEPCFG : 

• RTC 

 

IRC 

PLL 

• BOD 

• SYSAHBCLKCTRL 

WDT 

• RTC RTC 

 

 

1. 

PCON DPDEN 0 

2. PDSLEEPCFG . 

3. 

PDAWAKECFG. 

4. 

– 

NVIC – RTC NVIC RTC 

5. 

MAINCLKSEL 

6.SYSAHBCLKCTRL 

RTC WDT 

7. ARM Cortex-M0 SCR SLEEPDEEP 1 

8. ARM Cortex-M0 Wait-For-Interrupt (WFI) 

 

 


XN62Lxxx 

• PIO0_0 

~ PIO0_11 

• RTC 

• 

• BOD 

BOD 

PDSLEEPCFG BOD BODCTRL 

• 

PDSLEEPCFG SYSAHBCLKCTRL WDT 

• Reset 

 

ARM 

PIO0_0 ~ PIO0_11 

 

 

NVIC 

0 3 PIO0_0 PIO0_11 

 

RTC 

RTC RTC NVIC 

RTC 

5.6.3.10 

 

WAKEUP 

WDMODE WDLOCKDP 1 

 

RTC 

RTC 

RTC 

RTC 

 

PMU 4 32 

SRAM 

 

WAKEUP . 

 

 

RTC RTC 

WAKEUP 

RTC RTC 

 

WDMODE 

WDLOCKDP 0 

WDLOCKDP = 1 

 

 

1. PCON 

DPDEN1 

2. 

3. ARM Cortex-M0 SCRSLEEPDEEP1 

4. ARM Cortex -M0 Wait-For-Interrupt (WFI) 

 


XN62Lxxx 

 

RTC 

XN62L 

• WAKEUP XN62L 

WAKEUP 

WAKEUP 

WAKEUP 

1. WAKEUP 

– PMU 

– GPREG0 GPREG3 

– RTC RTC 

2. PCON 

 

3. PCON . 

4. 

5. PMU 

5.6.4 

XN62L 

5.6.4.1 

DSWAKECTL P0 PIO0_0 ~ PIO0_11 

DSWAKECTL 

0 11 PIO0_0 ~ PIO0_11 

Table 5-53:(DSWAKECTL, 

0x4004 8200) 

 

0 CTLPIO0_0 PIO0_0 

0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


XN62Lxxx 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 

10 CTLPIO0_10 PIO0_10 

0 

0 = 

1 = 

11 CTLPIO0_11 PIO0_11 

0 

0 = 

1 = 

31:12 - - 0 

5.6.4.2 

DSWAKEEN 

Table 5-54: (DSWAKEEN, 

0x4004 8204) 

0 ERPIO0_0 PIO0_0 

0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


XN62Lxxx 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 

10 ERPIO0_10 PIO0_10 

0 

0 = 

1 = 

11 ERPIO0_11 PIO0_11 

0 

0 = 

1 = 

31:12 

5.6.4.3 

DSWAKECLR 

1 

 

 

Table 5-55: (DSWAKECLR, 

0x4004 8208) 

0 RSRPIO0_0 PIO0_0 

0 

0 = . 

1 = 1 


XN62Lxxx 


0 

0 = . 

1 = 1 


0 

0 = . 

1 = 1 


0 

0 = . 

1 = 1 


0 

0 = . 

1 = 1 


0 

0 = . 

1 = 1 


0 

0 = . 

1 = 1 


0 

0 = . 

1 = 1 


0 

0 = . 

1 = 1 


0 

0 = . 

1 = 1 

10 RSRPIO0_10 PIO0_10 

0 

0 = . 

1 = 1 

11 RSRPIO0_11 PIO0_11 

0 

0 = . 

1 = 1 

31:12 - - 

5.6.4.4 

 

Table 5-56: (DSWAKE, 

0x4004 820C) 


XN62Lxxx 

0 SRPIO0_0 PIO0_0 

0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 


0 

0 = 

1 = 

10 SRPIO0_10 PIO0_10 

0 

0 = 

1 = 

11 SRPIO0_11 PIO0_11 

0 

0 = 

1 = 

31:12 - - 


XN62Lxxx 

5.6.5 

5.6.5.1 

 

0 

 

1 

Table 5-57: (PRESETCTRL, 

0x4004 8004) 

 

0 SPI_RST_N SPI 1 

0 SPI 

1 SPI 

1 TWS_RST_N TWS 1 

0 TWS 

1 TWS 

2 UART0_RST_N UART0 1 

0 UART0 

1 UART0 


0 UART1 

1 UART1 

4 CT16B0_RST_N 16 / 0 (CT16B0) 1 

0 CT16B0 

1 CT16B0 

5 CT16B1_RST_N 16 / 1 (CT16B1) 1 

0 CT16B1 

1 CT16B1 

6 CT32B0_RST_N 32 / 0 (CT32B0) 1 

0 CT32B0 

1 CT32B0 

7 CT32B1_RST_N 32 / 1 (CT32B1) 1 

0 CT32B1 

1 CT32B1 

8 CMP_RST_N 1 

0 

1 

 

9 XDSP_RST_N xDSP 1 

0 xDSP 

1 xDSP 

10 DMA_RST_N DMA 1 

0 DMA 


XN62Lxxx 

1 DMA 

11 PWM0_RST_N PWM0 1 

0 PWM0 

1 PWM0 


0 PWM1 

1 PWM1 


0 PWM2 

1 PWM2 

14 ADC0_RST_N ADC0 1 

0 ADC0 

1 ADC0 


0 ADC1 

1 ADC1 


0 ADC2 

1 ADC2 

17 DAC_RST_N DAC 1 

0 DAC 

1 DAC 


0 UART2 

1 UART2 


0 UART3 

1 UART3 

31:20 - - 0x0 

5.7 I/O 

 

XN62L 

IOCON 

I/O 

• 

• / 

• 

• ADC 


XN62Lxxx 

• IO 

5.7.1 IOCON 

PIO0_10 

PIO0_11 Table 5-58: IOCON ( TWS ) 

 

2:0 FUNC 000 

000 0 ( ). 

001 1. 

010 2. 

011 3. 

100 4. 

101 5. 

110 6. 

111 . 

3 - 0 

4 MODE 

(). 1 

0 

1 

5 - . 0 

6 INV 0 

0 

1 

7 ADMODE / 1 

0 

1 

8 - . 0 

9 DRV 0 

0 

1 

10 OD 0 

0 

1 

 

V DD (IO). 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

 

1 

1 

2 

2 


XN62Lxxx 

0x3 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

0x7 

IOCONFIGCLKDIV0. 







 

31:16 - - . 0 

5.7.1.1 

IOCON FUNC GPIO (FUNC = 000) 

GPIO DIR 

 

GPIOnDIR . 

5.7.1.2 

IOCON MODE 

TWS PIO0_10 PIO0_11 

 

5.7.1.3 

 

PIO0_27PIO0_28 

PIO0_29PIO0_12 

5.7.1.4 

PIO0_10 PIO0_11 I/O 

V DD(IO) . 

5.7.1.5 A/D 

A/D 

ADC A/D 

5.7.1.6 TWS (I 2 C ) 

TWS PIO0_10 PIO0_11 

TWS 

PIO0_10 PIO0_11 (20 mA) 

5.7.1.7 

G PIO 


XN62Lxxx 

S_MODE 2 37 

= 1 PCLK0 6 

IOCONFIGCLKDIV0 6 

 

t pulse 

t pulse < t PCLKn × S_MODE 

 

t pulse < t PCLKn × (S_MODE + 1) 

(S_MODE 

 

SPI 

(S_MODE) 

5.7.2 IOCON 

Table 5-59: I/O 

( 0x4004 4000) 

 

 

- R/W 0x000 . - 

- R/W 0x004 . - 

PIO0_19 R/W 0x008 PIO0_19/ACMP0_I0/CT32B0_CAP1/CT32B0_MAT1 0x0000 0090 

PIO0_20 R/W 0x00C PIO0_20/ACMP0_I1/CT32B0_CAP2/CT32B0_MAT2 0x0000 0090 

PIO0_21 R/W 0x010 PIO0_21/ACMP0_I2/CT32B0_CAP3/CT32B0_MAT3/PWM1_0 0x0000 0090 

PIO0_22 R/W 0x014 PIO0_22/ACMP0_I3/PWM1_1 0x0000 0090 

PIO0_23 R/W 0x018 PIO0_23/ACMP1_I0/CT32B1_CAP0/CT32B1_MAT0/PWM_FAULT2 0x0000 0090 

PIO0_24 R/W 0x01C PIO0_24/ACMP1_I1/CT32B1_CAP1/CT32B1_MAT1/PWM_FAULT3 0x0000 0090 

PIO0_25 R/W 0x020 SWDIO/ACMP1_I2/CT32B1_CAP2/CT32B1_MAT2/PIO0_25 0x0000 0090 

PIO0_26 R/W 0x024 SWCLK/ACMP1_I3/CT32B1_CAP3/CT32B1_MAT3/PIO0_26 0x0000 0090 

PIO0_27 R/W 0x028 PIO0_27/ACMP0_O/DA0/PWM_FAULT0 0x0000 0090 

PIO2_12 R/W 0x02C PIO2_12/RXD1/ PWM2_0 0x0000 0090 

PIO2_13 R/W 0x030 PIO2_13/TXD1/ PWM2_1 0x0000 0090 

PIO2_14 R/W 0x034 PIO2_14/ PWM2_2/TXD3. 0x0000 0090 

PIO2_15 R/W 0x038 PIO2_15/ PWM2_3/RXD3. 0x0000 0090 

PIO0_28 R/W 0x03C PIO0_28/ACMP1_O/DA0/CT16B0_CAP0/CT16B0_MAT0 0x0000 0090 

PIO0_29 R/W 0x040 PIO0_29/ROSC/CT16B0_CAP1/CT16B0_MAT1/ PWM1_6 0x0000 0090 

PIO0_0 R/W 0x044 PIO0_0/PWM0_0 0x0000 0090 

PIO0_1 R/W 0x048 PIO0_1/RXD0/CT32B0_CAP0/CT32B0_MAT0 0x0000 0090 

PIO0_2 R/W 0x04C PIO0_2/TXD0/CT32B0_CAP1/CT32B0_MAT1 0x0000 0090 

- R/W 0x050 - 

PIO0_3 R/W 0x054 PIO0_3/CT32B0_CAP2/CT32B0_MAT2/PWM0_1/PWM1_4 0x0000 0090 


PIO0_5 R/W 0x05C PIO0_5/ PWM0_3. 0x0000 0090 



XN62Lxxx 


PIO0_8 R/W 0x068 PIO0_8/RXD1/CT32B1_CAP2/CT32B1_MAT2/PWM0_6 0x0000 0090 

PIO0_9 R/W 0x06C PIO0_9/TXD1/CT32B1_CAP3/CT32B1_MAT3/PWM0_7 0x0000 0090 

PIO2_0 R/W 0x070 PIO2_0/CT16B0_CAP0/CT16B0_MAT0/PWM1_0 0x0000 0090 

PIO2_1 R/W 0x074 

0x0000 0090 

PIO2_1/CT16B0_CAP1/CT16B0_MAT1/RXD0/PWM_FAULT2/PWM1_1 

PIO2_2 R/W 0x078 

0x0000 0090 

PIO2_2/CT16B1_CAP0/CT16B1_MAT0/TXD0/PWM_FAULT3/PWM1_2 

PIO2_3 R/W 0x07C PIO2_3/CT16B1_CAP1/CT16B1_MAT1/PWM1_3 0x0000 0090 

PIO2_4 R/W 0x080 PIO2_4/CT32B0_CAP0/CT32B0_MAT0/PWM1_4 0x0000 0090 

PIO2_5 R/W 0x084 PIO2_5/CT32B0_CAP1/CT32B0_MAT1/ PWM1_5 0x0000 0090 

PIO2_6 R/W 0x088 PIO2_6/CT32B0_CAP2/CT32B0_MAT2/PWM2_4/TXD2 0x0000 0090 

PIO2_7 R/W 0x08C PIO2_7/CT32B0_CAP3/CT32B0_MAT3/PWM2_5/RXD2 0x0000 0090 

PIO0_10 R/W 0x090 PIO0_10/SCL 0x0000 0080 

PIO0_11 R/W 0x094 PIO0_11/SDA/CT16B0_CAP0/CT16B0_MAT0 0x0000 0080 

PIO0_12 R/W 0x098 PIO0_12/CLKOUT/CT16B0_CAP1/CT16B0_MAT1// PWM1_6 0x0000 0090 

PIO0_13 R/W 0x09C RESET/PIO0_13. 0x0000 0090 

PIO0_14 R/W 0x0A0 PIO0_14/SPI_CLK/TXD2. 0x0000 0090 

PIO0_15 R/W 0x0A4 PIO0_15/SSEL/CT16B1_CAP0/CT16B1_MAT0/RXD2 0x0000 0090 

PIO0_16 R/W 0x0A8 PIO0_16/MISO/CT16B1_CAP1/CT16B1_MAT1/TXD3 0x0000 0090 

PIO0_17 R/W 0x0AC PIO0_17/SPI_MOSI/RXD3. 0x0000 0090 

PIO0_18 R/W 0x0B0 PIO0_18/SWCLK/CT32B0_CAP0/CT32B0_MAT0 0x0000 0090 

PIO0_30 R/W 0x0B4 R/PIO0_30/AD0. 0x0000 0090 

PIO0_31 R/W 0x0B8 R/PIO0_31/AD1/PWM1_7 0x0000 0090 

PIO1_0 R/W 0x0BC R/PIO1_0/AD2. 0x0000 0090 

PIO1_1 R/W 0x0C0 R/PIO1_1/AD3/ PWM0_4/PWM1_4. 0x0000 0090 

PIO1_2 R/W 0x0C4 PIO1_2/SWDIO/AD4. 0x0000 0090 

PIO1_3 R/W 0x0C8 PIO1_3/AD5/WAKEUP. 0x0000 0090 

PIO1_4 R/W 0x0CC PIO1_4/AD6/ PWM0_5/PWM1_5. 0x0000 0090 

PIO1_5 R/W 0x0D0 PIO1_5/AD7/CT16B1_CAP0/CT16B1_MAT0 0x0000 0090 

PIO1_6 R/W 0x0D4 PIO1_6/CT16B1_CAP1/CT16B1_MAT1/PWM_FAULT1 0x0000 0090 

- - 0x0D8 . - 

- - 0x0DC . - 

PIO2_8 R/W 0x0E0 PIO2_8/CT32B1_CAP0/CT32B1_MAT0/PWM2_6/AD8 0x0000 0090 

PIO2_9 R/W 0x0E4 PIO2_9/CT32B1_CAP1/CT32B1_MAT1/PWM2_7/AD9 0x0000 0090 

PIO2_10 R/W 0x0E8 PIO2_10/CT32B1_CAP2/CT32B1_MAT2/TXD1/AD10 0x0000 0090 

PIO2_11 R/W 0x0EC PIO2_11/CT32B1_CAP3/CT32B1_MAT3/RXD1/AD11 0x0000 0090 


XN62Lxxx 

5.7.2.1 PIO0_0 IOCON 

Table 5-60: PIO0_0 (PIO0_0, 0x4004 4044) 

 

2:0 FUNC . 000 

0x0 

PIO0_0. 

0x1~2 

0x3 

0x4 

PWM0_0. 

QSPI_CS. 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 

5 . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 2mA . 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 


XN62Lxxx 

5.7.2.2 PIO0_1 IOCON 

Table 5-61: PIO0_1 (PIO0_1, 0x4004 4048) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

PIO0_1. 

. 

RXD0. 

CT32B0_CAP0. 

CT32B0_MAT0. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 


XN62Lxxx 

5.7.2.3 PIO0_2 IOCON 

Table 5-62: PIO0_2 (PIO0_2, 0x4004 404C) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

PIO0_2. 

. 

TXD0. 

CT32B0_CAP1. 

CT32B0_MAT1. 

3 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 


XN62Lxxx 

5.7.2.4 PIO0_3 IOCON 

Table 5-63: PIO0_3 (PIO0_3, 0x4004 4054) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

PIO0_3. 

QSPI_CLK. 

. 

CT32B0_CAP2. 

CT32B0_MAT2. 

PWM0_1 

PWM1_4 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 









XN62Lxxx 

31:16 - - . 0 

5.7.2.5 PIO0_4 IOCON 

Table 5-64: PIO0_4 (PIO0_4, 0x4004 4058) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

PIO0_4. 

QSPI_WP. 

. 

CT32B0_CAP3. 

CT32B0_MAT3. 

PWM0_2 

PWM1_5 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 







XN62Lxxx 

0x5 

0x6 



31:16 - - . 0 

5.7.2.6 PIO0_5 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

PIO0_5. 

QSPI_HOLD 

 

PWM0_3. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 








XN62Lxxx 

0x6 


31:16 - . 0 

5.7.2.7 PIO0_6 IOCON 

Table 5-66: PIO0_6 (PIO0_6, 0x4004 4060) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

PIO0_6. 

QSPI_DI 

. 

CT32B1_CAP0. 

CT32B1_MAT0. 

PWM0_4. 

PWM1_2. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 






XN62Lxxx 

0x4 

0x5 

0x6 




31:16 - . 0 

5.7.2.8 PIO0_7 IOCON 

Table 5-67: PIO0_7 (PIO0_7, 0x4004 4064) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

PIO0_7. 

QSPI_DO 

. 

CT32B1_CAP1. 

CT32B1_MAT1. 

PWM0_5. 

PWM1_3. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 




XN62Lxxx 

0x2 

0x3 

0x4 

0x5 

0x6 






31:16 - . 0 

5.7.2.9 PIO0_8 IOCON 

Table 5-68: PIO0_8 (PIO0_8, 0x4004 4068) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO0_8. 

. 

RXD1. 

CT32B1_CAP2. 

CT32B1_MAT2. 

PWM0_6. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 



XN62Lxxx 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 







31:16 - - . 0 

5.7.2.10 PIO0_9 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO0_9. 

. 

TXD1. 

CT32B1_CAP3. 

CT32B1_MAT3. 

PWM0_7. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 


XN62Lxxx 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.1 PIO0_10 IOCON 

Table 5-70: PIO0_10 (PIO0_10, 0x4004 4090) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

PIO0_10. 

. 

TWS SCL 

5:3 - . 000 

6 INV 0 

0 . 

1 . 

10:7 - - . 0001 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

0x0 








. 

31:16 - . 0 

5.7.2.2 PIO0_11 IOCON 

Table 5-71: PIO0_11 (PIO0_11, 0x4004 4094) 

 


XN62Lxxx 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

PIO0_11. 

. 

TWS SDA . 

CT16B0_CAP0. 

CT16B0_MAT0. 

5:3 - - . 000 

6 INV 0 

0 . 

1 . 

10:7 - - . 0001 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

0x0 








. 

31:16 - . 0 

5.7.2.3 PIO0_12 IOCON 

Table 5-72: PIO0_12 (PIO0_12, 0x4004 4098) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

PIO0_12. 

. 

CLKOUT. 

CT16B0_CAP1. 

CT16B0_MAT1. 

. 

PWM1_6. 

3 - 0 

4 MODE 

(). 1 


XN62Lxxx 

0 . 

1 . 

5 . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 

5.7.2.4 PIO0_13 IOCON 

Table 5-73: RESET_PIO0_13 (RESET_PIO0_13, 0x4004 409C) 

 

2:0 FUNC . 000 

0x0 

0x1 

RESET. 

PIO0_13. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 . 0 


XN62Lxxx 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 

5.7.2.5 PIO0_14 IOCON 

Table 5-74: PIO0_14 (PIO0_14, 0x4004 40A0) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO0_14. 

. 

SCK. 

CLKOUT. 

. 

TXD2. 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 


XN62Lxxx 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 2mA . 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.6 PIO0_15 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO0_15. 

. 

SSEL. 

CT16B1_CAP0. 

CT16B1_MAT0. 

RXD2. 

3 - 0 

4 MODE 

() 

. 1 

0 . 


XN62Lxxx 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 2mA . 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.7 PIO0_16 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO0_16. 

. 

MISO. 

CT16B1_CAP1. 

CT16B1_MAT1. 

TXD3. 

3 - 0 

4 MODE 

() 

. 1 


XN62Lxxx 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 2mA . 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.8 PIO0_17 IOCON 

Table 5-77: PIO0_17 (PIO0_17, 0x4004 40AC) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

PIO0_17. 

. 

MOSI. 

0x3~4 . 

0x5 

RXD3. 

3 - 0 

4 MODE 

() 

. 1 


XN62Lxxx 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 2mA . 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.9 PIO0_18 IOCON 

Table 5-78: PIO0_18 (PIO0_18, 0x4004 40B0) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

PIO0_18. 

. 

SWCLK. 

CT32B0_CAP0. 

CT32B0_MAT0. 

3 - 0 

4 MODE 

() 

. 1 


XN62Lxxx 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 2mA . 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.10 PIO0_19 IOCON 

Table 5-79: PIO0_19 (PIO0_19, 0x4004 4008) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

PIO0_19. 

. 

ACMP0_I0. 

CT32B0_CAP1. 

CT32B0_MAT1. 

3 - 0 

4 MODE 

() 

. 1 


XN62Lxxx 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.11 PIO0_20 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

PIO0_20. 

. 

ACMP0_I1. 

CT32B0_CAP2. 

CT32B0_MAT2. 


XN62Lxxx 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.12 PIO0_21 IOCON 

Table 5-81: PIO0_21 (PIO0_21, 0x4004 4010) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

PIO0_21. 

. 

ACMP0_I2. 


XN62Lxxx 

0x3 

0x4 

0x5 

CT32B0_CAP3. 

CT32B0_MAT3. 

PWM1_0 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.13 PIO0_22 IOCON 

Table 5-82: PIO0_22 (PIO0_22, 0x4004 4014) 

 

2:0 FUNC . 000 


XN62Lxxx 

0x0 

0x1 

0x2 

PIO0_22. 

. 

ACMP0_I3. 

0x3~4 . 

0x5 

PWM1_1 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 

5.7.2.14 PIO0_23 IOCON 

Table 5-83: PIO0_23 (PIO0_23, 0x4004 4018) 


XN62Lxxx 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO0_23. 

. 

ACMP1_I0. 

CT32B1_CAP0. 

CT32B1_MAT0. 

PWM_FAULT2 

3 - - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 


XN62Lxxx 

5.7.2.15 PIO0_24 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO0_24. 

. 

ACMP1_I1. 

CT32B1_CAP1. 

CT32B1_MAT1. 

PWM_FAULT3 

3 - - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 








XN62Lxxx 

0x6 


31:16 - - . 0 

5.7.2.16 PIO0_25 IOCON 

Table 5-85: SWDIO_PIO0_25 (SWDIO_PIO0_25, 0x4004 4020) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

SWDIO. 

. 

ACMP1_I2. 

CT32B1_CAP2. 

CT32B1_MAT2. 

. 

PIO0_25. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 




XN62Lxxx 

0x2 

0x3 

0x4 

0x5 

0x6 






31:16 - - . 0 

5.7.2.17 PIO0_26 IOCON 

Table 5-86: SWCLK_PIO0_26 (SWCLK_PIO0_26, 0x4004 4024) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

SWCLK. 

. 

ACMP1_I3. 

CT32B1_CAP3. 

CT32B1_MAT3. 

. 

PIO0_26. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

 

1 

1 

2 

2 


XN62Lxxx 

0x3 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.18 PIO0_27 IOCON 

Table 5-87: PIO0_27 (PIO0_27, 0x4004 4028) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

PIO0_27. 

. 

ACMP0_O. 

0x3~4 . 

0x5 

0x6 

PWM_FAULT0 

DA0 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 


XN62Lxxx 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 

5.7.2.19 PIO0_28 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

PIO0_28. 

. 

ACMP1_O. 

CT16B0_CAP0. 

CT16B0_MAT0. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 


XN62Lxxx 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 

5.7.2.20 PIO0_29 IOCON 

Table 5-89: PIO0_29 (PIO0_29, 0x4004 4040) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO0_29. 

. 

. 

CT16B0_CAP1. 

CT16B0_MAT1. 

PWM1_6. 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 

5 . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV 0 

0 

1 

. 

10 OD 0 

0 

1 


XN62Lxxx 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - 0 

5.7.2.1 PIO0_30 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

. 

PIO0_30. 

. 

AD0. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 


XN62Lxxx 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.2 PIO0_31 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

. 

PIO0_31. 

. 

AD1. 

. 

PWM1_7. 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 


XN62Lxxx 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.3 PIO1_0 IOCON 

Table 5-92: PIO1_0 (PIO1_0, 0x4004 40BC) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

. 

PIO1_0. 

AD2. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 2mA . 


XN62Lxxx 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.4 PIO1_1 IOCON 

Table 5-93: PIO1_1 (PIO1_1, 0x4004 40C0) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

. 

PIO1_0. 

AD3. 

0x3~4 . 

0x5 

0x6 

PWM0_4. 

PWM1_4. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 


XN62Lxxx 

8 - . 0 

9 DRV . 0 

0 2mA . 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.5 PIO1_2 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

PIO1_2. 

SWDIO. 

AD4. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 


XN62Lxxx 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.6 PIO1_3 IOCON 


 

2:0 FUNC . 

WAKEUP 

000 

0x0 

0x1 

PIO1_3. 

AD5. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 


XN62Lxxx 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.7 PIO1_4 IOCON 

Table 5-96: PIO1_4 (PIO1_4, 0x4004 40CC) 

 

2:0 FUNC . 000 

0x0 

0x1 

PIO1_4. 

AD6. 

0x2~4 . 

0x5 

0x6 

PWM0_5. 

PWM1_5. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 


XN62Lxxx 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - -. 0 

5.7.2.8 PIO1_5 IOCON 

Table 5-97: PIO1_5 (PIO1_5, 0x4004 40D0) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

PIO1_5. 

AD7. 

CT16B1_CAP0. 

CT16B1_MAT0. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 


XN62Lxxx 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.9 PIO1_6 IOCON 

Table 5-98: PIO1_6 (PIO1_6, 0x4004 40D4) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

PIO1_6. 

CT16B1_CAP1. 

CT16B1_MAT1. 

0x3~4 . 

0x5 

PWM_FAULT1. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 


XN62Lxxx 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.10 PIO2_0 IOCON 

Table 5-99: PIO2_0 (PIO2_0, 0x4004 4070) 

Z` 

2:0 FUNC . 000 

0x0 

0x1 

PIO2_0. 

CT16B0_CAP0. 

0x2~3 . 

0x4 

0x5 

0x6 

CT16B0_MAT0. 

. 

PWM1_0. 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 

5 - . 0 

6 INV 0 


XN62Lxxx 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.11 PIO2_1 IOCON 

Table 5-100: PIO2_1 (PIO2_1, 0x4004 4074) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

PIO2_1. 

CT16B0_CAP1. 

. 

CT16B0_MAT1. 

RXD0. 

PWM_FAULT2. 

PWM1_1. 

3 - - 0 

4 MODE 

(). 1 

0 . 

1 . 


XN62Lxxx 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - - . 1 

8 - - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.12 PIO2_2 IOCON 

Table 5-101: PIO2_2 (PIO2_2, 0x4004 4078) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

PIO2_2. 

. 

CT16B1_CAP0. 

CT16B1_MAT0. 

TXD0. 

PWM_FAULT3. 

PWM1_2. 

3 - 0 

4 MODE 

(). 1 


XN62Lxxx 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 

5.7.2.13 PIO2_3 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

PIO2_3. 

. 

CT16B1_CAP1. 

CT16B1_MAT1. 

0x4~5 . 

0x6 

PWM1_3. 

3 - 0 


XN62Lxxx 

4 MODE 

(). 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 

5.7.2.14 PIO2_4 IOCON 

Table 5-103: PIO2_4 (PIO2_4, 0x4004 4080) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO2_4. 

. 

CT32B0_CAP0. 

CT32B0_MAT0. 

. 

PWM1_4. 


XN62Lxxx 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.15 PIO2_5 IOCON 

Table 5-104: PIO2_5 (PIO2_5, 0x4004 4084) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

PIO2_5. 

. 

CT32B0_CAP1. 

CT32B0_MAT1. 

. 


XN62Lxxx 

0x5 

PWM1_5. 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 

5.7.2.16 PIO2_6 IOCON 

Table 5-105: PIO2_6 (PIO2_6, 0x4004 4088) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

PIO2_6. 

. 

CT32B0_CAP2. 

CT32B0_MAT2. 


XN62Lxxx 

0x4 

0x5 

0x6 

. 

PWM2_4. 

TXD2. 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.17 PIO2_7 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

PIO2_7. 

. 


XN62Lxxx 

0x2 

0x3 

0x4 

0x5 

0x6 

CT32B0_CAP3. 

CT32B0_MAT3. 

. 

PWM2_5. 

RXD2. 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - . 1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - . 0 

5.7.2.18 PIO2_8 IOCON 

Table 5-107: PIO2_8 (PIO2_8, 0x4004 40E0) 

 

2:0 FUNC . 000 


XN62Lxxx 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO2_8. 

. 

CT32B1_CAP0. 

CT32B1_MAT0. 

AD8 

PWM2_6. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 


XN62Lxxx 

5.7.2.19 PIO2_9 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO2_9. 

. 

CT32B1_CAP1. 

CT32B1_MAT1. 

AD9 

PWM2_7. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 








XN62Lxxx 

0x6 


31:16 - - . 0 

5.7.2.20 PIO2_10 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO2_10. 

. 

CT32B1_CAP2. 

CT32B1_MAT2. 

AD10. 

TXD1. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 

0x2 





XN62Lxxx 

0x3 

0x4 

0x5 

0x6 





31:16 - - . 0 

5.7.2.21 PIO2_11 IOCON 

Table 5-110: PIO2_11 (PIO2_11, 0x4004 40EC) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

PIO2_11. 

. 

CT32B1_CAP3. 

CT32B1_MAT3. 

AD11. 

RXD1. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 ADMODE 

1 

0 

1 

8 - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 


XN62Lxxx 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 








31:16 - - . 0 

5.7.2.1 PIO2_12 IOCON 


 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

PIO2_12. 

. 

PWM2_0. 

RXD1. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - - 1 

8 - - 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 

000 

0x0 



XN62Lxxx 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 







31:16 - -. 0 

5.7.2.2 PIO2_13 IOCON 

Table 5-112: PIO2_13 (PIO2_13, 0x4004 4030) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

0x3 

PIO2_13. 

. 

PWM2_1. 

TXD1. 

3 - - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 - - . 1 

8 - - . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 




XN62Lxxx 

0x2 

0x3 

0x4 

0x5 

0x6 






31:16 - - . 0 

5.7.2.3 PIO2_14 IOCON 

Table 5-113: PIO2_14 (PIO2_14, 0x4004 4034) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

PIO2_14. 

 

PWM2_2. 

0x3~4 

0x5 

TXD3. 

3 - 0 

4 MODE 

() 

. 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 . 1 

8 . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 




XN62Lxxx 

0x2 

0x3 

0x4 

0x5 

0x6 






31:16 - - . 0 

5.7.2.4 PIO2_15 IOCON 

Table 5-114: PIO2_15 (PIO2_15, 0x4004 4038) 

 

2:0 FUNC . 000 

0x0 

0x1 

0x2 

PIO2_15. 

. 

PWM2_3. 

0x3~5 . 

0x6 

RXD3. 

3 - 0 

4 MODE 

(). 1 

0 . 

1 . 

5 - . 0 

6 INV 0 

0 . 

1 . 

7 . 1 

8 . 0 

9 DRV . 0 

0 

1 

. 

10 OD 0 

0 

1 

12:11 S_MODE 00 

0x0 

0x1 

0x2 

0x3 

 

1 

1 

2 

2 

3 

3 

15:13 CLK_DIV 000 

0x0 

0x1 




XN62Lxxx 

0x2 

0x3 

0x4 

0x5 

0x6 






31:16 - . 0 


XN62Lxxx 

6 PWM 

6.1 

XN62L 3 

PWM0PWM1PWM2 

 

4 8 

 

PWM 2 

4 

0~100% 

 

PWM 32 

2 PWM PWM_PCLK() 

PWM 

PWM 

PWM PWM 

ADC GPIO 

PWM 

PWM 

8 

PWM 

A/D 

6.1.1 

• 3 

• System Clock 

• 24 PWM 

– 

– 

– 

• 

– / 

– 

– 

PWM – 

• PWM 

• 32 

• 

• 1 16 

• 

PWM • 8 

• 


XN62Lxxx 

• PWM 

• PWM 

– PWM 

– GPIO 

– 

– ADC 

6.1.2 

Figure 6-1 PWMn (n=0,1,2) 

PCLK 

Edge or Center 

Align 

Control 

PWM Counter 

Modulus 

Prescaler 

PWM Counter 

PWM Control 

Sources 

-ADC 

-GPIO 

-Timer 

PWM Value 

Register 0 

Compare Unit 0 

PWM 0 

PWM Value 

Register 1 


PWM 1 

PWM Value 

Register 2 

PWM Value 

Register 3 

PWM Value 

Register 4 

PWM Value 

Register 5 





MUX/SWAP 

/DEADTIME 

Insertion and 

Output Control 

PWM Fault Protection 

Polarity Control 

PWM Channel Mask 

PWM 2 

PWM 3 

PWM 4 

PWM 5 

PWM Value 

Register 6 


PWM 6 

PWM Value 

Register 7 


PWM 7 

PWM Compare 

Output 

Polarity Control 

Software Control 

and Output Mode 

Setting 

Fliters Fault Input [3:0] 

Figure 6-1: PWMn(n=0,1,2) 


XN62Lxxx 

6.2 

PWM 

Table 6-1: PWM 

 

PWM0_0 ~ PWM0_7 PWM0 



PWM_FAULT0 ~ PWM_FAULT3 

PWM 6.3 

 


( 0x4005 8000 PWM0/0x4005 C000 PWM1/0x4006 0000 PWM2) 

 

CTRL R/W 0x000 0x0 

FCTRL R/W 0x004 0x0 

FLTACK R/W 0x008 0x0 

OUTCTRL R/W 0x00C 

0x0 

CNTR RO 0x010 0x0 

CMOD R/W 0x014 0x0 

VAL0 R/W 0x018 0 0x0 

VAL1 R/W 0x01C 1 0x0 

VAL2 R/W 0x020 2 0x0 

VAL3 R/W 0x024 3 0x0 

VAL4 R/W 0x028 4 0x0 

VAL5 R/W 0x02C 5 0x0 

VAL6 R/W 0x030 6 0x0 

VAL7 R/W 0x034 7 0x0 

DTIM0 R/W 0x038 0 0xFFF 

DTIM1 R/W 0x03C 1 0xFFF 

DMAP1 R/W 0x040 

1 0x0 

DMAP2 R/W 0x044 

2 0x0 

CNFG R/W 0x048 0x0 

CCTRL R/W 0x04C 0x0 

PORT R/W 0x050 

0x0 

ICCTRL R/W 0x054 

. 0x0 

SCTRL R/W 0x058 0x0 

TMRSEL R/W 0x05C PWM 0x0 


XN62Lxxx 

PCR R/W 0x060 0x0 

CNTRINI WO 0x064 0x0 

DELAYST R/W 0x068 PWMnPWM(n+1) 

0x0 


XN62Lxxx 

6.3.1 PWM 

Table 6-3 PWM (CTRL) 

 

0 PWMEN PWM 0 

0 PWM 

PWM 

OUTCTLm =1 

1 PWM 

1 LDOK 

CTRL 

PRSC CMOD 

VALm 0 

PWM 

CTRL 

CMOD 

VALm PWM 

LDOK 

1 

PWM 

LDOK 

0 

0 0 

1 CTRL 

CMOD 

VALm PWM 

2 PWMF 

1 PWMF 0 0 

0 

0 : PWMF 

PWMF 

0 PWMF 

1 PWMF 

3 PWMRIE PWMF 0 

0 PWMF 

1 PWMF 

4 - - 0 

6:5 PRSC - PWM 

00 

: PRSC 

LDOK 1 PWM 

00 PWM 

01 PWM /2 

10 PWM /4 

11 PWM /8 

7 IPOL0 PWMn_0 PWMn_1 

PWM 0 

0 PWM 

VAL0 

1 PWM 

VAL1 


PWM 0 

0 PWM 

VAL2 

1 PWM 

VAL3 


PWM 0 

0 PWM 

VAL4 

1 PWM 

VAL5 


PWM 0 

0 PWM 

VAL6 


XN62Lxxx 

1 PWM 

VAL7 

11 HALF 

0 

0 

1 

15:12 LDFQ - PWM 

LDFQ / 

PWM 

HALF 0000 

: LDOK LDFQ 

 

LDFQ 

0000 PWM 

0001 2 PWM 

0010 3 PWM 

0011 4 PWM 

0100 5 PWM 

0101 6 PWM 

0110 7 PWM 

0111 8 PWM 

1000 9 PWM 

1001 10 PWM 

1010 11 PWM 

1011 12 PWM 

1100 13 PWM 

1101 14 PWM 

1110 15 PWM 

1111 16 PWM 

16 SOFTFAULT 0 

0 

1 

17 INIDIR 0 

0 PWM 

1 PWM 

18 LDOUTEN 

24 31 0 

23~19 - - 

timerADC 

0 

1 

24 CH0OUTEN 0 

0 

0 

1 


0 

0 

1 


XN62Lxxx 


0 

0 

1 


0 

0 

1 


0 

0 

1 


0 

0 

1 


0 

0 

1 


0 

0 

1 

6.3.2 PWM 

Table 6-4 PWM (FCTRL) 

 

0 FMODE0 / PWM_FAULT0 . 0 

0 

1 

1 FIE0 PWM_FAULT0 0 

0 

1 


0 

1 


0 

1 


0 

1 


0 

1 


XN62Lxxx 


0 

1 


0 

1 

8 FMODE4 / 

0COMPARATOR0 

. 0 

0 

1 

9 FIE4 0COMPARATOR0 0 

0 

1 

10 FMODE5 / 

1COMPARATOR1 

. 0 

0 

1 

11 FIE5 1COMPARATOR1 0 

0 

1 

12 FMODE6 /(CTRL 

SOFTFAULT) . 0 

0 

1 

13 FIE6 (CTRL SOFTFAULT) 0 

0 

1 

31:14 - - 0 

6.3.3 PWM 

Table 6-5 PWM (FLTACK) 

 

0 FTACK0 - 1 FFLAG00 

0RE 

SET FTACK0 . 0 

PWM PWM 

PWM 

 

PWM 1 FTACK1 - 1 FFLAG10 

0RESET 

FTACK1 . 

PWM PWM 

PWM 

 


0 RESET FTACK2 . 0 

PWM PWM 

PWM 

 


0RESET 

FTACK3 . 0 

PWM PWM 

PWM 


XN62Lxxx 

 

PWM 4 FTACK4 1 FFLAG40 

0RESET 

FTACK4 . 

PWM PWM 

PWM 

 


0RESET 

FTACK5 . 0 

PWM PWM 

PWM 

 


0RESET 

FTACK6 . 0 

PWM PWM 

PWM 

 


0RESET 

FTACK7 . 0 

PWM PWM 

PWM 

 

PWM 15:8 - 0 

16 FFLAG0 

PWM_FAULT0 

2 PWM 

10 

FTACK0 1 FFLAG0 

0 PWM_FAULT0 

1 PWM_FAULT0 

17 FPIN0 

PWM_FAULT0 0 

0 0 PWM_FAULT0 


18 FFLAG1 

PWM_FAULT1 

2 PWM 

10 


0 PWM_FAULT1 

1 PWM_FAULT1 

19 FPIN1 

PWM_FAULT1 0 



20 FFLAG2 

PWM_FAULT2 

2 PWM 

10 


0 PWM_FAULT2 

1 PWM_FAULT2 

21 FPIN2 

PWM_FAULT2 0 



22 FFLAG3 

PWM_FAULT3 

2 PWM 

10 


0 PWM_FAULT3 

1 PWM_FAULT3 

23 FPIN3 

PWM_FAULT3 0 


XN62Lxxx 



24 FFLAG4 

0COMPARATOR0 

2 PWM 0 

1FTACK4 1 FFLAG4 

0 

0COMPARATOR0 

1 

0COMPARATOR0 

25 FPIN4 

0COMPARATOR0 0 

0 0COMPARATOR0 0 


26 FFLAG5 

1COMPARATOR1 

2 PWM 0 


0 

1COMPARATOR1 

1 

1COMPARATOR1 

27 FPIN5 

1COMPARATOR1 0 



28 FFLAG6 (CTRL 

SOFTFAULT) 2 PWM 0 


0 

1 

3129 - - 0 

6.3.4 PWM 

 

PWMn 0~7 

(OUTCTL m) PWMn_m OUTm 

 

OUTCTL 

Table 6-6 PWM (OUT CTRL; n=0,1.2) 

 

0 OUT0 PWMn_0 0 

0 0 

1 1 


0 0 

1 1PWM n_0 

n_1 


0 0 

1 1 


0 0 

1 1PWM n_2 

n_3 


XN62Lxxx 


0 0 

1 1 


0 0 

1 1PWM n_4 

n_5 


0 0 

1 1 


0 0 

1 1PWM n_6 

n_7 

8 OUTCTL 0 PWMn_0 0 

0 

1 


0 

1 


0 

1 


0 

1 


0 

1 


0 

1 


0 

1 

15 OUTCTL7 PWMn_7 0 

0 

1 

31:16 - - 0 

6.3.5 PWM 

Table 6-7 PWM (CNTR) 


XN62Lxxx 

 

31:0 CNT - 

PWM 

PWM 

PWMEN 1 0 

 

6.3.6 PWM 

PWM 

PWM 

LDOK 1 PWM 

CMOD 

PWM . 

Table 6-8 PWM (CMOD;) 

 

31:0 CMOD - 32 

PWM 

0 

6.3.7 PWM 

32 

PWM 

0PWM PWM 

0 

PWM CMOD 

PWM PWM 

1 

Table 6-9 PWM (VALm, m=0~7) 

 

31:0 VAL - PWM s 0 

6.3.8 PWM 

DTIM0 PWM 

0 1 

DTIM1 PWM 

1 0 

 

 

PWM PRSC 

DT=P × DTIMm – 1 PWM 

P PRSC 

DTIMm 

PWM PRSC 

2 

DTIMm 5 

DT = 2 × 5 - 1 = 9 PWM 

 

P=1DT=DTIMm 

Table 6-10 PWM (DTIMm, m=0,1) 

 

31:0 DTIMm - 

32 

PWM 0xFFFFFFFF 

6.3.9 PWM 

 

PWM DMAP1-2 

1 CNFG WP 1 DMAP1-2 


XN62Lxxx 

Table 6-11: PWM (DMAP1) 

1 

 

0 P0FLTMAP0 0PWM_FAULT0 

0 1 

0 

1 


0 1 

0 

1 


0 1 

0 

1 


0 1 

0 

1 

4 P0FLTMAP4 0 COMPARATOR0 

PWM 0 1 

0 

1 

5 P0FLTMAP5 1 COMPARATOR1 

PWM 0 1 

0 

1 

6 P0FLTMAP6 

PWM 0 1 

0 

1 

7 - - 1 

15:8 P1FLTMAPn PWM 1 

PWM 0F0FLTMAPn 





0xFF 

0xFF 

0xFF 

Table 6-12: PWM (DMAP1) 

2 

 









0xFF 

0xFF 

0xFF 

0xFF 

6.3.10 PWM 

 

PWM CNFG WP 1 

Table 6-13: PWM (CNFG) 

 


XN62Lxxx 

0 WP PWM 

0 

CNFG 

 

DMAP1–2, DTIM, CNFG, CCTRL ENHA 

ENHA VLMODE, SWP67, SWP45, SWP23, CCTRL 

SWP01 

: CNFG WP 1 

 

0 

1 

1 NDEP01 

PWMn 0-1 

0 

0 

1 

2 NDEP23 

PWMn 2-3 

0 

0 

1 

3 NDEP45 

PWMn 4-5 

0 

0 

1 

4 NDEP67 

PWMn 6-7 

0 

0 

1 

5 BOTNEG01 

PWMn 1 0 

0 

1 

6 BOTNEG23 

PWMn 3 0 

0 

1 

7 BOTNEG45 

PWMn 5 0 

0 

1 

8 BOTNEG67 

PWMn 7 0 

0 

1 

9 TOPNEG01 

PWMn 0 0 

0 

1 

10 TOPNEG23 

PWMn 2 0 

0 

1 

11 TOPNEG45 

PWMn 4 0 


XN62Lxxx 

0 

1 

12 TOPNEG67 

PWMn 6 0 

0 

1 

13 EDG 

PWMn 

0 

 

0 

1 

31:14 - - 0 

6.3.11 PWM 

 

PWM 

ENHA VLMODE, SWP67, SWP45, SWP23 SWP01 

ENHA 

 

CNFG WP 

Table 6-14: PWM (CCTRL , n=0,1.2) 

 

0 SWP01 ENHA 0 PWM 

0-1 0 

0 

1 PWM 0-1 

1 SWP23 ENHA 0 

PWM 2-3 0 

0 

1 PWM 2-3 


PWM 4-5 0 

0 

1 PWM 4-5 


PWM 6-7 0 

0 

1 PWM 6-7 

5:4 VLMODE PWM 

ENHA 0 

00 

00 VAL0~7 

PMW0~7 01 VAL0 

PMW0~5 

10 VAL0 

PMW0~3 

11 VAL0 

PMW0~7 

6 MSK0 PWM 0 0 

0 

1 0 


0 

1 1 


XN62Lxxx 


0 

1 2 


0 

1 3 

10 MSK4 PWM 4 0 

0 

1 4 

11 MSK5 PWM 5 0 

0 

1 5 

12 MSK6 PWM 6 0 

0 

1 6 

13 MSK7 PWM 7 0 

0 

1 7 

14 - 0 

15 ENHA 

VLMODE, SWP67, SWP45, SWP23, SWP01 

0 

 

CNFG WP 1 . 

0 VLMODE, SWP67, SWP45, SWP23 SWP01 

1 VLMODE, SWP67, SWP45, SWP23 SWP01 

31:16 - - 0 

6.3.12 PWM 

Table 6-15: PWM (FPORTCTRL , n=0,1.2) 

 

7:0 FAULTPORT PWM 8 1 

0 

 

8 FAULTVAL0 PWM FPSEL=1 PWM 0 0 

0 0 

1 1 


0 0 

1 1 


0 0 

1 1 


0 0 


XN62Lxxx 

1 1 


0 0 

1 1 


0 0 

1 1 


0 0 

1 1 


0 0 

1 1 

16 FPSEL0 PWM 

FAULTVAL0 PWM 0. 0 

0 PWM 

1 FAULTVAL0 PWM 



0 PWM 




0 PWM 




0 PWM 




0 PWM 




0 PWM 




0 PWM 




0 PWM 


31:24 - - . NA 


XN62Lxxx 

6.3.13 PWM 

 

IPOLm Valm PWM Table 6-16: PWM (ICCTRL, n=0,1.2) 

 

0 ICC0 PWM 0-1 . 0 

0 IPOL0 VAL0 VAL1 

1 PWM 

VAL0 PWM 

VAL1 1 ICC1 PWM 2-3 . 0 


1 PWM 

VAL2 PWM 

VAL3 2 ICC2 PWM 4-5 . 0 


1 PWM 

VAL4 PWM 

VAL5 3 ICC3 PWM 6-7 . 0 


1 PWM 

VAL6 PWM 

VAL7 4 PAD_EN PWM 

PWM 

0 

PWM 

0 

1 

31:5 - - . 0 

6.3.14 PWM 

 

PWM 

CNFG WP 

WP 0 

Table 6-17: PWM (SCTRL; n=0,1.2) 

 

1:0 SRC0 PWMn_0/PWMn_1 

OUTCTL0 OUTCTL1 0 

( OUT 8,9 ) 1 

00 PWM 

01 ADC0 LOWLMT0 HILMT0 

HILMT0 0 1 PWMn_0 1PWMn_1 0 

LOWLMT0 0 1 PWMn_0 0PWMn_1 

10 GPIO0_20 

11 TMRSEL [1:0] 

/ 

0Match0 


XN62Lxxx 

 

Match 0 

PWMn_0 0PWMn_1 1 




( OUT 10,11 ) 1 

000 PWM 



LOWLMT1 0 1 PWMn_2 0PWMn_ 3 1 

010 GPIO0_19 

011 TMRSEL [3:2] 

/ 

0Match0 

 

Match 0 PWMn_2 0PWMn_3 1 


1xx 

SRC0 



( OUT 12,13 ) 1 

000 PWM 



LOWLMT0 0 1 PWMn_4 0PWMn_5 1 

010 GPIO0_2 

011 TMRSEL [5:4] 

/ 

0Match0 

 



1xx 

SRC0 



( OUT 14,15 ) 1 

000 PWM 



LOWLMT1 0 1 PWMn_6 0PWMn_7 1 

010 GPIO0_1 

011 TMRSEL [7:6] 

/ 

0Match0 

 



1xx 

SRC0 

31:11 - - 0 

6.3.15 PWM 

Table 6-18: PWM TMR (TMRSEL) 

 

1:0 SRC0TMSEL PWM 0,1 0 


XN62Lxxx 

0 TMR32B0 0 

1 TMR32B1 0 

2 TMR16B0 0 

3 TMR16B1 0 


0 TMR32B0 0 

1 TMR32B1 0 

2 TMR16B0 0 

3 TMR16B1 0 


0 TMR32B0 0 

1 TMR32B1 0 

2 TMR16B0 0 

3 TMR16B1 0 


0 TMR32B0 0 

1 TMR32B1 0 

2 TMR16B0 0 

3 TMR16B1 0 

31:8 - - 0 

6.3.16 PWM 

Table 6-19: PWM (PSCR ; n=0,1.2) 

 

0 CINV0 PWM 0 0 

0 CNTR 

VAL0 

1 CNTR 

VAL0 


0 CNTR 

VAL1 

1 CNTR 

VAL1 


0 CNTR 

VAL2 

1 CNTR 

VAL2 


0 CNTR 

VAL3 

1 CNTR 

VAL3 


0 CNTR 

VAL4 

1 CNTR 

VAL4 



XN62Lxxx 

0 CNTR 

VAL5 

1 CNTR 

VAL5 


0 CNTR 

VAL6 

1 CNTR 

VAL6 


0 CNTR 

VAL7 

1 CNTR 

VAL7 

31:8 - - 0 

6.3.17 PWM 


(CNTRINI) 

 

31:0 INITVAL PWM 

PWM PWM 0 

 

PWM 

6.3.18 PWM 

PWM 

PWM 0 PWM 1PWM 2 PWM 3… PWM0 PWM1 

 


(DELAYST; n=0.1) 

 

30:0 DLYTIME 31 

PWM 0 

31 TRIG_EN PWM n n+1 0 

0 

1 

6.4 

6.4.1 

PWM PWM 

PWMn_PCLK (System Clock)12,4,8 CTRL 

PRSC 

LDOK 1 PWM PWM 

. 

6.4.2 PWM 

PWM 

32 

PWM PWM 


XN62Lxxx 

6.4.2.1 

PWM Edge 

-AlignCenter 

-Aligned PWM CNFG 

 

PSCR CINVm PWM 

• VALm PWM 

CINVm=0PWM 

CINVm=1PWM 

 

• VALm 

PWM 

CINVm=0PWM 

CINVm=1 

PWM 

Alignment Reference 

Up/Down Counter 

Modulus =4 

PWM Compare Output 

Duty Cycle = 50% 

CINVx = 0 

CINVx = 1 

Figure 6-2: PWM 

: 

PWM modulu 

0 

 

6.4.2.2 

PWM 

CMOD PWM 

/ 

 

 

2 PWM 

CMOD PWM 

 

PWM = (PWM ) × (PWM ) × 2 

4 

3 

Up/Down Counter Modulus = 4 

PWM Clock Period 

2 

1 

0 

PWM Period = 8 x PWM Clock Period 


PWM 

PWM 

1 

PWM 

 

CMOD PWM 

PWM = (PWM ) × (PWM ) 


XN62Lxxx 

4 

3 

2 

Up Counter Modulus = 4 

PWM Clock Period 

1 

0 

PWM Period = 8 x PWM Clock Period 


6.4.2.3 

PWM 

32 PWM 

CINVx=1 

 

PWM PWM 

: PWM 

PWM CINVx=0PWM 

 

CINVx=0 

PWM PWM 

PWM 

0CINVx=0 PWM PWM 

CINVx=1 

PWM 

PWM 

Figure 6-5 PWM 

2 PWM 

PWM 

PWM = (PWM ) ) × (PWM 

× 2 


2 

Modulus = 4 1 

PWM Value = 0 

0/4 = 0% 

PWM Value = 1 

1/4 = 25% 

PWM Value = 2 

2/4 = 50% 

PWM Value = 3 

3/4 = 75% 

PWM Value = 4 

4/4 = 100% 

4 

3 

0 

Figure 6-5: 

 


PWM 

PWM 

PWM = (PWM ) ) 

× (PWM 


XN62Lxxx 

Up Counter 

2 

Modulus = 4 1 

PWM Value = 0 

0/4 = 0% 

PWM Value = 1 

1/4 = 25% 

PWM Value = 2 

2/4 = 50% 

PWM Value = 3 

3/4 = 75% 

PWM Value = 4 

4/4 = 100% 

4 

3 

Figure 6-6: 

6.4.3 

CNFG INDEPm PWM 

INDEPm 1 PWM 0 -1,2-3,4-5,6-7 

 

PWM 

PWM 

INDEPm 0 PWM 0 -1,2-3,4-5,6-7 

PWM 

Figure 6-7 . 

VAL 0 

Register 

VAL 1 

Register 

PWM CHANNELS 0 AND 1 

TOP 

BOTTOM 

VAL 2 

Register 

VAL 3 

Register 


TOP 

BOTTOM 

VAL 4 

Register 

VAL 5 

Register 


TOP 

BOTTOM 

VAL 6 

Register 

VAL 7 

Register 


TOP 

BOTTOM 

Figure 6-7: 

PWM 

Figure 6-8 


XN62Lxxx 

PWM 

0 

PWM 

2 

PWM 

4 

AC 

Inputs 

3-Phase 

Load 

PWM 

1 

PWM 

3 

PWM 

5 

Figure 6-8: 

PWM 

 

1. 

2. 

PWM 

3. 

PWM 

6.4.4 

PWM 

 


PWM 

 

 

 

PWM PWM 

DTIMx 

 

PWM 

PWM 

DTIM0 PWM 

DTIM1 PWM 

PWM / 

PWM 

Generator 

Current 

Status 

OUT0 

PWM0 & 

PWM1 

OUT2 

PWM2 & 

PWM3 

OUT4 

PWM4 & 

PWM5 

OUT6 

PWM6 & 

PWM7 

MUX 

OUTCLT0 

MUX 

OUTCLT2 

MUX 

OUTCLT4 

MUX 

OUTCLT6 

OUT1 

Deadtime 

Generator 

OUT3 

Deadtime 

Generator 

OUT5 

Deadtime 

Generator 

OUT7 

Deadtime 

Generator 

Top/Bottom 

Generator 

Top/Bottom 

Generator 

Top/Bottom 

Generator 

Top/Bottom 

Generator 

Top(PWM0) 

Bottom(PWM1) 

Top(PWM2) 

Bottom(PWM3) 

Top(PWM4) 

Bottom(PWM5) 

Top(PWM6) 

Bottom(PWM7) 


XN62Lxxx 

Figure 6-9: 

Figure 6-10, Figure 6-11, Figure 6-12 

Modulus = 4 

PWM Value = 2 

PWM 0, No Deadtime 


PWM 0, Deadtime = 1 


Figure 6-10: 

Modulus = 3 

PWM Value = 1 PWM Value = 1 PWM Value = 3 PWM Value = 3 





Figure 6-11: 

Modulus = 3 

PWM 

Value = 2 

PWM 

Value = 3 

PWM 

Value = 2 

PWM 

Value = 1 





Figure 6-12: 

6.4.4.1 

 

 

 

 

Figure 6-13 


XN62Lxxx 

Desired 

Load Voltage 

Deadtime 

PWM To Top 

Transistor 

V+ 

Positive 

Current Direction 

PWM To Bottom 

Transistor 

Positive Current 

Load Voltage 

Negative Current 

Load Voltage 

Negative 

Current Direction 

Figure 6-13: 

 

 

 

 

 

 

 

PWM 

 

 

VALm 

 

 

• ICCTRL ICC 0IPOL n 

• ICCTRL ICC 1 

VALn 

• 

VALn • 

VALn : 

ICCn 0 CTRL IPOL0–IPOL2 

/ 

PWM 

Table 6-21: / 

 

IPOL0 

IPOL1 

IPOL2 

IPOL3 

0 PWMnVAL0 PWMn_0/ PWMn_1 








: IPOLn 

PWM 

PWM 

IPOLn PWM 

LDOK IPOL 

n 


XN62Lxxx 

 

Figure 6-14 Figure 6-15 

Deadtime 

Desired Load Voltage 

Top PWM 

Bottom PWM 

Load Voltage 

Figure 6-14: 

Deadtime 

Desired Load Voltage 

Top PWM 

Bottom PWM 

Load Voltage 

Figure 6-15: 

6.4.5 PWM 

PWM 

PWM 

 

PWM 

PWM PWM 

PWM 

PWM PWM 

PWM 

PWM Table 6-22: ICCn / 

 

ICC0 

ICC1 

ICC2 

ICC3 

0 IPOL0 PWMn_0/ PWMn_1 

1 PWM 

PWMn_0/ PWMn_1 


1 PWM 



1 PWM 



1 PWM 


: ICCTRL ICCn PWM 

PWM 150 www.xinnovatech.com

XN62Lxxx 

4 

3 

2 


Modulus =4 

Even PWM 

Value = 1 

Odd PWM 

Value = 3 

1 

0 

Even PWM 

Value 

Odd PWM 

Value 

Even PWM 

Value 

Odd PWM 

Value 

Even PWM 

Value = 3 

Odd PWM 

Value = 1 

Figure 6-16: – PWM 

6.4.6 PWM 

PWM 

1. TOPNEGnn PWM PWMn_0, PWMn_2, PWMn_4 PWMn_6 

TOPNEGnn 

2. BOTNEGnn PWM PWMn_1, PWMn_3, PWMn_5 PWMn_7 

BOTNEGnn 

TOPNEGnn BOTNEGnn 

CNFG Figure 6-17 

Center-Aligned 

Positive PWM Output Polarity 

Edge-Aligned 

Positive PWM Output Polarity 


Modulus = 4 

PWM = 0 

PWM = 1 

PWM = 2 

PWM = 3 

PWM = 4 

Up Counter 

Modulus = 4 

PWM = 0 

PWM = 1 

PWM = 2 

PWM = 3 

PWM = 4 

Center-Aligned 

Negative PWM Output Polarity 

Edge-Aligned 

Negative PWM Output Polarity 


Modulus = 4 

PWM = 0 

PWM = 1 

PWM = 2 

PWM = 3 

PWM = 4 

Up Counter 

Modulus = 4 

PWM = 0 

PWM = 1 

PWM = 2 

PWM = 3 

PWM = 4 



XN62Lxxx 

6.4.7 

(OUTCTRL 

n) PWM 

PWM 

OUTCTRLm=1 OUTm PWMn_m / 

OUTm 

PWM OUTCTRL 

m OUTm 

PWM 

OUT 

 

TOPNEGmm BOTNEGmm 

Modulus = 4 

PWM Value = 2 

Deadtime = 1 

PWM 0 Generator 

PWM 1 Generator 

OUTCTL0 

OUT0 

OUT1 

PWM 0 with Deadtime 

PWM 1 with Deadtime 

OUTCTL0 is Cleared 

Toggling OUT0 with OUTCTL0 

Set 

Toggling OUT1 with 

OUTCTL0 Set and 

OUT0 Clear 

Setting OUTCTL0 with OUT0 Set 

Figure 6-18: 

6.4.8 PWM 

6.4.8.1 

LDOK 

PWM 

• PWM (CTRL) PRSC 

• (CMOD) PWM 

• VALm 

PWM 

LDOK 

PWM LDOK 

PWM 

 

PWM 

LDOK 0 

6.4.8.2 

CTRL LFQ 

PWM 1 16 

PWM 

LDOK LDFQ CTRL 

HALF 

HALF 

HALF 

. 

:modulu 

PWM 

 


XN62Lxxx 

Up/Down 

Counter 

Reload 

Change 

Reload 

Frequency 

To Every 

Two Opportunities 

To Every 

Four Opportunities 

To Every 

Opportunities 

Figure 6-19: 

Up/Down 

Counter 

Reload 

Change 

Reload 

Frequency 

To Every 

Two Half 

Opportunities 

To Every 

Four Half 

Opportunities 

To Every Half 

Opportunities 

To Every 

Two Half 

Opportunities 

Figure 6-20: 

6.4.8.3 

PWM 

LDOK CTRL 

PWM (PWMF) 

(PWMRIE) PWMF 

PWMF 

PWMF 0 PWMF Half = 0, LDFQ[3:0] = 0000 = Reload Every Cycle 

Up/Down 

Counter 

LDOK = 1 

Modulus = 3 

PWM Value = 1 

PWMF = 1 

0 

3 

2 

1 

1 

3 

2 

1 

0 

3 

1 

1 

PWM 


Half = 0, LDFQ[3:0] = 0000 = Reload Every Cycle 

Up/Down 

Counter 

0 

1 

3 

2 2 2 

1 1 1 1 1 

0 0 0 0 

LDOK = 1 

Modulus = 2 

PWM Value = 1 

PWMF = 1 

1 

3 

1 

1 

1 

2 

1 

1 

1 

1 

1 

1 

0 

2 

1 

1 

PWM 



XN62Lxxx 

Half = 1, LDFQ[3:0] = 0000 = Reload Every Half Cycle 

Up/Down 

Counter 

LDOK = 1 

Modulus = 3 

PWM Value = 1 

PWMF = 1 

1 

3 

2 

1 

0 

3 

2 

1 

0 

3 

2 

1 

1 

3 

1 

1 

1 

3 

3 

1 

0 

3 

3 

1 

1 

3 

1 

1 

PWM 


 

Half = 1, LDFQ[3:0] = 0000 = Reload Every Half Cycle 

Up/Down 

Counter 

LDOK = 1 

Modulus = 2 

PWM Value = 1 

PWMF = 1 

0 

2 

1 

1 

0 

2 

1 

1 

1 

4 

1 

1 

0 

4 

1 

1 

1 

1 

1 

1 

0 

2 

1 

1 

1 

4 

1 

1 

PWM 


 

LDFQ[3:0] = 0000 = Reload Every Cycle 

Up only 

Counter 

LDOK = 1 

Modulus = 3 

PWM Value = 1 

PWMF = 1 

0 

3 

2 

1 

1 

3 

2 

1 

0 

3 

1 

1 

0 

3 

1 

1 

PWM 



XN62Lxxx 

LDFQ[3:0] = 0000 = Reload Every Cycle 

Up only 

Counter 

LDOK = 1 

Modulus = 3 

PWM Value = 2 

PWMF = 1 

1 

4 

2 

1 

1 

2 

2 

1 

0 

1 

2 

1 

PWM 


 

6.4.8.4 

PWM 

LDOK PWM 

 

6.4.8.5 PWM 

PWMEN 

LDOK LDOK=1PWMEN PWM 

PWMF 

PWMF 

PWMRIE 

IPOLn s ICCn 

PWM 

PWM 

: PWMPWMEN PWMF LDOK 1 

PWM PWMRIE 

LDOK 

PWM PWM 1PWM 1 

PWMEN 

 

LDOK ,PWM 

PWMEN OUTCTLm 

 

PWM 

Operation Clock 

PWM 

Bit 

PWM 

Pins 

HI-Z 

Active 

HI-Z 

Figure 6-27: PWMEN PWM (OUTCTL0 

-5 = 0) 


XN62Lxxx 

PWM 

Operation Clock 

PWM 

Bit 

PWM 

Pins 

HI-Z 

Active 

HI-Z 

Figure 6-28: PWMEN PWM (OUTCTL0,2,4 = 0) 

PWMEN : 

• PWMn 

OUTCTLn=1 

• PWM 

• PWM 

0 

• PWMF 

• 

• 

OUTCTLn=1 

• 

6.4.9 

PWM 

PWM 

FCTRL 

0 1 

PWM 

PWM 

PWM 

PWM 

DMAP1–2 7 

PWM 0~7 

PWM 

 

PWM 

P0FLTMAP3 P0FLTMAP2 P0FLTMAP1 P0FLTMAP0 

Fault 0 

Fault 1 

Fault 2 

Fault 3 

Disable PWM Pin 0 

Fault 4 

Fault 5 

Fault 6 

P0FLTMAP4 

P0FLTMAP5 

P0FLTMAP6 

Figure 6-29: -PWMn_0 


XN62Lxxx 

Table 6-23: 

PWM 

PWMn_0 

PWMn_1 

PWMn_2 

PWMn_3 

PWMn_4 

PWMn_5 

PWMn_6 

PWMn_7 

 

DISMAP0[7:0] 

DISMAP0[15:8] 

DISMAP0[23:16] 


DISMAP1[7:0] 

DISMAP1[15:8] 



6.4.9.1 

XN12L 4 

PWM_FAULT0 ~ PWM_FAULT3 

 

 

PWM 

FFLAGm FPINm FPINm 

 

PWM 

1FTACKm FFLAGm FIEm, PWM_FAULTn 

FFLAG 

m 

• 1 FTACKm FFLAGm 

• 0 FIEm 

• 

6.4.9.2 

 

FMODEm PWM_FAULTn 

PWM 

PWM 

PWM 

Figure 6-30FMODEm 

FFLAGm 

PWM PWM Output 

Fault Input 

PWM Enabled Disabled Enabled PWM Disabled PWM Enabled 

Figure 6-30: 

6.4.9.3 

 

0, 2, 4, 5, 6 

FFLAG PWM 

 


XN62Lxxx 

 

PWM Figure 6-31 1, 3 

FFLAGm 

PWM 

Figure 6-32 

Fault 0 

Or Fault 2 

PWMS Enabled PWMS Disabled PWMS Enabled PWMS Disabled 

FFLAGn 

Cleared 

Figure 6-31: 

0 

Fault 1 

Or Fault 3 

PWMS Enabled PWMS Disabled PWMS Enabled 

FFLAGn 

Cleared 

Figure 6-32: 

1 

• PWM 

PWM 

PWM 

• OUTCTL 

m 1 

PWM PWMEN=1 

 

PWM PWMEN=0 

OUTm PWM 

PWM 

 

6.4.10 

PWM : 

• (PWMF)—PWMF PWM 

(PWMRIE) PWMF PWMF 

PWMRIE PWM 

(CTRL) 

• (FFLAG0 –FFLAG6)— FFLAGm PWM_FAULTn 

1 FIE0–FIE6 

FFLAGm 

FFLAG0–FFLAG6 (FLTAC 

FIE0–FIE6 FCTRL 


XN62Lxxx 

7 GPIO 

7.1 

XN62L 55 GPIO 

• 

• 

• 

• 

• 

• 

• GPIO . 

7.2 

Table 7-1: GPIO 

GPIO LQFP48 LQFP64 

GPIO0 PIO0_0 ~ PIO0_31 31:0 

GPIO1 PIO1_0 ~ PIO1_6 6:0 

GPIO2 PIO2_0 ~ PIO2_15 15:0 

7.3 GPIO 

GPIO 3 : Port0, Port2 

Port1 

GPIO 

• Port 0: GPIO0 

0 ~ 31 


0 ~ 6 7 ~ 31 


0 ~ 15 16 ~ 31 

Table 7-2: 

: GPIO ( port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000) 

 

MASK R/W 0x000 

PIN, 0x0000 OUT, SET, CLR, 0000 NOT 

PIN R 0x004 

. 

OUT R/W 0x008 . 0x0000 0000 

SET W 0x00C 

. NA 

CLR W 0x010 

. NA 

NOT W 0x014 

. 0x0000 0000 

DIR R/W 0x020 

. 0x0000 0000 


XN62Lxxx 

IS R/W 0x024 

. 0x0000 0000 

IBE R/W 0x028 

. 0x0000 0000 

IEV R/W 0x02C 

. 0x0000 0000 

IE R/W 0x030 

. 0x0000 0000 

RIS R 0x034 

. 0x0000 0000 

MIS R 0x038 

. 0x0000 0000 

IC W 0x03C 

. 0x0000 0000 

7.3.1 GPIO 

/ 

PINOUTSETCLR NOT 

MASK 

0 

 

0 OUTSETCLR NOT 

 

PIN 

OUT 

1 OUTSETCLR NOT 

0 

OUT 


(MASK - 0x5000 0000 (GPIO0), 0x5001 0000 (GPIO1), 0x5002 0000 (GPIO2)) 

 

x (31~0) MASKx GPIO PIOn_x 

0x0 

0 

1 

7.3.2 GPIO 

 

 

GPIO 

GPIO GPIO / 

 

PIN 

ADC PIN 

MASK 

 

0 


(PIN - 0x5000 0004 (GPIO0), 0x5001 0004 (GPIO1);0x5002 0004 (GPIO2)) 

 

x (31~0) PINx GPIO PIOn_x . 0 

0 

1 


XN62Lxxx 

7.3.3 GPIO 

 

0 1 

GPIO 

GPIO OUT 

MASK GPIO 

MASK SET 

CLR NOT OUT 

OUT Table 7-5: GPIO 

(OUT - 0x5000 0008 (GPIO0), 0x5001 0008 (GPIO1), 0x5002 0008 (GPIO2)) 

 

x (31~0) OUTx GPIO PIOn_x . 0 

0 : GPIO . 

: GPIO 

1 : GPIO. 

: 

7.3.4 GPIO 

 

DIR 

GPIO 

IOCONFIG 

GPIO 

1 

0 GPIO 

GPIO SET 

 

SET MASK 


(SET - 0x5000 000C (GPIO0), 0x5001 000C (GPIO1), 0x5002 000C (GPIO2)) 

 

x (31~0) SETx GPIO PIOn_x 

: 

0 

0 = 

1 = GPIO 

7.3.5 GPIO 

 

DIR 

GPIO 

IOCONFIG 

GPIO 

1 

0 GPIO 

GPIO CLR 

 

CLR MASK 


(CLR - 0x5000 0010 (GPIO0), 0x5000 1010 (GPIO1), 0x5002 0010 (GPIO2)) 

 

x (31~0) CLEARx GPIO PIOn_x 

: 

0 

0 = 

1 = GPIO 


XN62Lxxx 

7.3.6 GPIO 

 

DIR 

GPIO 

IOCONFIG 

GPIO 

1 

0 GPIO 

GPIO NOT 

 

NOT 

MASK 

Table 7-8: GPIO (NOT - 0x5000 0014 (GPIO0), 0x5001 0014 (GPIO1), 0x5002 0014 (GPIO2)) 

 

x (31~0) NOT GPIO PIOn_x 

: 

0 

0 = 

1 = GPIO 

7.3.7 GPIO 


(DIR - 0x5000 0020 (GPIO0), 0x5001 0020 (GPIO1), 0x5002 0020 (GPIO2)) 

 

x (31~0) IOx GPIO PIOn_x 0 

0 GPIO PIOn_x 

1 GPIO PIOn_x 

7.3.8 GPIO 


(IS - 0x5000 0024 (GPIO0), 0x5001 0024 (GPIO1), 0x5002 0024 (GPIO2)) 

 

x (31~0) ISENSEx PIOn_x 0 

0 PIOn_x 

1 PIOn_x 

7.3.9 GPIO 


(IBE - 0x5000 0028 (GPIO0), 0x5001 0028 (GPIO1), 0x5002 0028 (GPIO2)) 

 

x (31~0) IBEx PIOn_x / 0 

0 PIOn_x 

IEV 1 PIOn_x 

7.3.10 GPIO 


(IEV - 0x5000 002C (GPIO0), 0x5001 002C (GPIO1), 0x5002 002C (GPIO2)) 

 

x (31~0) IEVx PIOn_x 0 

0 . 


XN62Lxxx 

1 . 

7.3.11 GPIO 

lE 


(IE - 0x5000 0030, 0x5001 0030 (GPIO1),0x5002 0030 (GPIO2)) 

 

x (31~0) MASKx 

PIOn_x 0 

0 PIOn_x 

1 PIOn_x 

7.3.12 GPIO 

lRS 

IE 0 


(RIS - 0x5000 0034 (GPIO0), 0x5001 0034 (GPIO1), 0x5002 0034 (GPIO2)) 

 

x (31~0) RAWSTx 0 

0 

PIOn_x 

1 PIOn_x 

7.3.13 GPIO 

MIS 

MIS 

 


(MIS - 0x5000 0038 (GPIO0), 0x5001 0038 (GPIO1), 0x5002 0038 (GPIO2)) 

 

x (31~0) INTSx PIOn_x 0 

0 PIOn_x 

1 PIOn_x 

7.3.14 GPIO 


(IC - 0x5000 003C, 0x5001 003C (GPIO1), 0x5002 003C (GPIO2)) 

 

x (31~0) CLRx PIOn_x 0 

0 0 

1 1 


XN62Lxxx 

8 16 / 

8.1 

XN62L 

16 / / 

SYSAHBCLKDIV 

SYSAHBCLKDIV / 

 

• 

16 / 

• / 

: 

– 

– 

– 

– 

– 

• 16 

• 4 16 : 

– 

– 

– 

• : 

– 

– . 

– . 


XN62Lxxx 

CAPTURE REGISTER 3 


CAPTURE GEGISTER 1 


MATCH REGISTER 3 




CAPTURE CONTROL REGISTER 

MATCH CONTROL REGISTER 

ENTERNAL MATCH REGISTER 

INTERRUPT REGISTER 

CONTROL 

= 

= 

LOAD[3:0] 

= 

= 

MAT[1:0] 

INTERRUPT 

CAP[3:0] 

TIMER CONTROL 

REGISTER 

Reset/Enable 

TIMER COUNTER 

+ - 

COUNT/ 

Edge CNT 

QUAD 

CNT 

GATE 

CNT 

TRIGGER 

CNT 

SIGNED 

CNT 

PRI 

SEC 

SOURCE SEL 

MAXVAL 

PRESCALE REGISTER 

PRESCALE 

COUNTER 

CAP[3:0] 

Other C16B MAT 

C32B MAT 

PCLK 

Figure 8-1: 16 / 


XN62Lxxx 

8.2 

16 / 

Table 8-1: 16- / 

 

CT16B0_CAP[1:0] 

CT16B1_CAP[1:0] 

CT16B0_MAT[1:0] 

CT16B1_MAT[1:0] 

 

 

: 

 

CT16B0/1 

: 

CT16B0/1 

(MR1:0) TC 

 

EMR PWMCON 

2,3 

8.3 

Table 8-2: 16 / 

(CT16B0 0x4001 0000; CT16B1 0x4001 4000) 

 

IR R/W 0x000 / 

. 0 

TCR R/W 0x004 

TCR 

0 

 

TC R/W 0x008 

PCLK 1. TCR 0 

 

PR R/W 0x00C 

PC 

TC PC 0 

PC R/W 0x010 

16 

PC PR 0 

TC 1PC 

MCR R/W 0x014 

MCR 

TC 0 

MR0 R/W 0x018 0 TC 

MR0 TC 

0 

TC 

MR1 R/W 0x01C 1 

MR0 0 

MR2 R/W 0x020 2 

MR0 

0 

MR3 R/W 0x024 3 

MR0 

0 

CCR R/W 0x028 CC 

TC 0 

 

CR0 RO 0x02C 

0CR0 CT16Bn_CAP0 

TC 0 

CR1 RO 0x030 


TC 0 

CR2 RO 0x034 


TC 0 

CR3 RO 0x038 


TC 0 

EMR R/W 0x03C 

EMR 

0 

CT16B0_MAT[1:0] CT16B1_MAT[1:0]. 


XN62Lxxx 

- - 0x040 - 0x06C - 

CTCR R/W 0x070 

CTCR 

0 

8.3.1 

 

4 

2 

IR 

IR 1 

0 

DMA Table 8-3: (IR, 0x4001 0000 (CT16B0) 0x4001 4000 (CT16B1)) 

 

0 MR0INT 0 0 

1 MR1INT 1 0 

2 MR2INT 2 0 

3 MR3INT 3 0 

4 CR0INT 0 0 

5 CR1INT 1 0 

6 CR2INT 2 0 

7 CR3INT 3 0 

31:8 - - 

8.3.2 

/ 

Table 8-4: 

(TCR, 0x4001 0004 (CT16B0) 0x4001 4004 (CT16B1)) 

 

0 CEN 0 

0 

1 

1 CRST 0 

0 . 

1 

PCLK 

TCR 

31: 2 - - . NA 

8.3.3 

 

PC 16 

TC 

0x0000 FFFF 0x0000 0000 

Table 8-5: 

(TC, 0x4001 0008 (CT16B0) 0x4001 4008 (CT16B1)) 

 

15:0 TC . 0 


XN62Lxxx 

31:16 - . - NA 

8.3.4 

16 

Table 8-6: (PR, 

0x4001 000C (CT16B0) 0x4001 400C (CT16B1)) 

 

15:0 PCVAL . 0 

31:16 - . - 

8.3.5 

16 

PCLK 

 

PCLK 

PCLK TC PR = 0 

PCLK 

PR = 1 2 PCLK . 

Table 8-7: 

(PC, 0x4001 0010 (CT16B0) 0x4001 4010 (CT16B1)) 

 

15:0 PC 

. 0 

31:16 - . - 

8.3.6 

 

Table 8-8: 

(MCR, 0x4001 0014 (CT16B0) 0x4001 4014 (CT16B1)) 

 

0 MR0I MR0 TC 0 

1 

0 

1 MR0R MR0 TC TC 0 

1 

0 

2 MR0S MR0 TC TC PC TCR CEN 0 0 

1 

0 


1 

0 


1 


XN62Lxxx 

0 


1 

0 


1 

0 


1 

0 


1 

0 


1 

0 


1 

0 


1 

0 

31:12 . NA 

8.3.7 

 

 

MCR Table 8-9: s (MR0 ~ 3, 0x4001 0018 ~24 (CT16B0) 0x4001 4018~24 (CT16B1)) 

 

15:0 MATCH . 0 

31:16 - . NA 

8.3.8 

/ 

 

 

“n” 0 1 2 3 “n” 

0 

1 0 CT16B0 1 CT16B1 

Table 8-2: 

(CCR, 0x4001 0028 (CT16B0) 0x4001 4028 (CT16B1)) 


XN62Lxxx 

 

0 CAP0RE CT16Bn_CAP0 

CT16Bn_CAP0 0 1 0 

1 

0 

CR0 TC 

1 CAP0FE CT16Bn_CAP0 

CT16Bn_CAP0 1 0 0 

1 

0 

CR0 TC 

2 CAP0I CT16Bn_CAP0 

CT16Bn_CAP0 

CR0 0 

1 

0 

 


CT16Bn_CAP1 0 1 0 

1 

0 

CR1 TC 


CT16Bn_CAP1 1 0 0 

1 

0 

CR1 TC 

5 CAP1I CT16Bn_CAP1 

CT16Bn_CAP0 

CR1 0 

1 

0 

 

6 CAP2RE 0 

0 0 1 

CR2 0 

1 

0 

TC 

7 CAP2FE 0 

0 1 0 

CR2 0 

1 

0 

TC 

8 CAP2I 0 

0 

CR2 0 

1 

0 

 

9 CAP3RE 1 

1 0 1 

CR3 0 

1 

TC 


XN62Lxxx 

0 

10 CAP3FE 1 

1 1 0 

CR3 0 

1 

0 

TC 

11 CAP3I 1 

1 

CR3 0 

1 

0 

 

31:12 - NA 

8.3.9 

 

 

Table 8-3: (CR0 

~ 3, 0x4001 002C ~ 38 (CT16B0) 0x4001 402C ~ 38 (CT16B1)) 

 

15:0 CAP 0 

31:16 - . NA 

8.3.10 

 

CT16Bn_MAT[1:0] 

0 1 DMA 

Table 8-4: 

(EMR, 0x4001 003C (CT16B0) 0x4001 403C (CT16B1)) 

 

0 EM0 0 

CT16B0_MAT0/CT16B1_MAT0 

0 

 

TC MR0 

 

EMR[5:4] 

IOCON 

0= 

1= 


1 EM1 1 


0 

 

TC MR1 

 

EMR[7:6] 

IOCON 

0= 

1= 


2 EM2 2 

2 TC MR2 

0 

 

EMR[9:8] 


XN62Lxxx 

3 EM3 3 

3 

TC MR3 

0 

 

EMR[11:10] 

5:4 EMC0 

0 

0 00 

00 

01 / 

 

CT16Bn_MAT0 

 

10 / 

1 

CT16Bn_MAT0 

 

11 

/ 7:6 EMC1 

1 

1 00 

00 

01 / 

 

CT16Bn_MAT1 

 

10 / 

1 

CT16Bn_MAT1 

 

11 

/ 9:8 EMC2 

2 

3 00 

00 

01 / 

 

CT16Bn_MAT2 

 

10 / 

1 

CT16Bn_MAT2 

 

11 

/ 11: 10 EMC3 

3 

3 00 

00 

01 / 

 

CT16Bn_MAT3 

 

10 / 

1 

CT16Bn_MAT3 

 

11 

/ 31: 12 - - . NA 

8.3.11 

(CTCR) 

 

 

PCLK CTCR 

3:2 CAP 

CAP 

CAP 

CTCR 1:0 


XN62Lxxx 

 

PCLK CAP 

CAP 

PCLK 

CAP / 

 

1/PCLK 

 

7:4 - 

- 

CAP 

 

 

Table 8-5: 

(CTCR, 0x4001 0070 (CT16B0) 0x4001 4070 (CT16B1)) 

 

2:0 CTM / 

PCLK 00 

(PC) 

PC (TC) 

 

CTCR (CCR) 

2:0 000 

000 

PCLK 001 TC 

11:8 CAP 

010 TC 

11:8 CAP 

011 TC 

11:8 CAP 

100 

101 

110 

111 

3 - - 

4 ENCC 1 7:5 - 

0 

7:5 SELCC 4 1 

000 

4 

000 CAP0 

4 001 CAP0 

4 010 CAP1 

4 011 CAP1 

4 100 CAP2 

4 101 CAP2 

4 110 CAP3 

4 111 CAP3 

4 11:8 PRISEL 0000 

0000 CAP0. 

0001 CAP0. 

0010 0 . 

0011 1 . 

0100 CT16B0 PWM0 

CT16B1 PWM1 


XN62Lxxx 

0101 CT16B0 CT16B1_MAT1 

CT16B1 CT16B1_MAT0 

0110 CT32B0_MAT0. 

0111 CT32B1_MAT0 

1xxx 

 

15:12 SECSEL 0000 

0000 CAP0. 

0001 CAP1. 

0010 0 . 

0011 1 . 

0100 CT1B0 PWM0 

CT1B1 PWM1 

0101 CT1B0 CT16B1_MAT1 

CT1B1 CT16B1_MAT0 

0110 CT32B0_MAT0. 

0111 CT32B1_MAT0 

1xxx 

 

16 IPS 0 

0 

1 

31: 17 - - . NA 

8.3.11.1 

 

 

8.3.11.2 

 

 

90° 

 

PHASE A 

(Primary) 

PHASE B 

(Secondary) 

COUNT 

+1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 

Figure 8-2: 


XN62Lxxx 

8.3.11.3 

 

 

Primary 

Secondary 

COUNT 0 1 2 3 4 

5 

6 7 8 

Figure 8-3: 

8.3.11.4 

 

Primary 

Secondary 

COUNT 0 1 2 3 4 3 2 1 0 1 2 3 4 5 

Figure 8-4: 

8.3.11.5 

 

IPS 

Primary 

Secondary 

COUNT 0 1 2 3 4 

5 

6 7 8 9 

Figure 8-5: 

8.3.12 DMA 

0 / 

DMA 

DMA 

DMA 

DMA 

“1” 

DMA DMA 

DMA 


XN62Lxxx 

9 32 / 

9.1 

16 / XN62L 

32 / / 

SYSAHBCLKDIV 

 

SYSAHBCLKDIV / 

 

• 

32 / 

• / 

: 

– 

– 

– 

– 

– 

• 32 

• 4 32 : 

– 

– 

– 

• : 

– 

– . 

– . 

• 

DMA . 


XN62Lxxx 



CAPTURE GEGISTER 1 






CAPTURE CONTROL REGISTER 

MATCH CONTROL REGISTER 

ENTERNAL MATCH REGISTER 

INTERRUPT REGISTER 

CONTROL 

= 

= 

LOAD[3:0] 

= 

= 

MAT[3:0] 

INTERRUPT 

CAP[3:0] 

TIMER CONTROL 

REGISTER 

Reset/Enable 

TIMER COUNTER 

+ - 

COUNT/ 

Edge CNT 

QUAD 

CNT 

GATE 

CNT 

TRIGGER 

CNT 

SIGNED 

CNT 

PRI 

SEC 

SOURCE SEL 

MAXVAL 

PRESCALE REGISTER 

PRESCALE 

COUNTER 

CAP[3:0] 

C16B MAT 

Other C32B MAT 

PCLK 

Figure 9-1: 32 / 

 

9.2 

Table 9-1: / 

 

CT32B0_CAP[3:0] 

CT32B1_CAP[3:0] 

CT32B0_MAT[3:0] 

CT32B1_MAT[3:0] 

 

 

: 

 

 

CT32B0/1 

: 

CT32B0/1 

(MR1:0) TC 

 

EMR PWMCON 


XN62Lxxx 

9.3 

32 / 

Table 9-2: 32 / 

(CT32B0 0x4001 8000; CT32B1 0x4001 C000) 

 

IR R/W 0x000 

/ 

. 

0 

TCR R/W 0x004 

TCR 

0 

 

TC R/W 0x008 

PCLK 1. TCR 0 

 

PR R/W 0x00C 32 

 

PC PR 0 

TC 1PC 

PC R/W 0x010 16 

 

PC PR 0 

TC 1PC 

MCR R/W 0x014 

. MCR 

TC 0 

MR0 R/W 0x018 0. TC 

MR0 TC 

TC 

 

MR1 R/W 0x01C 1. MR0 . 0 

MR2 R/W 0x020 2. MR0 . 0 

MR3 R/W 0x024 3. MR0 . 0 

CCR R/W 0x028 

CCR TC 0 

 

CR0 RO 0x02C 

0. CR0 CT32Bn_CAP0 

TC 0 

CR1 RO 0x030 


TC 0 

CR2 RO 0x034 


TC 0 

CR3 RO 0x038 


TC 0 

EMR R/W 0x03C 

. EMR 

0 

CT32Bn_MAT[3:0]. 

- - 0x040 - 0x06C - 

CTCR R/W 0x070 . 

CTCR 

0 

0 

9.3.1 

 

4 

2 

IR 

IR 1 

0 

DMA Table 9-3: (IR, 0x4001 8000 (CT32B0) 0x4001 C000(CT32B1)) 

 

0 MR0INT 0 0 

1 MR1INT 1 0 


XN62Lxxx 

2 MR2INT 2 0 

3 MR3INT 3 0 

4 CR0INT 0 0 

5 CR1INT 1 0 

6 CR2INT 2 0 

7 CR3INT 3 0 

31:8 - - 0 

9.3.2 

/ 

. 

Table 9-4: 

(TCR, 0x4001 8004 (CT32B0) 0x4001 C004 (CT32B1)) 

 

0 CEN 0 

0 

1 

1 CRST 0 

0 . 

1 

PCLK 

TCR 

31: 14 - - . N/A 

9.3.3 

 

32 

TC 

0xFFFF FFFF 0x0000 0000 

Table 9-5: 

(TC, 0x4001 8008 (CT32B0) 0x4001 5C008 (CT32B1)) 

 

31:0 TC 0 

9.3.4 

32 

Table 9-6: (PR, 

0x4001 800C (CT32B0) 0x4001 5C00C (CT32B1)) 

 

31:0 PCVAL . 0 


XN62Lxxx 

9.3.5 

32 

PCLK 

 

PCLK 

PCLK TC PR = 0 

PCLK 

PR = 1 2 PCLK . 

Table 9-7: 

(PC, 0x4001 8010 (CT32B0) 0x4001 5C010 (CT32B1)) 

 

31:0 PC 0 

9.3.6 

 

Table 9-8: 

(MCR, 

0x4001 8014 (CT32B0) 0x4001 C014 (CT32B1)) 

 


1 

0 

1 MR0R MR0 TC TC 

0 

1 

0 


1 

0 


1 

0 


0 

1 

0 


1 

0 


1 

0 


0 

1 


XN62Lxxx 

0 


1 

0 


1 

0 


0 

1 

0 


1 

0 

31:12 NA 

9.3.7 

 

 

MCR Table 9-9: (MR0 ~ 3, 0x4001 8018 ~24 (CT32B0) ; 0x4001 C018 ~ 24 (CT32B1)) 

 

31:0 MATCH 0 

9.3.8 

/ 

 

“n” 0 1 

Table 9-10: 

(CCR, 0x4001 8028 (CT32B0) 0x4001 C028 (CT32B1)) 

 

0 CAP0RE 1 CT32Bn_CAP0 

CT32Bn_CAP0 0 1 0 

1 

0 

CR0 TC 

1 CAP0FE 1 CT32Bn_CAP0 

CT32Bn_CAP0 1 0 0 

1 

0 

CR0 TC 

2 CAP0I CT32Bn_CAP0 CT32Bn_CAP0 

 

CR0 0 

 


XN62Lxxx 

1 

0 


CT32Bn_CAP1 0 1 0 

1 

0 

CR0 TC 


CT32Bn_CAP1 1 0 0 

1 

0 

CR0 TC 


 

CR0 0 

1 

0 

 


CT32Bn_CAP2 0 1 0 

1 

0 

CR0 TC 


CT32Bn_CAP2 1 0 0 

1 

0 

CR0 TC 


 

CR0 0 

1 

0 

 


CT32Bn_CAP3 0 1 0 

1 

0 

CR0 TC 


CT32Bn_CAP3 1 0 0 

1 

0 

CR0 TC 


 

CR0 0 

1 

0 

 

31:12 - - NA 


XN62Lxxx 

9.3.9 

 

 

Table 9-11: (CR0 

~ 3, 0x4001 802C ~38 (CT32B0) 0x4001 C02C~ 38 (CT32B1)) 

 

31:0 CAP 0 

9.3.10 

 

CT32Bn_MAT[3:0] 

0 1 DMA 

Table 9-12: 

(EMR, 0x4001 803C (CT32B0) 0x4001 C03C (CT32B1)) 

 

0 EM0 0 


0 

 

TC MR0 

 

EMR[5:4] IOCON 0= 

1= 


1 EM1 1 


0 

 

TC MR1 

 


1= 


2 EM2 2 


0 

 

TC MR2 

 


1= 


3 EM3 3 


0 

 

TC MR3 

 


1= 


5:4 EMC0 

0 

0 00 

00 

11 / 

 

CT32Bn_MAT0 

 

10 / 

1 

CT32Bn_MAT0 

 

11 

/ www.xinnovatech.com 183

XN62Lxxx 

7:6 EMC1 

1 

1 00 

00 

11 / 

 

CT32Bn_MAT1 

 

10 / 

1 

CT32Bn_MAT1 

 

11 

/ 9:8 EMC2 

2 

2 00 

00 

11 / 

 

CT32Bn_MAT2 

 

10 / 

1 

CT32Bn_MAT2 

 

11 

/ 11:10 EMC3 

3 

3 00 

00 

11 / 

 

CT32Bn_MAT3 

 

10 / 

1 

CT32Bn_MAT3 

 

11 

/ 31:12 - NA 

9.3.11 

(CTCR) 

 

 

PCLK CTCR 

3:2 CAP 

CAP 

CAP 

CTCR 1:0 

 

PCLK CAP 

CAP 

PCLK 

CAP / 

 

1/PCLK 

 

7:4 - 

- 

CAP 

 

 

Table 9-13: (CTCR, 0x4001 8070 (CT32B0) 0x4001 C070 (CT32B1)) 

 


XN62Lxxx 

2:0 CTM / 

PCLK 00 

(PC) 

PC (TC) 

 

CTCR 

(CCR) 

2:0 000 

000 

PCLK 001 TC 

11:8 CAP 

010 TC 

11:8 CAP 

011 TC 

11:8 CAP 

100 

101 

110 

111 

3 - - NA 

4 ENCC 1 7:5 - 

0 

7:5 SELCC 4 1 

000 

4 

000 CAP0 

4 001 CAP0 

4 010 CAP1 

4 011 CAP1 

4 100 CAP2 

4 101 CAP2 

4 110 CAP3 

4 111 CAP3 

4 11:8 PRISEL 0000 

0000 CAP0. 

0001 CAP1. 

0010 CAP2 

0011 CAP3. 

0100 CT32B0 PWM0 

CT32B1 PWM1 

0101 CT16b1_MAT0. 

0110 CT32b0_MAT0. 

0111 CT32b1_MAT0./ CT32b0_MAT0 

1xxx 

 

15:12 SECSEL 0000 

0000 CAP0. 

0001 CAP1. 

0010 CAP2 

0011 CAP3. 


XN62Lxxx 

0100 CT32B0 PWM0 

CT32B1 PWM1 

0101 CT16b1_MAT0. 

0110 CT32b0_MAT0. 

0111 CT32b1_MAT0./ CT32b0_MAT0 

1xxx 

 

16 IPS 0 

0 

1 

31: 17 - - . NA 

9.3.12 DMA 

0 / 

 

DMA 

DMA 

DMA 

DMA 

“1” 

DMA DMA 

DMA 


XN62Lxxx 

10 

(WDT) 

10.1 

 

 

• 

• 

• 

 

feed ok 

TC 

WDT_CLK 

24-bit down counter 

enable count 

FEED 

WD TV 

WINDOW 

feed sequence 

Detect and 

protection 

in 

range 

compare 

0 

WDINTVAL 

feed ok 

TC write 

feed error 

compare 

underflow 

compare 

shadow bit 

feed ok 

MOD 

register 

WDPRO TECT 

(MOD [4]) 

WDTOF 

(MOD [2]) 

WDINT 

(MOD [3]) 

WDRESET 

(MOD [1]) 

WDEN 

(MOD [0]) 

chip reset 

watchdog 

interrupt 

Figure 10-1: 


XN62Lxxx 

10.2 

Table 10-1: ( 

0x4000 4000) 

 

MOD R/W 0x000 

 

0x0000 0003 

 

TC R/W 0x004 

 

0x0000 FFFF 

FEED WO 0x008 

0xAA 

NA 

0x55 TC 

TV RO 0x00C 

0xFF 

 

CLKSEL R/W 0x010 0 

WARNINT R/W 0x014 

0 

WINDOW R/W 0x018 0xFF FFFF 

10.3 

MOD WDEN RESET 

 

Table 10-2: 

(MOD - 0x4000 4000) 

 

0 WDEN 

WDLOCKEN 

WDEN 0 

0 

1 

1 WDRESET 

WDLOCKEN 

WDRESET 1 

0 

1 

2 WDTOF 

WDPROTECT=1 0 ( 

WDTC 

0 ) 

 

WDTOF 1 

 

3 WDINT 

WDWARNINT 

0 

 

1 4 WDPROTECT 

WDPROTECT 

0 

WDPROTECT 

0 (WDTC) 


XN62Lxxx 

1 

WARNINT WINDOW 

(WDTC) 

5 WDLOCKCLK 

0 

 

0 (WDCLK) 

1 

PDRUNCFGPDSLEEPCFG PDAWAKECFG 

 

WDLOCKCLK 

/ IRC WDT 

WDLOCKCLK 

 

IRC 

 

WDLOCKCLK 

WDT 

PDSLEEPCFG 

WDLOCKCLK 

6 WDLOCKDP 

0 

 

0 

1 PMU 

DPDEN 1 

7 WDLOCKEN 

0 

31: 8 

 

0 WDEN WDRESET 

1 

1 WDEN WDRESET 

WDLOCK 

WDEN 

 

• WDLOCKEN 

WDRESET 1 

 

• WDLOCKEN 

WDRESET 0 

 

Table 10-3: 

WDEN WDRESET 

0 X (0 or 1) 

1 0 

 

WDWARNINT WDINT 

 

1 1 

 

 

WDWARNINT WDINT 

 


XN62Lxxx 

10.3.1 

TC 

TC 

0x00 FFFF 0xFF 0xFF TC 

TWDCLK × 256 × 4 MOD WDPROTECT 1 

 

WARNINT WINDOW 

TC 

WDTOF Table 10-4: 

(TC - 0x4000 4004) 

23:0 WDTC 0x00 FFFF 

31:24 - 

10.3.2 

 

0xAA 0x55 WDTC 

WDTOF Table 10-5: 

(FEED - 0x4000 4008) 

 

7:0 WDFEED 

0xAA 0x55 - 

31:8 

10.3.3 

WDTV 

Table 10-6: 

(TV - 0x4000 400C) 

 

23:0 WDTV 0x00 00FF 

31:24 - NA 

10.3.4 

 

31 IRC PDRUNCFG 

WDT 

Table 10-7: (CLKSEL 

- 0x4000 4010) 

 

1:0 WDSEL 

00 

 

WDLOCK WDSEL 

 

PDRUNCFG 

WDSEL 0x0 

IRC 


XN62Lxxx 

0x1 

 

WDT 

 

0x2 

0x3 

. 

. 

30:2 - - . NA 

31 WDLOCK 0 

0 

0 

1 

WDLOCK 

10.3.5 

WDWARNINT 

WDWARNINT WDCLK 

10 WARNINT 10 

0 

1,023 4,096 

WARNINT 0 

 

Table 10-8: 

(WARNINT - 0x4000 4014) 

 

9:0 WARNINT 0 

31:10 - NA 

10.3.6 

WDWINDOW 

WDTV 

WDTV WDWINDOW 

 

WDWINDOW WDTV 

WDWINDOW 0x100 

Table 10-9: 

(WINDOW - 0x4000 4018) 

 

23:0 WDWINDOW 

. 

0xFF FFFF 

31:24 - NA 

10.4 

 

PCLK WDCLKPCLK 

APB 

WDCLK 

wdt_clk 

wdt_clk IRC 

 

WDCLKSEL 

MODE www.xinnovatech.com 191

XN62Lxxx 

 

MOD TC APB 

WDCLK 

 

WDCLK 

WDCLK 

PCLK TV 

CPU 

 

PDRUNCFG 

MOD 5 

AHBCLKCTRL (PCLK) 

10.5 

 

WDT 

 

• WDT / 

• 

• PDRUNCFGPDSLEEPCFGPDAWAKECFG 

WDT 

• WDT 

• 

 

• 

PDSLEEPCFGPDRUNCFG PDAWAKECFG WDT 

• 

WDT 

10.6 

: 

WDCLK / 4 

Watchdog 

Counter 

125A 1259 1258 1257 

Early Feed 

Event 

Watchdog 

Reset 

Conditions: 

WINDOW = 0x1200 

WARNINT = 0x3FF 

TC = 0x2000 

Figure: 10-2 


XN62Lxxx 

WDCLK / 4 

Watchdog 

Counter 

125A 1259 1258 1257 

Early Feed 

Event 

Watchdog 

Reset 

Conditions: 



TC = 0x2000 

Figure 10-3: 

WDCLK / 4 

Watchdog 

Counter 

0403 0402 0401 0400 03FF 03FE 03FD 03FC 03FB 03FA 03F9 

Watchdog 

Interrupt 

Conditions: 



TC = 0x2000 

Figure 10-4: 


XN62Lxxx 

11 xDSP 

11.1 

XN62L 

DSP xDSP 

, 

xDSP ARM 

 

xDSP 

xDSP xDSP_PCLK 

 


xDSP 

xDSP 

• CRC 

• 32 

• Sine 

• Cosine 

• Arctangent 

• FIR 

IIR 

11.2 xDSP 

Table 11-1: 

( 0x5007 0000) 

 

CRC_MODE R/W 0x00 CRC 0x0000 0000 

CRC_SEED R/W 0x04 CRC 0x0000 FFFF 

CRC_SUM R/W 0x08 : CRC 

0x0000 FFFF 

: CRC 

~ ~ ~ 

DIVIDEND R/W 0x100 32 0x0000 0000 

DIVISOR R/W 0x104 32 0x0000 0000 

QUOTIENT RO 0x108 32 0x0000 0000 

~ ~ ~ 

CORDIC_CTRL R/W 0x200 CORDIC 0x0000 0000 

CORDIC_X R/W 0x204 32 CORDIC X 0x0000 0000 

CORDIC_Y R/W 0x208 32 CORDIC Y 0x0000 0000 

CORDIC_PH R/W 0x20C 32 CORDIC 0x0000 0000 

CORDIC_RLTX RO 0x210 32- CORDIC X 0x0000 0000 

CORDIC_RLTY RO 0x214 32- CORDIC Y 0x0000 0000 

CORDIC_RLTPH RO 0x218 32- CORDIC 

0x0000 0000 

~ ~ ~ 


XN62Lxxx 

FILTER_CR R/W 0x280 0x0000 0000 

FILTER_D R/W 0x284 0x0000 0000 

FILTER_START R/W 0x288 

0x0000 0000 

FILTER_RESULT R/W 0x28C 0x0000 0000 

FILTER_C01 

R/W 

0x290 

0~15 0x0000 0000 

~ 

~ 

FILTER_CEF 

0x2AC 

11.2.1 CRC 

Table 11-2: CRC (CRC_MODE, 0x5007 0000) 

 

1:0 CRC_POLY CRC 00 

00 CRC-CCITT 

01 CRC-16 

1X 

CRC-32 

2 BIT_RVS_WR 0 

0 CRC_WR_DATA 

1 CRC_WR_DATA 

3 CMPL_WR 0 

0 CRC_WR_DATA 1 

1 1 

CRC_WR_DATA 

4 BIT_RVS_SUM CRC 0 

0 CRC_SUM 

1 CRC_SUM 

5 CMPL_SUM CRC 0 

0 CRC_SUM 1 

1 1 

CRC_SUM 

6 SEED_OP CRC 0 

0 

1 

CRC 

7 SEED_SET - 1 

CRC 0 

31:8 - - NA 

11.2.2 CRC Seed 

Table 11-3: CRC (CRC_SEED, 0x5007 0004) 

 

31:0 CRC_SEED CRC 0x0000 FFFF 

11.2.3 CRC 

 


XN62Lxxx 

Table 11-4: CRC (CRC_SUM, 0x5007 0008) 

 

31:0 CRC_SUM 1 

CRC 

0x0000 FFFF 

 

11.2.4 CRC 

 

CRC Table 11-5: CRC Data (CRC_DATA, 0x5007 0008) 

 

31:0 CRC_WR_DATA 1 

CRC 

- 

816 32 

11.2.5 

Table 11-6: (DIVIDEND, 0x5007 0100) 

 

31:0 DIVIDEND 32 . - 

11.2.6 

Table 11-7: (DIVISOR, 0x5007 0104) 

 

31:0 DIVISOR 32 . - 

11.2.7 

Table 11-8: 

(QUOTIENT, 0x5007 0108) 

 

31:0 QUOTIENT - 

11.2.8 CORDIC 

Table 11-9: CORDIC 

(CODIC_CTRL, 0x5007 0200) 

 

4:0 RES CORDIC 00 

0~14 

15~31 16~32 CORDIC 

5 - . 0 

7:6 MODE CORDIC 00 

00 

01 arctan CORDIC 

10 sin/cos CORDIC 

31:8 - - . 0 


XN62Lxxx 

11.2.9 CORDIC X 

Table 11-10: CORDIC X (CODIC_X, 0x5007 0204) 

 

31:0 CORDIC_X 32 CORDIC X . - 2 RES-1 ~ 2 RES-1 . 

31~RES 0 

 

11.2.10 CORDIC Y 

Table 11-11: CORDIC Y (CODIC_Y, 0x5007 0208) 

 

31:0 CORDIC_Y 32 CORDIC Y . 

-2 RES-1 ~ 2 RES-1 . 

31~RES 0 

 

11.2.11 CORDIC Phase 

Table 11-12: CORDIC Phase (CODIC_PH, 0x5007 020C) 

 

31:0 CORDIC_PH 32 CORDIC Phase . 

-2 RES-1 ~ 2 RES-1 . 

31~RES0 

 

11.2.12 CORDIC X 

Table 11-13: CORDIC X (CODIC_RLTX, 0x5007 0210) 

 

31:0 CORDIC_RLTX 

0 

32 CORDIC X . -2 RES-1 ~ 2 RES-1 . 

31~RES 

11.2.13 CORDIC Y 

Table 11-14: CORDIC Y (CORDIC_RLTY, 0x5007 0214) 

 

31:0 CORDIC_RLTY 

0 

32 CORDIC Y . -2 RES-1 ~ 2 RES-1 . 

31~RES 

11.2.14 CORDIC Phase 

Table 11-15: CORDIC Phase (CORDIC_RLTPH, 0x5007 0218) 

 

31:0 CORDIC_RLTPH 

0 

32 CORDIC 

. 

-2 RES-1 ~ 2 RES-1 . 

31~RES 

11.2.15 

Table 11-10: 

(FILTER_CR, 0x5007 0280) 

 


XN62Lxxx 

15:0 SHF_DSRCSEL 0000 

0 D[n] 

D[n-1] 

1 D[n] 

19:16 FILTER_CYC . 

0 

0 1 

~ 

0xf 16 . 

FIR - 

1 IIR , 

 

21:20 FILTER_MODE 00 

00 

01 DMA 

DMA 

DMA 

10 DMA 

DMA 

DMA 

 

xDSP 

XDSP0_DMA_info 

. 

11 

23:22 - - . 0 

24 FILTER_CLR 0 

0 . 

1 

26:25 - - . 0 

31:27 OUTPUT_SHIFT . 

 

0 

FILTER_RESULT 

IIR 

11.2.16 

Table 11-11: 

(FILTER_D, 0x5007 0284) 

 

15:0 FILTER_D 

. 0 

31:16 - 0 

11.2.17 

Table 11-11: 

(FILTER_START, 0x5007 0288) 

 

0 FILTER_START 

1 0 0 

31:1 - 0 

11.2.18 

Table 11-11: 

(FILTER_RESULT, 0x5007 028c) 

 


XN62Lxxx 

15:0 FILTER_RESULT . 0 

16 FILTER_STAT 

1 

0 

1 

31:16 - 0 

11.2.19 

Table 11-11: 0~7 (FILTER_C n, n=0~7, 0x5007 0290 ~ 0x5007 02ac) 

 

15:0 FILTER_C 2n 2n 0 

31:16 FILTER_C 2n+1 2n+1 0 

11.3 

11.3.1 CRC 

CRC 

 

CRC-CCITT 

= x 16 + x 12 + x 5 + 1 

= 0xFFFF 

 

1 

CRC 

CRC 1 

CRC_MODE = 0x0000 0000 

CRC_SEED = 0x0000 FFFF 

CRC-16 

= x 16 + x 15 + x 2 + 1 

= 0x0000 

 


XN62Lxxx 

1 

CRC 

CRC 1 

CRC_MODE = 0x0000 0015 

CRC_SEED = 0x0000 0000 

CRC-32 

32 

= + x 26 x+ x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 

= 0xFFFF FFFF 

 

1 

CRC 

CRC 1 

CRC_MODE = 0x0000 0036 

CRC_SEED = 0xFFFF FFFF 

11.3.2 32 

xDSP 32 

1. DIVIDENT . 

2. DIVISOR . 

3. QUOTIENT 

11.3.3 Sin/Cos/Arctan 

xDSP CORDIC (Coordinate Rotation Digital Computer) 

Sin, Cos Arctan. 

1. CORDIC xDSP CORDIC 32 

CORDIC 16 

32 

RES 

CORDIC_X, CORDIC_Y CORDIC_PH 

 


XN62Lxxx 

2. 

CORDIC_X, CORDIC_Y CORDIC_PH 

Phase: -π/2 +π/2 CORDIC 

-π/2 +π/2 -0x64 

ED51 +0x6487 ED51 32 -0x6487 ED51 ( >> 16) +0x6487 (+0x6487 ED51 >> 16) 16 

 

CORDIC x, y : ([RES:0] 

) -1 +1 

 

32 CORDIC -0x7FFF FFFF -1+0x7FFF FFFF 

+1 

3. CORDIC xDSP CORDIC Sin, Cos Arctan 

4. Sin : 

a) CORDIC_PH 

b) CORDIC 10Sin/Cos 

c) CORDIC_RLTY 

5. Cos : 

a) CORDIC_PH 

b) CORDIC 10Sin/Cos 

c) CORDIC_RLTX 

6. Arctan : 

a) CORDIC_X CORDIC_Y 

b) CORDIC 01Arctan 

c) CORDIC_RLTPH 

11.3.4 

XN62L 

16 FIR 

5 IIR 

16 

36 . 


XN62Lxxx 

FILTER_D0 

D 

D 

D 

D 

D 

D 

C0 

C1 

C2 

C3 

 

Cn 

Cn+1 

Cn+2 

+ + + + + + 

Shift & clamp 

FILTER_RESULT 

Figure 11-1: n+2 FIR 

FILTER_D0 

D 

D 

D 

D 

D 

D 

D 

D 

D 

C0 

C1 

C2 

C3 

C4 

Cn 

Cn+1 

Cn+2 

Cn+1 

Cn+2 

+ + + 

+ 

+ + + 

Shift & 

+ + FILTER_RESULT 

clamp 

Figure 11-2: 5 IIR 

Figure 11-1 Figure 11-2 D 

2 

16 FIR 

32 

FILTER_STAT 

xDSP 

FILTER_CR FILTER_MODE 

 

DMA DMA 

UART, 

TWS, ADC, SPI 

DMA_xDSP0 DMA 

DMA_xDSP1 DMA DMA 

 

5 IIR DMA 

Y=A0*X(n)+A1*X(n-1)+A2*X(n-2)+A3*X(n-3)+A4*X(n-4)+A5*X(n-5)-B1*Y(n-1)- B2*Y(n-2)- B3*Y(n-3)- B4*Y(n-4)- B5*Y(n-5): 

1. DMA_XDSP0_info DMA 

2. DMA_XDSP1_info DMA 

3. FILTER_CR: (1

XN62Lxxx 

5. 


XN62Lxxx 

12 UART 

12.1 

XN62L : UART1, UART2 UART0, UART3 

IrDA 


UART 

( UART0CLKDIV / 

UART1CLKDIV / UART2CLKDIV / UART3CLKDIV) 

IRDAEN bit 

TX 

IrDA Transmit 

Encoder 

TXDn Pin 

UART 

IRDAEN bit 

RX 

IrDA Receiver 

Decoder 

RXDn Pin 

Figure 12-1: UART/IrDA 

Transmitter Buffer 

Shift Register 

TX 

TX FSM 

APB 

Interface 

Baud Rate Generator 

RX FSM 

Receiver Buffer 

Shift Register 

RX 

Figure 12-2: UART 


XN62Lxxx 

12.2 

Table 12-1: UART0,1, 2, 3 

 

RXD0 UART0 

TXD0 UART0 

RXD1 UART1 

TXD1 UART1 

RXD2 UART2 

TXD2 UART2 

RXD3 UART3 

TXD3 UART4 

12.3 UART 

UART 

• UART0 0x4000 8000 

• UART1 0x4000 C000 

• UART2 0x4007 0000 

• UART3 0x4007 4000 

UART 

Table 12-2: 

(UART0: -0x4000 8000; UART1 - 0x4000 c000; UART2: -0x4007 0000; UART3 

-0x4007 4000) 

 

RBR RO 0x000 

NA 

THR WO 0x000 

NA 

STATE R/W 0x004 RBR THR 

 

CTRL R/W 0x008 UART 

INTSTATUS R/W 0x00C UART 

0x00 

0x00 

0x0 

BAUDDIV R/W 0x010 UART 0x10 

12.3.1 

RBR UART 

Table 12-3: UART 

(RBR) www.xinnovatech.com 205

XN62Lxxx 

 

7:0 RBR UART 

UART 

NA 

31:8 - - 

12.3.2 

THR. 


(THR) 

7:0 THR 

UART 

UART TX NA 

 

31:8 - - 

12.3.3 UART 

STATE 

UART 

Table 12-5: UART (STATE) 

 

1:0 - - . 00 

2 THROE 0 

1 

1 

3 RBROE 0 

1 

1 

4 BRADRDY 

0 

1 

1 

31:5 - - . NA 

12.3.4 UART 

CTRL UART 

Table 12-6: UART (CTRL3) 

 

0 THRE THR 0 

0 THR . 

1 THR 

1 RBRE RBR 0 

0 RBR . 

1 RBR. 

2 THRIE THR 

 

0 

0 THR . 


XN62Lxxx 

1 THR . 

3 RBRIE RBR 

0 

0 RBR . 

1 RBR . 

4 THROIE THR 0 

0 THR 

. 

1 THR 

. 

5 RBROIE RBR 0 

0 RBR . 

1 RBR . 

6 THRHS THR 

0 0 

0 

1 

7 IRDAEN IrDA 0 

0 IrDA 

1 IrDA 

8 DMATXEN TX DMA 0 

0 

1 

9 DMARXEN RX DMA 0 

0 

1 

14:10 - - NA 

15 BRADEN 0 

0 

1 

31:10 - - NA 

12.3.5 UART 

INTSTATUS UART 


(INTSTATUS) 

 

0 THRIES 

0 

0 

1 

1 

1 RBRIES 0 

0 

1 

1 

2 THROIES 

0 


XN62Lxxx 

0 

1 

1 

3 RBROIES 

0 

0 

1 

1 

31:4 - - . NA 

STATE STATE 

 

 

12.3.6 UART 

UART 

(BAUDDIV) 

UART CLKDIV UART PCLK 


(BAUDDIV) 

 

19:0 BAUDDIV 

16 

0x10 

31:20 - . 0 

 

UART baudrate=UARTn_PCLK / BAUDDIV 

UARTn_PCLK UART 

12.4 

12.4.1 UART 

 

UART UART 1 

, , 8 1 , 

. 

 

 

BAUDDIV 

BAUDDIV UART 

CTRL BRADEN 

0x80 

UART 

UART 


XN62Lxxx 

12.4.2 IrDA 

UART 

IRDAEN IrDA 

IrDA UART RXDn/TXDn 

3/16 / 

 

IrDA 1.63us 

UART IrDA 

 

TX 

Start Bit 

0 

Bit Period 

Stop Bit 

1 0 1 0 0 

1 1 0 1 

IrDA OUT 

IrDA IN 

3/16 

RX 

0 

1 

0 1 0 0 1 1 0 1 

Figure 12-3: UART IrDA 


XN62Lxxx 

13 SPI 

13.1 

XN62L SPI (Serial Peripheral interface) 

SPI 4 SSI (Synchronous Serial 

Interface )/ 

4 16 SPI_PCLKsystem SYSAHBCLKDIV clock 

• SPI 4 SSI 

• 

• / 

• 8 FIFO 

First In First Out 

• 4 

-16- 

13.2 

Table 13-1: SPI 

 

 

 

 

 

SPI SSI 

SCK I/O SCK CLK 

SCK/CLK 

SPI 

 

SPI 

SSEL I/O SSEL FS / 

SPI 

 

 

SPI 

 

 

 

MISO I/O MISO DR(M) 

DX(S) 

MISO 

 

SPI 

SPI 

SPI FS/SSEL 

MOSI I/O MOSI DX(M) 

DR(S) 

MOSI 

 

SPI 

SPI 

13.3 

Table 13-2: 

( 0x4004 0000) 


XN62Lxxx 

 

CR0 R/W 0x000 0 

0x0 

CR1 R/W 0x004 1 / 

DR R/W 0x008 

FIFO 

0x0 

0x0 

SR RO 0x00C 0x0000 0003 

CPSR R/W 0x010 SPI 0x0 

IMSC R/W 0x014 

0x0 

RIS RO 0x018 

- 

MIS RO 0x01C 0x0000 0008 

ICR WO 0x020 

NA 

DMACR R/W 0x024 DMA 0x0 

13.3.1 SPI 

0 

 

SPI . 

Table 13-3: SPI 0 (CR0 - 0x4004 0000) 

 

3:0 DSS 

0000 

0x0~0x2 

0x3 

0x4 

0x5 

0x6 

0x7 

0x8 

0x9 

0xA 

0xB 

0xC 

0xD 

0xE 

0xF 

 

4- 

5- 

6- 

7- 

8- 

9- 

10- 

11- 

12- 

13- 

14- 

15- 

16- 

5:4 FRF 00 

0x0 

0x1 

0x2 

0x3 

SPI 

SSI 

 

 

6 CPOL 

SPI 0 

0 SPI 

1 SPI 


XN62Lxxx 

7 CPHA 

SPI 0 

31:8 - . 

0 SPI 

1 SPI 

13.3.2 SPI 

1 

 

SPI 

Table 13-4: SPI 1 (CR1 - 0x4004 0004) 

 

0 LBM 

0 

0 

1 MISO 

MOSI 

1 SSE SPI 0 

0 SPI 

1 SPI 

SPI 

2 MS / SSE 

0 

0 SPI 

SCLKMOSI SSEL MISO 

1 SPI 

MISO SCLKMOSI SSEL 

3 SOD (MS 1 0 

= 1) 

SPI (MI 

SO) 

4 CSFL SPI SSEL 0 

0 SSEL 

1 SSEL 

SSE=1 5 RSFR FIFO 0 

0 FIFO 

1 FIFO 

6 FILTEN SPI 0 

0 

1 

31:7 NA 

13.3.3 SPI 

 


(DR - 0x4004 0008) 

 


XN62Lxxx 

15:0 DATA 

TNF 1 Tx FIFO 

0x0000 

 

Tx FIFO 

SPI 

 

 

16 

 

RNE 1 Rx FIFO 

 

SPI Rx FIFO 

16 

0 31:16 - - 

13.3.4 SPI 

 

SPI 

Table 13-6: SPI (SR - 0x4004 000C) 

 

0 TFE FIFO 

FIFO 

1 0 1 

1 TNF FIFO Tx FIFO 

0 1 1 

2 RNE FIFO 

FIFO 

0 1 0 

3 RFF FIFO 

FIFO 

1 0 0 

4 BSY SPI 

0 / 

/ Tx FIFO 

 

1 

31:5 - NA 

0 

13.3.5 SPI 

 

SPI SPI 

SPI SPI_PCLK 

 


(CPSR - 0x4004 0010) 

 

7:0 CPSDVSR 

3 255 SPI_PCLK 

0 0 

0 

31:8 

CR1 FILTEN CPSDVSR 

 

7 

: CPSR 

13.3.6 SPI 

 

 

SPI 4 


(IMSC - 0x4004 0014) 

 


XN62Lxxx 

0 RORIM 

Rx FIFO 

1 0 

 

1 RTIM 

1 Rx FIFO “ 

0 

” 

SPI 

 

PCLK/(CPSDVSR × [SCR+1]) 32 

2 RXIM Rx FIFO 

1 0 

3 TXIM Tx FIFO 

1 0 

31:4 - NA 

13.3.7 SPI 

IMSC 

1 


(RIS - 0x4004 0018) 

 

0 RORRIS Rx FIFO 

1 0 

1 RTRIS 

Rx FIFO “ ” 

0 

 

SPI 


2 RXRIS Rx FIFO 

1 0 

3 TXRIS Tx FIFO 

1 1 

31:4 - NA 

13.3.8 SPI 

 

IMSC 1 SPI 

 


(MIS - 0x4004 001C) 

 

0 RORMIS Rx FIFO 

1 0 

1 RTMIS Rx FIFO “ ” 

1 0 

 

SPI PCLK/(CPSDVSR × [SCR+1]) 32 

2 RXMIS Rx FIFO 

1 0 

3 TXMIS Tx FIFO 

1 0 

31:4 - NA 


XN62Lxxx 

13.3.9 SPI 

 

1 SPI FIFO / 

FIFO IMSC 


(ICR - 0x4004 0020) 

 

0 RORIC 1 Rx FIFO 

NA 

1 RTIC 1 Rx FIFO 

NA 

 

SPI 


31:2 - NA 

13.3.10 SPI DMA 

DMACR DMA / 

Table 13-12: SPI DMA 

(DMACR - 0x4004 0024) 

 

0 RXDMAE DMA 0 

0 DMA 

1 FIFO DMA 

1 TXDMAE DMA 0 

0 DMA 

1 FIFO DMA 

31:2 NA 

13.4 

13.4.1 SPI 

SPI 4 

SSEL SPI 

 

SCK 

SPICR0 

CPOL CPHA 

(CPOL) (CPHA) 

 

CPOL 

0 SCK 

CPOL 1 

CLK 

CPHA 

CPHA 0 

CPHA 

1 

CPOL=0, CPHA=0 SPI 

CPOL = 0 CPHA = 0 SPI 


XN62Lxxx 

CLK 

SSEL 

MOSI 

MSB 

LSB 

MISO 

MSB 

LSB 

Q 

4 to 16 bit 

a. Single transfer with CPOL = 0 and CPHA = 0 

MSB 

LSB 

MSB 

LSB 

MSB 

LSB 

Q 

MSB 

LSB 

Q 

4 to 16 bit 

4 to16 bit 

Figure 13-1: CPOL=0 CPHA=0 SPI a) b) 

 

• CLK 

• SSEL 

CSFL=0 

• MOSI/MISO 

SPI FIFO 

SSEL 

 

MISO 

MOSI1/2 SCK 

MOSI 

1/2 SCK SCK 

SCK 

SCK 

SCK 

SSEL 

CSFL=0 CSFL=1 SSEL 

CPOL=0, CPHA=1 SPI 


CLK 

SSEL 

MOSI 

MSB 

LSB 

MISO 

Q 

MSB 

LSB 

Q 

4 to 16 bit 


XN62Lxxx 

Figure 13-2: SPI CPOL = 0 CPHA = 1 

 

• CLK 

• SSELCSFL=0 


SPI FIFO 

SSEL 

MOSI 

1/2 SCK 

SCK SCK 

SCK 

 

SCK SSEL 


CPOL = 1, CPHA = 0 SPI 

CPOL=1 CPHA=0 SPI 

CLK 

SSEL 

MOSI 

MSB 

LSB 

MISO 

MSB 

LSB 

Q 

4 to 16 bit 

a. Single transfer with CPOL = 1 and CPHA = 0 

MSB 

LSB 

MSB 

LSB 

MSB LSB Q 

MSB LSB Q 

4 to 16 bit 

4 to 16 bit 

b. Continuous transfer with CPOL = 1 and CPHA = 0 

Figure 13-3: SPI CPOL = 1 CPHA = 0 (a) (b) 

 

• CLK 




XN62Lxxx 

SPI FIFO 

SSEL 

 

MISO 

MOSI 1/2 SCK 

MOSI 

1/2 SCK SCK 

SCK 

SCK 

SCK SSEL 




CLK 

SSEL 

MOSI 

MSB 

LSB 

MISO 

Q 

MSB 

LSB 

Q 

4 to 16 bit 

Figure 13-4: SPI CPOL = 1 CPHA = 1 

 

• CLK 



SPI FIFO 

SSEL 

MOSI 

1/2 SCK 

SCK SCK 

 

SCK 

SCK SSEL 


13.4.2 SSI 

SPI 

4 


XN62Lxxx 

CLK 

FS 

DX/DR 

MSB 

LSB 

4 to 16 bit 

a. Single frame transfer 

CLK 

FS 

DX/DR 

MSB LSB MSB LSB 

4 to 16 bit 

4 to 16 bit 

b. Continuous/back-to-back frames transfer 

Figure 13-5:4a) 

b) / 2 

 

CLK FS 

SPI DX 

FIFO 

FS 

CLK 

FIFO 

CLK 4 16 MSB DX 

MSB 

DR 

CLK SPI 

CLK 

FIFO 


XN62Lxxx 

14 Flash QSPI 

14.1 

XN62L Flash QSPI 

I/ODUAL I/OQUAD Flash 

SPI (Serial 

Peripheral interface)/ 

Flash QSPI 

_PCLKsystem cloc 

 

SYSAHBCLKDIV 

• / / Flash 

• 

• 16FIFO 

First In First Out 

• SPI 00,0 3 1,1 

14.2 

Table 14-1: Flash 

 

 

QSPI_CLK I/O 

CLK 

QSPI_CS I/O Flash 

C 

LK 

 

QSPI_DI(IO 0) I/O Flash ( / 

0) (1) 

QSPI_DO(IO 1) I/O Flash ( / 

1) (1) 

QSPI_WP(IO 2) I/O Flash ( / 

2) (2) 

QSPI_HOLD(IO 3) I/O Flash ( / 

(1). IO 0 IO 1 I/O 

 

(2). IO 0-IO 3 I/O 

3) (2) 

14.3 

Table 14-2: ( 0x4007 8000) 

 

CR0 R/W 0x000 0 0x08 

CR1 R/W 0x004 1 / 

DR R/W 0x008 

FIFO 

0x0 

NA 

SR RO 0x00C 0x03 

CPSR R/W 0x010 0x0 


XN62Lxxx 

IMSC R/W 0x014 

RIS RO 0x018 

0x0 

0x05 

MIS RO 0x01C 0x0 

ICR WO 0x020 0x0 

DMACR R/W 0x024 DMA 0x0 

14.3.1 Flash 

0 

. 


0 (CR0 - 0x4007 8000) 

 

0 ENABLE 0 1 Flash 0 

1 RE 

DUAL QUAD 

/ 

0 

 

2 TE 

DUAL QUAD 

/ 

0 

 

3 CSS CS 1 

4 CPOL 0 

0 

CLK 

1 

CLK 

5 CPHA 0 

0 

1 

7:6 MODE Flash 00 

00 

01 DUAL 

10 QUAD 

11 

15:8 RNUM 

0 

RNUM=0 1 

RNUM=255 256 

14.3.2 Flash 

1 

 

Flash 


1 (CR1 - 0x4007 8004) 

 

0 RFIFOCLR FIFO 1 FIFO 0 0 

1 TFIFOCLR FIFO 1 FIFO 0 0 

2 WP Flash WP 

QUAD WP 

IO 2WP 0 

 


XN62Lxxx 

3 HOLD Flash Hold 

QUAD HOLD 

IO 3 HOLD 0 

 

31:4 - - NA 

14.3.3 Flash 

 


(DR - 0x4007 8008) 

 

7:0 DATA 

TNF 1 Tx FIFO 

NA 

 

Tx FIFO 

QSPI 

 

 

RNE 1 Rx FIFO 

 

QSPI Rx FIFO 

31:8 - NA 

14.3.4 Flash 

 

Flash 


(SR - 0x4007 800C) 

 

0 TFE FIFO 

FIFO 

1 0 1 

1 TNF FIFO Tx FIFO 

0 1 1 

2 RNE FIFO 

FIFO 

0 1 0 

3 RFF FIFO 

FIFO 

1 0 0 

4 BSY 

Flash 

0 / 

/ 0 

Tx FIFO 

1 

31:5 - NA 

14.3.5 Flash 

 

Flash QSPI 

_PCLK 

Table 14-7: 

(CPSR - 0x4007 8010) 

 

7:0 CPSDVSR 

1 255 QSPI_PCLK 

0 0 

31:8 

QSPI _PCLK 

: CPSR 


XN62Lxxx 

14.3.6 

 

 

4 Table 14-8: 

(IMSC - 0x4007 8014) 

 

0 TXEND Tx FIFO 

1 0 

1 RXIM Rx FIFO 

1 0 

2 TXIM Tx FIFO 

1 0 

3 RXEND 

RNUM 

1 0 

31:4 - NA 

14.3.7 

IMSC 

1 

Table 14-9: 

(RIS - 0x4007 8018) 

 

0 TXERIS Tx FIFO 

1 1 

1 RXRIS Rx FIFO 

1 0 

2 TXRIS Tx FIFO 

1 1 

3 RXERIS 

RNUM 

1 0 

31:4 - NA 

14.3.8 

 

IMSC 1 

 

Table 14-10: 

(MIS - 0x4007 801C) 

 

0 TXEMIS Tx FIFO 

1 0 

1 RXMIS Rx FIFO 

1 0 

2 TXMIS Tx FIFO 

1 0 

3 RXEMIS 

RNUM 

1 0 

31:4 - NA 

14.3.9 

 

1 

Table 14-11: 

(ICR - 0x4007 8020) 

 


XN62Lxxx 

0 RXERIC 1 FIFO 

(MIS) RXEMIS flash 

FIFONA 

31:1 - NA 

14.3.10 DMA 

DMACR DMA / 

Table 14-12: DMA 

(DMACR - 0x4007 8024) 

 

0 RXDMAE DMA 0 

0 DMA 

1 FIFO DMA 

1 TXDMAE DMA 0 

0 DMA 

1 FIFO DMA 

31:2 NA 

14.4 

14.4.1 

 

SPI 00,0 31,1 

SPICR0 

CPOL CPHA 

CPOL=0, CPHA=0 

CPOL = 0 CPHA = 0 

CLK 

CS 

DI 

MSB 

LSB 

DO 

MSB 

LSB 

Q 

8 bit 

 

• CLK 

• DI/DO 


Figure 14-1: CPOL=0 CPHA=0 



XN62Lxxx 

CLK 

CS 

DI 

MSB 

LSB 

DO 

Q 

MSB 

LSB 

Q 

8 bit 

Figure 14-2: CPOL = 1 CPHA = 1 

 

• CLK 

• DI/DO 

14.4.2 DUAL 

 

Flash 

DUAL / 

IO 0 IO 1 

DUAL Flash 

Begin with Standard Mode 

CLK 

CS 

DI(IO0) 

MSB 

LSB 

MSB 

LSB 

DO(IO1) 

High Impedance 

8 bit 

address 

Change to DUAL mode 

CLK 

CS 

DI(IO0) 

6 4 2 0 

6 4 2 0 

DO(IO1) 

7 5 3 1 

7 5 3 1 

dummy 

Figure 14-3:DUAL Flash 


XN62Lxxx 

14.4.3 QUAD 

QUAD / 

IO 0IO 1IO 2IO 3 QUAD Flash 

Begin with Standard Mode 

CLK 

CS 

DI(IO0) 

MSB 

LSB 

MSB 

LSB 

DO(IO1) 

High Impedance 

WP(IO2) 

HOLD(IO3) 

8 bit 

address 

Change to QUAD mode 

CLK 

CS 

DI(IO0) 

 

 

 

 

 

DO(IO1) 

 

 

 

 

 

WP(IO2) 

 

 

 

 

 

 

 

 

HOLD(IO3) 

 

 

 

 

 

 

 

 

dummy 

byte0 byte1 byte2 byte3 

igure 14-4: QUAD Flash 

F 


XN62Lxxx 


XN62Lxxx 

15 TWS 

15.1 

TWS 

I 2 C 

I 2 C • I 

2 

C 

• TWS 

• 

• 

• 3MHz 

• 4 

 

• TWS 

pull-up 

resistor 

pull-up 

resistor 

SDA 

Compatible I 2 C bus 

SCL 

SDA SCL 

XN62L 

OTHER XN62L 

OTHER I 2 C 

Compatible 

DEVICE 

Figure 15-1: TWS 

15.2 

Table 15-1: TWS 

 

SDA 

SCL 

/ 

/ 

TWS 

TWS 


XN62Lxxx 

15.3 

Table 15-2: 

( 0x4000 0000) 

 

 

CONSET R/W 0x000 TWS 

1 TWS 

0x00 

0 

STAT RO 0x004 TWS 

TWS 

0x1F 

 

DAT R/W 0x008 TWS 

. / 

/ 0x00 

 

ADR0 R/W 0x00C TWS 

0 7 

TWS 0x00 

 

. 

SCLH R/W 0x010 

TWS 

SCLL R/W 0x014 

TWS 

0x04 

0x04 

CONCLR WO 0x018 TWS 

1 TWS 

NA 

0 TWS 

- - 0x01C 0x00 

ADR1 R/W 0x020 TWS 

1 7 

TWS 0x00 

 


2 7 

TWS 0x00 

 


3 7 

TWS 0x00 

 

DATA_ 

BUFFER 

RO 0x02C 

. 

9 8 ACK NACK DAT 0x00 

 

8 

DATA_BUFFER 

MASK0 R/W 0x030 TWS 

0 

ADR0 0x00 


1 

ADR0 0x00 


2 

ADR0 0x00 

MASK3 R/W 0x03C TWS 

3 

ADR0 0x00 

15.3.1 TWS 

CONSET TWS 

1 TWS 

0 Table 15-3: TWS 

(CONSET - 0x4000 0000) 

 

0 TXRX / 

1 MASL / 

0x0 

0x0 

2 AA 0x0 

3 SI TWS 

0x0 


XN62Lxxx 

4 STO 0x0 

5 STA 0x0 

6 TWSEN TWS 0x0 

31:7 - 0x0 

TXRX: / 

• TXRX 1 , TWS 

• TXRX 0 , TWS 

MASL: / 

• MASL 1 , TWS 

• MASL 0 , TWS 

AA: 

• AA 1 SCL 

1. 

2. TWS 

3. TWS 

• CONCLR AAC 1 AA AA 0 SCL 

SDA 

1. TWS 

2. TWS 

SI: 

• TWSSI 

SCL 

SI 

SI 

CONCLR 

SI C1 

STO: 

• TWS 

 

TWS 

STO ST 

 

” 

STO 

STA: 

• 

TWS 

1 TWS 

 

 

STA TWS 

CONCLR 

STAC 1 

STASTA 0 

 

STA STO TWS 

TWS 

 


XN62Lxxx 

TWSEN: TWS 

• TWS EN 1 TWSCONCLR 

TWS 

ENC 1 TWSEN TWSEN 

0 TWS 

• TWSEN 0 SDA SCL TWS 

“ ” STO 

0 TWSEN 

TWS 

TWS 

EN TWS AA 

15.3.2 TWS 

TWS 

TWS TWS 

 


(STAT - 0x4000 0004) 

 

6:0 STATUS TWS 

Table 15-14~Table 15-17. 

0x1F 

8 SLVADDMATCH 

1 0 

9 SLVRXBUFFULL ( 

: 0x08) 0 

10 SLVTXBUFEMPTY ( 

: 0x08) 0 

31: 11 - NA 

15.3.3 TWS 

 

SI 

CPU SI DAT 

DAT 

MSB 7 

 

DAT MSB Table 15-5: TWS 

(DAT - 0x4000 0008) 

 

7:0 DATA 0 

31: 8 - - 

15.3.4 TWS 

0~3 

4 / 

TWS 

Table 15-6: TWS 0 (ADR0- 0x4000 000CADR1 - 0x4000 0020, ADR2 - 0x4000 0024, ADR3 -0x4000 0028)) 

 

0 0 

7:1 ADDR TWS 

0x00 

31: 8 - - 

15.3.5 TWS 


(SCLH - 0x4000 0010) 

 


XN62Lxxx 

15:0 SCLH SCL 0x0004 

31: 16 - - 

15.3.6 TWS 


(SCLL - 0x4000 0014) 

 

15:0 SCLL SCL 0x0004 

31: 16 - - 

: 

 

SCLH SCLL 

SCLH SCL TWS_PCLK 

SCLL 

SCL TWS_PCLK TWS_PCLK 

APB TWS = TWS_PCLK/(SCLH + SCLL) 

15.3.7 TWS 

CONCLR 

CON 

TWS 

1 TWS 

0 Table 15-9: TWS 

(CONCLR - 0x4000 0018) 

 

0 TXRX / 

1 TWSONSET TXRX 0 . NA 

1 MASL / 

1 TWSONSET MASL 0 . 0 

2 AAC 

1 TWSONSET AA 0 0 

3 SIC 

1 TWSONSET SI 0 0 

4 - . NA 

5 STAC 

1 TWSONSET STA 0 0 

6 TWSENC TWS 

1 TWSONSET TWSEN 0 0 

31: 7 - - 

15.3.8 TWS 


(DATA_BUFFER - 0x4000 002C) 

 

7:0 DATA 

DAT 

8 0 

31: 8 - - 

15.3.9 TWS 

0~3 

4 

7 7:1 

ADRn 

 

ADRn 


XN62Lxxx 


(MASK0 - 0x4000 0030, MASK1 - 0x4000 0034,MASK2 - 0x4000 0038, MASK3 - 0x4000 003C) 

 

0 - . 0 

7:1 MASK 0x00 

31: 8 - . 0 

15.4 TWS 

I 2 C 

TWS 

TWS 4 

 

TWS 

15.4.1 

 

CONSET MASL 1 

TXRX 

1 

TWSEN 1 TWS AA 0 

I2C 

STASTO SI 0 CONCLR SIC 1 

SI 

STA STA, STO SI 0SI 1 CONCLR SIC 

 

STA Table 15-12: TWS CONSET 

7 6 5 4 3 2 1 0 

- TWSEN STA STO SI AA MASL TXRX 

- 1 0 0 0 0 1 1 

 

7 

0 

 

 

8 

 

STA TWS 

TWS 

SI STAT 

0x01 

 

DAT 

SI CONCLR SIC 1 SI 

 

R/W SI 

 

0x0b, 0x4b 0x14 

Table 15-14 Table 15-17 

S SLAVE ADDRESS RW=0 A DATA A DATA A/A# P 

n bytes data transmitted 

from Master to Slave 

from Slave to Master 

A = Acknowledge (SDA low) 

A# = Not acknowledge (SDA high) 

S = START condition 

P = STOP condition 

Figure 15-2: 


XN62Lxxx 

successful 

transmission 

to a Slave 

Receiver 

S 

SLA W A DATA A P 

01H 

0BH 

14H 

next transfer 

started with a 

Repeated Start 

condition 

S 

SLA 

W 

Not 

Acknowledge 

received after 

the Slave 

address 

A# P R 

01H 

4BH 

Not 

Acknowledge 

received after a 

Data byte 

A# P 

54H 

to Master 

receive 

mode, 

entry 

= MR 



DATA 

A 

any number of data bytes and their associated Acknowledge bits 

n 

This number (contained in STAT) corresponds to a defined state of the TWS bus 

Figure 15-3: 

15.4.2 

 

(SLA+R) 

DAT 

CON SI 

(SI) 

STAT 

0x0b, 0x4b, 0x1d.(AA 0x680x78 = 1) 0xB0 Table 15-15 

TWS 

SI AA 

TWS 

 

SI 

AA 

TWS “ ” 

 

” 

SI STO STA 

SI 


XN62Lxxx 

S SLAVE ADDRESS RW=1 A DATA A DATA A# P 

n bytes data received 







Figure 15-4: 

MR 

successful 

transmission 

to a Slave 

transmitter 

S 

SLA R A DATA DATA A# P 

01H 

0BH 

1DH 

1DH 

next transfer 

started with a 

Repeated Start 

condition 

S 

SLA 

R 

Not 

Acknowledge 

received after 

the Slave 

address 

A# P W 

21H 

22H 

4BH 

to Master 

transmit 

mode, 

entry 

= MT 



DATA 

A 


n 

this number (contained in STAT) corresponds to a defined state of the TWS bus 

Figure 15-5: 

15.4.3 

 

-3) (MASK0 

-3) 

TWS (CONSET) 

Table 15-13: TWS CONSET 

 


XN62Lxxx 

7 6 5 4 3 2 1 0 

- TWSEN STA STO SI AA MASL TXRX 

- 1 0 0 0 1 0 0 

MASL 0 TWSEN 

TWS AA 1 STA 

STO SI 0 ADR CONSET TWS 

0(W) 

 

1(R)SI 

(STAT) 

 

Table 15-16 S SLAVE ADDRESS RW=0 A DATA A DATA A/A# P/Sr 








Sr = Repeated START condition 

Figure 15-6: 


XN62Lxxx 

reception of the 

own Slave 

address and one 

or more Data 

bytes all are 

acknowledged 

S 

SLA 

W A DATA A DATA 

A 

P PORS 

S 

01H 

0AH 

13H 

13H 

1DH 

Last data byte 

received is Not 

acknowledged 

A# A P PORS 

S 

13H 


General Call 


or more Data 

bytes 

GENERAL CALL W A DATA A DATA 

A 

P PORS 

S 

0AH 13H 13H 1DH 

last data byte is 

Not acknowledged 

A# A P PORS 

S 

13H 



DATA 

A 


n 


Figure 15-7: 

15.4.4 

 

1 

SDA SCL 

TWS / 

TWS 

 

S SLAVE ADDRESS RW=1 A DATA A DATA A# P 








Figure 15-8: 


XN62Lxxx 


own Slave 


or more Data 

bytes all are 

acknowledged 

S 

SLA 

R A DATA A DATA A# A P PORS 

S 

4AH 

5CH 

1CH 



DATA 

A 


n 


Figure 15-9: 

15.4.5 

TWS 

XN62L 

TWS 

TWS 

SLVADDMATCHSLVRXBUFFULL SLVTXBUFEMPTY TWS 

TWS 

SLVADDMATCH 1 SLVRXBUFFULL 

1 

TWS 

SLVTXBUFEMPTY 1 

 

TWS 

 

SLVADDMATCH=1 

/ 

SLVRXBUFFULL=1 

TWS 

DAT 

SLVTXBUFEMPTY=1 

 

DAT 

 

Figure 15-10: 


XN62Lxxx 

15.4.6 

TWS 

Table 15-14: 

TWS 

TWS 

/ DAT 

CON 

STA TXRX STO SI AA 

0x01 

 

SLA+W; 

X 1 0 0 X SLA+W ACK 

STA 

0x01 

 

SLA+W X 1 0 0 X . 

SLA+R; 

X 1 0 0 X SLA+RTWS 

STA 

0x0b 

SLA+W; 0 1 0 0 X 

ACK ACK 

DAT 1 1 0 0 X 

DAT 0 1 1 0 X 

STO 

DAT 1 1 1 0 X 

STO 

0x4b 

SLA+W 

0 1 0 0 X 

ACK ACK 

DAT 1 1 0 0 X 

DAT 0 1 1 0 X 

STO 

DAT 1 1 1 0 X 

STO 

0x14 

DAT 

0 1 0 0 X 

ACK 

ACK DAT 1 1 0 0 X 

DAT 0 1 1 0 X 

STO 

DAT 1 1 1 0 X 

STO 

0x54 

DAT 

0 1 0 0 X 

ACK 

ACK DAT 1 1 0 0 X 

DAT 0 1 1 0 X 

STO 

DAT 1 1 1 0 X 

STO 

Table 15-15: 

TWS 

TWS 

/ DAT 

CON 


0x01 

0x22 

 

SLA+R X 1 0 0 X SLA+W ACK 

 

SLA+R X 1 0 0 X 

SLA+W X 1 0 0 X SLA+WTWS 


XN62Lxxx 

DAT 1 1 0 0 X 

0x0b 

SLA+W; 

DAT 0 0 0 0 0 

ACK ACK 

DAT 0 0 0 0 1 

ACK 0x4b 

SLA+W DAT 1 1 0 0 X 

ACK 

DAT 0 1 1 0 X 

STO 

DAT 1 1 1 0 X 

STO 

0x1d 

0 0 0 0 0 

ACK 0 0 0 0 1 

ACK 0x5d 

1 1 0 0 X 

0 X 1 0 X 

STO 

1 X 1 0 X 

STO 

Table 15-16: 

TWS 

TWS 

/ DAT 

CON 


0x0a 

 

SLA+W 

DAT X 0 0 0 0 

ACK ACK 

DAT X 0 0 0 1 

ACK 0x13 

 

X 0 0 0 0 

ACK 

 

X 0 0 0 1 

ACK 

ACK 

0x13 

 

0 0 0 0 0 

SLV 

SLA 

 

0 0 0 0 1 

SLV 

SLA 

 

ACK 

1 0 0 0 0 

SLV 

SLA 

 

1 0 0 0 1 

SLV 

SLA 

 

0x13 

 

X 0 0 0 0 

ACK 

 

X 0 0 0 1 

ACK 

ACK 

0x1d 

 

DAT 0 0 0 0 0 

SLV 

SLA 

 

DAT 1 0 0 0 0 

SLV 

SLA 

 

 

 

Table 15-17: 

TWS 

TWS 

/ DAT 

CON 


XN62Lxxx 


0x4a 

 

SLA+W 

X 0 0 0 X 

ACK ACK 

0x5C 

DAT X 1 0 0 0 

ACK ACK 

X 1 0 0 1 

ACK 0x1C 

DAT DAT 0 1 0 0 0 

SLV 

SLA 

 

ACK 

DAT 0 1 0 0 1 

SLV 

SLA 

DAT 1 1 0 0 0 

SLV 

SLA 

 

DAT 1 1 0 0 1 

SLV 

SLA 

 

0x1C 

DAT DAT 0 X 0 0 X 

SLV 

SLA 

(AA = 0) DAT 1 X 0 0 X 

SLV 

SLA 

ACK 

 

15.4.7 TWS 

 

TWS 

• TWS 

• TWS 

• TWS 

13 

15.4.7.1 

TWS 

1. ADR 

2. T WS 

3. CONSET 

0x42 EN MASL 

0x40 

15.4.7.2 

 

1. 

2. 

3. CONSET 0x20 STA 

4. 

5. 


XN62Lxxx 

15.4.7.3 

 

 

1. 

2. 

3. CONSET 0x20 STA 

4. 

5. 

6. 

15.4.7.4 TWS 

TWS 

• STA TWS 

• 13 

15.4.7.5 

: 0x01 

 

SLA+R/W ACK 

1. DAT R/W 

2. CONSET 0x04 AA 

3. CONCLR 0x08 SI 

4. 

5. 

6. 

7. 

: 0x0b 

 

R/W ACK 1. DAT R/W 

2. CONSET 0x04 AA TXRX . 


4. 

5. 

6. 

7. 


XN62Lxxx 

15.4.7.6 

: 0x0b 

0x01 

ACK 

1. DAT 


3. 1 

4. 

: 0x4b 

 

ACK 

1. CONSET 0x14 STO AA 


3. 

: 0x14 

 

ACK 

1. 1 

5 

2. 11 



5. 

6. DAT 

7. CONSET 0x 04 AA 


9. 1 

10. 

11. CONSET STA MASL 

12. +R 

13. CONCLR 0x0 8 SI 

14. 

: 0x54 

 

ACK 




XN62Lxxx 

3. 

15.4.7.7 

: 0x0b 

0x01 

ACK 

1. CONCLR 0x0 9 SI TXRX 

2. 

: 0x1b 

 

ACK 



3. 

: 0x1d 

 

ACK DAT 

ACK 

ACK 

1. DAT 

2. 1 

5 

3. CONCLR 0x0C SI AA 

4. CONSET 0x1 0 STO 

4. 


6. 1 

7. 

: 0x5d 

 

ACK DAT 

1. DAT 



4. 

15.4.7.8 

: 0x0a 

 

SLA+W ACK 


XN62Lxxx 


2. 

3. 

4. 

: 0x13 

 

ACK 

1. DAT 

2. 1 

5 

3. CONCLR 0x0C SI AA 

4. . 


6. 1 

7. 

: 0x13 

 

ACK 


2. 

: 0x1d 

 


2. 

15.4.7.9 

: 0x4a 

 

ACK 

1. DAT 

2. CONCLR 0x09 SI TXRX 

3. 

4. 1 

5. 

: 0x5c 

 

ACK 

1. DAT 

. 


XN62Lxxx 


3. 1 

4. 

: 0x1c 

 

ACK 


2. . 


XN62Lxxx 

16 RTC 

16.1 

1 Hz/1KHz RTC 

 

RTC • 32 kHz 

• 1 1KHz 

 

• 32RTC 

• 

16.2 

Table 16-1: RTC 

 

RTCXIN 32 kHz 

RTCXOUT 32 kHz 

16.3 RTC 


( 0x4005 0000) 

 

DR R 0x000 0x00 

MR R/W 0x004 0x00 

LR R/W 0x008 0x00 

CR R/W 0x00C 0x00 

ICSC R/W 0x010 

0x00 

RIS R 0x014 0x00 

MIS R 0x018 

ICR W 0x01C 

0x00 

0x00 

16.3.1 RTC 


(DR - 0x4005 0000) 

 

31:0 DATA 

. 0x00 

16.3.2 RTC 


(MR - 0x4005 0004) 


XN62Lxxx 

 

31:0 MATCH RTC 

. 0x00 

16.3.3 RTC 


(LR - 0x4005 0008) 

 

31:0 RTC 

. 0x00 

16.3.4 RTC 

/ 

(R/W) 

RTC 

RTC 

 

0 


(CR - 0x4005 000C) 

 

0 RTCSTART RTC 

RTC 

0x0 

(POR) 

0 RTC . 

1 RTC 

31:1 - - . - 

16.3.5 RTC 

R/W 

RTC 

RTC 

Table 16-7: RTC Mask (ICSC - 0x4005 0010) 

 

0 RTCIC 

RTC 0x0 

0 0 

1 1 

31:1 - - . 0x0 

16.3.6 RTC 

(RO) 

 


(RIS - 0x4005 0014) 

 

0 RTCRIS 

0x0 

31:1 - . 0x0 


XN62Lxxx 

16.3.7 RTC 

 


(MIS - 0x4005 0018) 

 

0 RTCMIS 

ICR 

0x0 

31:1 . Read as zero. 0x0 

16.3.8 RTC 

 

1 

0 Table 12-16-10: RTC 

(ICR - 0x4005 001C) 

 

0 RTCICR 

1 

0 0x0 

31:1 . 0x0 

16.4 

RTC 

Deep-sleep Power-down 

RTC 

RTC 

RTC RTC 

 

: RTC 

RTC “ 

”RTC 


XN62Lxxx 

17 ADC/DAC 

17.1 

XN62L 3 12 ADC 1 10 DAC 

 

• 3 1M Hz 1 2 A/D 

• ADC 8 AD 

• 12 A/D 

• 

• ADC 0 ~ V REF_ADC. 

• 

ADC • ADC -. 

• ADC 8 

• -40°C 

+120°C 

• 1M Hz D/A 

RESULT0 

AD0 

AD1 

AD2 

AD3 

12bit 

ADC0 

RESULT1 

RESULT2 

RESULT3 

RESULT4 

RESULT5 

HILMT 

CHNSEL0 

DMA, iterrupt 

request 

RESULT6 

AD4 

AD5 

AD6 

AD7 

4,5,6 

12bit 

ADC1 

RESULT7 

HILMT 

CHNSEL1 

HILMT0 

> 

Interrupt 

enable 

Interrupt 

AD8 

AD9 

AD10 

AD11 

12bit 

ADC2 

Temperature 

sensor 

LOLMT 

CHNSEL0 

HILMT1 

> 

LOLMT0 

< 

Interrupt 

PWM 

PWM Fault 

LOLMT1 

< 

enable 

or 

LOLMT 

CHNSEL0 

Figure 17-1: ADC 


XN62Lxxx 

17.2 

Table 17-1: ADC 

 

AD0~AD11 

ADC 

V REF_ADC 3.3 V . 

DA0 

V REF_ADC ADC 

17.3 


(ADC0: 0x4002 0000; ADC1: 0x4006 4000; ADC2: 0x4006 8000) 

 

 

CR R/W 0x000 ADC 

CR 

0x0 

GDR R/W 0x004 ADC 

ADC NA 

CHSEL R/W 0x008 0x0 

INTEN R/W 0x00C ADC 

 

ADC 

DONE ADC 0x0000 

 

0100 

DR0 R/W 0x010 A/D 

0 

CHSEL SEL0 

NA 

DR1 R/W 0x014 A/D 

1 

CHSEL SEL1 

NA 

DR2 R/W 0x018 A/D 

2 

CHSEL SEL2 

NA 

DR3 R/W 0x01C A/D 

3 

CHSEL SEL3 

NA 

DR4 R/W 0x020 A/D 

4. 

CHSEL SEL4 

NA 

DR5 R/W 0x024 A/D 

5 

CHSEL SEL5 

NA 

DR6 R/W 0x028 A/D 

6 

CHSEL SEL6 

NA 

DR7 R/W 0x02C A/D 

7 

CHSEL SEL7 

NA 

: ADC1 DR7 

INTSTAT RO 0x030 ADC 

 

DONE OVERRUN 

0 

HILMT R/W 0x034 ADC 

0 

LOLMT R/W 0x038 ADC 

0 

- - 0x03C 0 

SSCR R/W 0x040 0 

Table 17-3: DAC 

( 0x4006 C000) 

 

 

DACCTL R/W 0x00 D/A 

. 0 

DACBUF W 0x04 DA NA 

17.3.1 ADC 

ADC 

A/D 


XN62Lxxx 

Table 17-4: A/D 

(CR) 

 

7:0 0x0 

15:8 CLKDIV A/D ADC 

(PCLK) ADC 

0x0 

 

16MHz ADC 16 ADC 

1MHz 

16 BURST ADC 0 

0 

ADC START 

ADC 

DR 

1 

1 START 0 ADC 

ADC 

DR 

ADC 23:17 - - . 0x0 

27:24 START ADC 

ADC ADC 0x0 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

0x7 

0x8 

0x9 

0xa 

 

 

CT16B0_CAP0 

28 CT16B0_CAP1 

28 CT32B0_MAT0 

28 CT32B1_MAT0 

28 CT16B0_MAT0 

28 CT16B1_MAT0 

28 PWM0 

PWM1 

PWM2 

28 EDGE 0 

0 

1 

29 SCMODE ADC 0 

0 

1 

1 

31:30 - - . 0x0 

17.3.2 ADC 

 

ADC 


(GDR) 


XN62Lxxx 

11:0 RESULT DONE 1 

SELNO 

A/D X 

0 

V SS; 

0xFFF 

V REF_ADC 

14:12 SELNO 

0 CHSEL) 

SEL0 A/D 

1 000 

CHSEL) SEL1 A/D 

15 OVERRUN 1 

A/D 

0 

16 DONE 1 A/D 

0 

31:17 - NA 

17.3.3 ADC 

 

AD ADC 

8 AD 

12 AD0~AD11 

ADC0~3 0~7 

AD0~AD7 

ADC0 0~7 

AD0~AD6 

ADC1 0~7 

AD4~AD11 

ADC2 0~7 


(CHSEL) 

 

0 SEL0EN SEL0 A/D 0 

0 SEL0 A/D 

1 SEL0 A/D 

3:1 SEL0 AD ADC 

DR0 ADC 0~7 000 

 


0 SEL1 A/D 

1 SEL1 A/D 


DR1 ADC 0~7 000 

 


0 SEL2 A/D 

1 SEL2 A/D 


DR2 ADC 0~7 000 

 


0 SEL3 A/D 

1 SEL3 A/D 


DR3 ADC 0~7 000 

 


0 SEL4 A/D 

1 SEL4 A/D 


XN62Lxxx 


DR4 ADC 0~7 000 

 


0 SEL5 A/D 

1 SEL5 A/D 


DR5 ADC 0~7 000 

 


0 SEL6 A/D 

1 SEL6 A/D 


DR6 ADC 0~7 000 

 


0 SEL7 A/D 

1 SEL7 A/D 


DR7 ADC 0~7 000 

 

17.3.4 ADC 

 

A/D 

A/D 

A/D Table 17-7:: A/D 

(INTEN) 

 

7:0 INTEN 0 7 

SEL0 SEL7 A/D 

0x00 

0 

1 A/D 

8 GINTEN 1 ADC DONE 

0 

INTEN 7:0 1 

A/D 

31:9 - . NA 

17.3.5 ADC 

ADC 

A/D 


(DR0 ~ DR7) 

 

11:0 RESULT DONE 1 

SELn ADn X 

 

V REF_ADC V/V 

REF_ADC 0 ADn 

 

V SS 0xFFF ADn 

V REF_ADC 

29:12 - . 0x0 

30 OVERRUN 

RESULT 

0 

1 


XN62Lxxx 

31 DONE A/D 

1 0 

17.3.6 ADC 

A/D 

A/D A/D DRn DONE OVERRUN 

STAT STAT 

DONE “ ” A/D 


(STAT) 

 

7:0 DONE 0 7 

SEL0 SEL7 A/D DONE 0 

15:8 OVERRUN 0 7 

SEL0 SEL7 A/D OVERRRUN 0 

 

16 ADINT A/D 

A/D Done 1 A/D 

0 

INTEN 

1 

17 HILMTFLAG0 0 

0 1 1 0 

18 HILMTFLAG1 1 

1 1 1 0 

19 LOLMTFLAG0 0 

0 1 1 0 

20 LOLMTFLAG1 1 

1 1 1 0 

21 ADCRDY 1 ADC 0 

31:22 - . 0x0 

17.3.7 

 

A/D 

A/D 

ADC 

Table 17-10: ( 

HILMT) 

 

11:0 HILMT0 0~0xFFF 0 . 0 

14:12 CHNSEL0 0~7 0 0~7 

 

SEL0~SEL7 

0 

HILMT0 

15 INTEN0 0 

0 

0 

1 

27:16 HILMT1 0~0xFFF 1 . 0 

30:28 CHNSEL1 0~7 1 0~7 

 

SEL0~SEL7 

0 

HILMT1 

31 INTEN1 1 

0 

0 

1 


XN62Lxxx 

17.3.8 

 

A/D 

A/D 

ADC 

Table 17-11: 

(LOLMT) 

11:0 LOLMT0 0~0xFFF 0 . 0 

14:12 CHNSEL0 0~7 0 0~7 

 

SEL0~SEL7 

0 

HILMT0 

15 INTEN0 0 

0 

0 

1 

27:16 LOLMT1 0~0xFFF 1 . 0 

30:28 CHNSEL1 0~7 1 0~7 

 

SEL0~SEL7 

0 

HILMT1 

31 INTEN1 1 

0 

0 

1 

17.3.9 

 

ADC Table 17-12: 

(SSCR) 

0 ADCTRIG - 1 ADC 0 

31:2 - - . 0 

17.3.10 D/A 

D/A 

D/A 

Table 17-13: D/A (DACCTL) 

 

7:0 DACDIVIDER DACDIVIDER D/A 

1MHz 

0 

=PCLK/DACDIVIDER 

8 DACMODE DA 

0 

 

DAC 

 

4 

0 

1 


XN62Lxxx 

9 DACCLR 

0 1 

0 

 

0 

10 DACINTEN DAC 

DAC 

0 

0x0 

0x1 

 

 

11 DACDMAEN DAC DMA . DAC 

DMA 0x0 

0x1 

DMA 

DMA 

12 DACEN DAC 

0x0 

0x1 

DAC 

DAC 

14:13 - NA 

15 DACBUFSTAT DAC 0 

0 

1 

31:16 - . 0 

17.3.11 D/A 

Table 17-14: D/A 

(DACBUF) 

 

9:0 DACBUF 10 0 

31:10 - . 0 

17.4 

17.4.1 

ADC A/D 

ADC 

8 A/D 

12 

8 

CHSEL 

 

A/D 

A/D 

SEL0 SEL7 SEL0 SEL7 

 


ADC0 ADC1 ADC2 

AD ADC AD ADC AD ADC 

AD0 0 AD0 0 AD4 0 

AD1 1 AD1 1 AD5 1 

AD2 2 AD2 2 AD6 2 

AD3 3 AD3 3 AD7 3 

AD4 4 AD4 4 AD8 4 

AD5 5 AD5 5 AD9 5 


XN62Lxxx 

AD6 6 AD6 6 AD10 6 

AD7 7 

7 AD11 7 

17.4.2 ADC 

ADC 

A/D 

 

ADC 

ADC 

ADC (CAP) 

MAT 

PWM (CA 

MAT 

CR EDGE 17.4.3 

A/D 

DONE 1 

 

DONE DRn 

ADC 17.4.4 ADC DMA 

DMA ADC 

DMA 

: DMA NVIC ADC 

DMA 

DMA DMA 

17.4.5 DAC DMA 

ADC DMA DAC 

DMA 

: DMA NVIC DAC 

DMA 

DMA DMA 

17.4.6 

 

ADC1 SEL7 ADC1 DR7 

 

ADC 

Figure 17-2 

0ºC AD 

 

= ( 

- 0ºC ) * 


XN62Lxxx 

Temperature 

Slope(°C LSB Value) 

Offset(0°C LSB Value) 

` 

Offset(0°C LSB Value) 

LSB 

Figure 17-2: 

XN62L: 

• 0x 07- (ºC / LSB, fixed-point Q15 format) 

• 0x 1657 – (0 AD ºC ) 

 

3.3v 

3.3v 

 

3 1. ADC1 

2. ADC 

3. ADC 

ºC 


XN62Lxxx 

18 

18.1 

 

DA 

6 1 DA 

0 

1 

 

• 

• 

10 DA 

• 

32 

• 

I/O 

NVIC 

• 

AN ALOGLOGIC 

CMPn_LEVEL 

VDD(3V3) 

32 

+ 

- 

DIGITAL LOGIC 

C0_OUT 

CMP0_LEVEL 

C0_IN[0:5] 

DA Output 

C1_IN[0:5] 

6 

6 

+ 

- 

C1_OUT 

CMP1_LEVEL 

sync 

INT 

14 

APB REGISTERS 

6 

CMP_REG 

7 

edge detect 

CMP0_EDGE 

CMP1_EDGE 

VLAD_REG 

APB INTERFACE 

PCLK 

Figure 18-1: 

18.2 

Table 18-1: 

 

ACMP0_I[3:0] 0 ACMP0_I[0] ACMP0_I[1] 1 

ACMP1_I[3:0] 1 ACMP1_I[0] ACMP1_I[1] 0 


XN62Lxxx 

ACMP0_O 0 

ACMP1_O 1 

18.3 

Table 18-2: 

: ( 0x4005 4000) 

 

CCR R/W 0x00 0 

VLAD R/W 0x04 

0 

- - 0x08 NA 

INTSTA R/W 0x0C 0 

18.3.1 

 

Table 18-3: 

(CCR, 0x4005 4000) 

 

0 CMP0_EN 0 0 

0 0 

1 0 

1 CMP1_EN 1 0 

0 1 

1 1 

2 CMPIL 0 

0 

1 

3 CMPIEV 0 

0 

1 

4 CMPBE 0 

0 

1 

5 CMP1_INTEN 1 0 

6 CMP0_INTEN 0 0 

7 CMPSA 

/ 0 

0 

1 

10:8 CMP0_VP_CTRL 0 000 

0x0 

 


XN62Lxxx 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

0x7 

ACMP0_I0 

ACMP0_I1 

ACMP0_I2 

ACMP0_I3 

ACMP1_I0 

ACMP1_I1 

DA 

13:11 CMP0_VM_CTRL 0 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

0x7 

 

ACMP0_I0 

ACMP0_I1 

ACMP0_I2 

ACMP0_I3 

ACMP1_I0 

ACMP1_I1 

DA 

16:14 CMP1_VP_CTRL 1 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

0x7 

 

ACMP1_I0 

ACMP1_I1 

ACMP1_I2 

ACMP1_I3 

ACMP0_I0 

ACMP0_I1 

DA 

19:17 CMP1_VM_CTRL 0 000 

0x0 

0x1 

0x2 

0x3 

0x4 

0x5 

0x6 

0x7 

 

ACMP1_I0 

ACMP1_I1 

ACMP1_I2 

ACMP1_I3 

ACMP0_I0 

ACMP0_I1 

DA 

21:20 - - NA 

22 CMP0_DMAEN - 0 DMA 0 

23 CMP1_DMAEN - 1 DMA 0 

24 CMP0_PO - 0 0 

25 CMP1_PO - 1 0 

27:26 - - NA 


XN62Lxxx 

28 CMP0_RLT - 0 0 

29 CMP1_RLT - 1 0 

31:30 - - . 0 

18.3.2 

 

V REF 32 V SS 1.8V/3.3 V 

Table 18-4: 

(VLAD, 0x4005 4004) 

 

0 VLADEN 0 

0 

1 

5:1 VSEL 

VLADREF 

6 d 

00000 = V SS 

00001 = 1 × VLADREF /31 

00010 = 2 × VLADREF /31 

... 

11111 = VLADREF 

6 VLADREF 0 

0 1.8v 

1 V DD(3V3) 

7 - - 0 

15:8 DIV 0 

0 

1~255 

31:16 - - NA 

0 

18.3.3 

Table 18-5: 

(INTSTA, 0x4005 400C) 

 

0 CMP0_INT 0 

1 0 

1 CMP1_INT 1 

1 0 

31:2 - NA 

18.4 

18.4.1 

 

8 

CMP 

0 

7 

DA 


XN62Lxxx 

 

6 

IO 

IO 

ACMP1_I4 ACMP1_I5 ACMP0_I0 

ACMP0_I1 

ACMP0_I4 ACMP0_I5 

ACMP1_I0 ACMP1_I1 

VDD(3V3) 

C0_IN0 

C0_IN1 

AN ALOGLOGIC 

C0_IN2 

C0_IN3 

32 

+ 

- 

C1_IN0 

C1_IN1 

6 

6 

6 

6 

+ 

- 

C1_IN2 

C1_IN4 

C1_IN5 

C1_IN3 

Output From DA 

Figure 18-2: 

18.4.2 

 

CPU CLINT 

18.4.3 

 

16 

• 

PCLK 

• 

 

16 

• 16 0 (CT16B0) 

– 3 0 


XN62Lxxx 

– 2 0 

• 16 1 (CT16B1) 

– 3 1 

– 2 1 

 

 


XN62Lxxx 

19 DMA 

19.1 

XN62L DMA AMBA AHB-Lite 

DMA DMA APB 

DMA 

 

SYSAHBCLKDIV DMA 

 

AHB 

12 

• AHB-Lite 32 

• 28 DMA 

• 

• 

DMA 

• 

• DMA 

DMA 

• DMA 

• 

• AHB-Lite 

DMA 

• 

• DMA 

1 1024 

• 

19.2 DMA 

DMA APB 

AHB AHB-Lite 

DMA 

DMA Controller 

configuration 

control 

APB BUS 

APB 

REGISTER 

INTERFACE 

requests 

DMA stall 

DMA 

CONTROL 

AHB-Lite 

MASTER 

INTERFACE 

APB BUS 

DMA data 

transfer 

mode 

active channel 

channel done 

error 

Figure 19-1: DMA 


XN62Lxxx 

DMA 816 32 

DMA 

 

32 DMA 

• 

• 

• 

• AHB-Lite 

• 

DMA • DMA 

• 

DMA • 

DMA – 

– 

– 

19.3 DMA 

DMA 

SRAM 

DMA 

19.4 DMA 

DMA 

DMA Table 19-1: DMA 

DMA DMA 

DMA 

UART0 TX 0 

UART0 RX 1 

UART1 TX 2 

UART1 RX 3 

SPI TX 4 

SPI RX 5 

ADC 0 6 

RTC 7 

32 0 0 8 

32 0 1 9 

32 1 0 10 

32 1 1 11 


XN62Lxxx 

16 0 0 12 

16 1 0 13 

0 14 

1 15 

PIO 0 16 

PIO 1 17 

PIO 2 18 

DAC 19 

xDSP0 20 

xDSP1 21 

ADC1 22 

ADC2 23 

UART2 TX 24 

UART2 RX 25 

UART3 TX 26 

UART3 RX 27 

19.5 DMA 

Table 19-2: 

: DMA ( 0x4004 C000) 

 

DMA_STATUS RO 0x000 DMA - 

DMA_CFG WO 0x004 DMA - 

CTRL_BASE_PTR R/W 0x008 

0x0000 0000 

- - 0x00C-0x010 - 

CHNL_SW_REQUEST WO 0x014 - 

CHNL_USEBURST_SET R/W 0x018 0x0000 0000 

CHNL_USEBURST_CLR WO 0x01C - 

CHNL_REQ_MASK_SET R/W 0x020 0x0000 0000 

CHNL_REQ_MASK_CLR WO 0x024 - 

CHNL_ENABLE_SET R/W 0x028 0x0000 0000 

CHNL_ENABLE_CLR WO 0x02C - 

- - 0x030-0x034 - 

CHNL_PRIORITY_SET R/W 0x038 

0x0000 0000 

CHNL_PRIORITY_CLR WO 0x03C 

- 

- - 0x040 - 0x07C - 

CHNL_IRQ_STATUS R/W 0x080 DMA 

0x0000 0000 

- - 0x084 - 

CHNL_IRQ_ENABLE R/W 0x088 DMA 

0x0000 0000 


XN62Lxxx 

19.5.1 DMA 

 


(DMA_STATUS, 0x4004 C000) 

 

0 MASTER_EN 

0 

0 = 

1 = 

3:1 - . 0 

7:4 STATE 

0 

0000 = 

0001 = 

0010 = 

0011 = 

0100 = 

0101 = 

0110 = DMA 

0111 = 

1000 = 

1001 = 

1010 =- 

1011-1111 = 

5:31 - . NA 

19.5.2 DMA 

 


(DMA_CFG, 0x4004 C004) 

 

0 MASTER_EN DMA 0 

0 DMA 

1 DMA 

31:1 - - . NA 

19.5.3 

/ 

 

SRAM DMA 

 

Table 19-5: 

(CTRL_BASE_PTR, 0x4004 C008) 


XN62Lxxx 

 

31:0 CTRL_BASE_PTR DMA 0x0 

19.5.4 

c -27) DMA DMA 

(c = 0 

 

Table 19-6: 

(CHNL_SW_REQUEST, 0x4004 C014) 

 

27:0 DMA_SW_ REQUEST 

DMA : 

0 

[c] = 0: 

[c] = 1: 

c DMA 

31:28 - . NA 

19.5.5 

/ 

 

c (c = 0-27) DMA (dma_sreq[c]) 

dma_req[c] 

Table 19-7: 

(CHNL_USEBURST_SET, 0x4004 C018) 

 

27:0 DMA_USEBURST_ 

SET 

c (c = 0-27) 

dma_sreq[c] DMA 0x0 

 

[c] = 0DMA c dma_req[c] dma_sreq[c] 

2 R 

[c] = 1DMA c 

dma_sreq[c] 

dma_req[c] 2 R 

 

[c] = 0 

CHNL_USEBURST_CLR [c] 

0 

[c] = 1 dma_sreq[C] DMA 

2 R 31:28 - . NA 

19.5.6 

 

c DMA c -27dma_sreq[c] 

= 0 

Table 19-8: 

(CHNL_USEBURST_CLR, 0x4004 C01C) 

 

27:0 CHNL_USEBURST_ CLR 

dma_sreq[c] 

- 

 

[c] = 0 

chnl_useburst_set dma_sreq[c] 


XN62Lxxx 

 

[c] = 1 dma_sreq[c] DMA 

31:28 - . NA 

19.5.7 

/ 

 

c (c = 0-27) DMA dma_req[c] DMA (dma_sreqc[c]) 

 

dma_req[c]dma_sreq[c] 

Table 19-9: 

(CHNL_REQ_MASK_SET, 0x4004 C020) 

 

27:0 CHNL_REQ_ MASK_SET dma_req[c] dma_sreq[c] 

0x0 

DMA 

 

[c] = 0 c 

[c] = 1 c 

 

[c] = 0 CHNL_REQ_MASK_CLR DMA 

[c] = 1 dma_req[c] dma_sreq[c] DMA 

31:28 - . NA 

19.5.8 

 

c (c = 0-27) dma_req[c] dma_sreq[c] 

Table 19-10: Channel Request Mask Clear (CHNL_REQ_MASK_CLR, 0x4004 C024) 

 

27:0 CHNL_REQ_ MASK_CLR 

dma_req[c] dma_sreq[c] - 

DMA 

 

[c] = 0 

chnl_req_mask_set dma_req[c] 

dma_sreq[c] 

[c] = 1 dma_req[c] dma_sreq[c] DMA 

31:28 - . NA 

19.6 

/ 

 

DMA c (c = 0-27) 

Table 19-11: 

(CHNL_ENABLE_SET, 0x4004 C028) 

 


XN62Lxxx 

27:0 CHNL_ENABLE_ SET 0x0 

 

[c] = 0 c 

[c] = 1 c 

 

[c] = 0 

CHNL_ENABLE_CLR 

[c] = 1 c 

31:28 . - 

19.6.1 

 

 

DMA 

• DMA 

• cycle_ctrl = 000 channel_cfg 

• AHB-Lite 

Table 19-12: 

(CHNL_ENABLE_CLR, 0x4004 C02C) 

 

27:0 CHNL_ENABLE_ CLR 

DMA 

- 

 

[c] = 0 

CHNL_ENABLE_SET DMA 

[c] = 1 

c 

31:24 - . NA 

19.6.2 

/ 

 

DMA c (c = 0-27) 

Table 19-13: 

(CHNL_PRIORITY_SET, 0x4004 C038) 

 

27:0 CHNL_PRIORITY_SET 

0x0 

 

[c] = 0DMA c 

[c] = 1DMA c 

 

[c] = 0 

CHNL_PRIORITY_CLR 

c 

[c] = 1 c 

31:28 - . NA 

19.6.3 

 

DMA c (c = 0-27) 


XN62Lxxx 

Table 19-14: 

(CHNL_PRIORITY_CLR, 0x4004 C03C) 

 

27:0 CHNL_PRIORITY_CLR 

DMA - 

 

[c] = 0 

CHNL_PRIORITY_SET 

c 

[c] = 1 c 

31:28 - . NA 

19.6.4 DMA 

/ 

 

DMA c (c = 0-27) DMA “1” 


(CHNL_IRQ_STATUS, 0x4004 C080) 

Reset 

27:0 CHNL_IRQ_STAT 

DMA 

0x0 

 

[c] = 0DMA 

[c] = 1 c DMA 

 

[c] = 0 

[c] = 1 c DMA 

31:28 - . NA 

19.6.5 DMA 

/ 

 

DMA c (c = 0-27) DMA 


(CHNL_IRQ_ENABLE, 0x4004 C088) 

 

27:0 CHNL_IRQ_ENABLE DMA (dma_done[c]) 

0x0 

 

[c] = 0 c DMA 

[c] = 1 c DMA 

31:28 - . NA 

19.7 

19.7.1 DMA 

 

DMA 

DMA www.xinnovatech.com 273

XN62Lxxx 


/ 

 

DMA dma_req[c] 

 

/ 

 

 

dma_req[c] 2 R DMA DMA 

R_power 

 

c dma_req[c] 

 

DMA 

dma_sreq[c] 

/ 

 

dma_sreq 

 

DMA DMA 

c dma_sreq[c] 

 

19.7.2 DMA 

 

DMA 

 

AHB R_power R 2 

R = 4 

24 

16 DMA 

 

R_power 

N > 2 R 

2 R 

2 R 

N

XN62Lxxx 

... ... 

27 

19.7.4 DMA 

 

cycle_ctrl DMA 

 

• 

• 

• 

 

2 R DMA 

2 R DMA 

DMA 

channel_cfg 

R_power 

 

 

DMA DMA 

 

 

1. 2 R 

0 

3 2. 

a) 

b) 

1 3. 

dma_done[c] 

DMA 

 

1. 2 R 

0 

3 2. 2 R 

c 1 3. 

dma_done[c] 

DMA 19.7.5 DMA 

SRAM 

DMA DMA 

SRAM 


XN62Lxxx 

1024 

28 28 

 

SRAM 

0x1000 0000 0x1000 3F00 

CTRL_BASE_PTR 

DMA (SRAM) 

1GB 

alternate channel 20 

. 

. 

. 



primary channel 20 

. 

. 

. 



0x2A0 

0x2B0 

0x170 

0x160 

0x150 

0x140 

0x020 

0x010 

0x000 

unused 

channel control data 

destination end pointer 

source end pointer 

0x00C 

0x008 

0x004 

0x000 

Figure 19-2: DMA 

19.7.5.1 

src_data_end_ptr 

DMA 

2 R DMA 

DMA 

 

 

Table 19-19: src_data_end_ptr 

 

31:0 src_data_end_ptr 

19.7.5.2 

dst_data_end_ptr 

DMA 

2 

R DMA 

 

 

Table 19-20: dst_data_end_ptr 

 

31:0 dst_data_end_ptr 


XN62Lxxx 

19.7.5.3 

DMA channel_cfg DMA 

2 

 

SRAM channel_cfg 

 

2 R N 

channel_cfg SRAM 

src_size 

dst_size 

n_minus_1 dst_size 

src_size N 

cycle_ctrl 

000 channel_cfg SRAM 

 

R 

SRAM 

. 

Table 19-21: channel_cfg 

Name 

2:0 cycle_ctrl DMA 

3 

000: 

001: / 

DMA 100 - 111 

13:4 n_minus_1 DMA 

DMA DMA 

DMA 

10 DMA 

000000000 = 1 DMA 

000000001 = 2 DMA 

000000010 = 3 DMA 

000000011 = 4 DMA 

000000100 = 5 DMA 

... 

111111111 = 1024 DMA 

 

DMA DMA 

17:14 R_power 

DMA 

0000: DMA 

0001: 2 DMA 

0010: 4 DMA 

0011: 8 DMA 

0100: 16 DMA 

0101: 32 DMA 

0110: 64 DMA 

0111: 128 DMA 

1000: 256 DMA 

1001: 512 DMA 


XN62Lxxx 

23:18 - - 

1010-1111: 1024 DMA 

DMA 

1024 

25:24 src_size 

00 = 

01 = 

10 = 

11 = 

27:26 src_inc 

= 

00 = . 

01 = . 

10 = . 

11 = 


= 

00 = . 

01 = . 

10 = . 

11 = 


= 

00 = . 

01 = . 

10 = . 

11 = 


29:28 dst_size 

00 = 

01 = 

10 = 

11 = 

31:30 dst_inc 

 

= 

00 = . 

01 = . 

10 = . 

11 = 


= 

00 = . 

01 = . 

10 = . 

11 = 


= 


XN62Lxxx 

00 = . 

01 = . 

10 = . 

11 = 



XN62Lxxx 

20 Flash/SRAM ISP/IAP 

XN62 88 KB Flash 16 KB SRAM 

Flash 

(ISP) 

(IAP) 

 

XN62L bootloader ISP/IAP XN62L 128 

A/B 

20.1 Flash/Boot ROM 

XN62L Flash 1K 

88 Flash 

0 

ROM 8KB 

MCU bootloaderboot loader 0x1FFF0000 

Reserved 

0x1FFF 2000 

0x1FFF 0000 

Boot Loader 

Reserved 

0x0001 6000 

0x0001 5FFF 

0x0001 5C00 

Sector 87 

User App. 

0x0000 0800 

0x0000 0400 

0x0000 0000 

Sector 1 

Sector 0 

Figure 20-1: 

Flash 

XN62L (MAM 

) 64 Flash IPFlash 

 


XN62Lxxx 

Flash Control 

Address 

Address 

M0 Core 

32bits Data Bus 

MAM 

64bits Data Bus 

On Chip Flash 

Rdy/Bsy 

Figure 20-2: 

(MAM) 20.2 Flash / 


(: 0x5006 0000) 

· 

~ 0x00~0x24 ~ 

FLASH_RDCYC 0x28 R/W Flash 0x0000 0000 

DID 0x2C RO ID 

0xxxxx xxxx 

VERID 0x30 RO 0xxxxx xxxx 

UNIQUEID 0x34 RO 0xxxxx xxxx 

20.2.1 Flash 

Flash 

FLASH_RDCYC 


(FLASH_RDCYC, 0x5006 0028) 

 

1:0 CYCLES Flash 00 

00 1 

system clock 30MHz 

01 2 


10 3 

system clock 60MHz 90MHz 

 

11 4 


31:2 - - - 0x0 

20.2.2 ID 

Table 20-3: ID (DID, 0x5006 002C) 

 

15:0 DID ID 

31:16 MID 

ID 

XXXX 

XXXX 


XN62Lxxx 

20.2.3 

Table 20-4: 

(VERID, 0x5006 0030) 

 

15:0 MINOR XXXX 

31:16 MAJOR XXXX 

20.2.4 

Table 20-5: 

(UNIQUEID, 0x5006 0034) 

 

31:0 SID XXXXXXXX 

20.3 Flash 

XN62L 128 

Flash Fl 

SRAM 

0x0001 5FFF 

Flash Memory(88KB) 

0x10003000 

SRAM(16KB) 

Access Control by 

B Area 

B Area 

Password B (128 bits) 

0x000x xxxx 

0x1000 xxxx 

Open Area 

A Area 

0x1000 0000 

Password A (128 bits) 

0x0000 0000 

Figure 20-3: / 

Figure 20-3 128 

SWD 

A B 

1. B 

A/B/ 

B SRAM 

2. A 

B 

B 3. A 

A 

4. Flash 

 

5. SWD 


XN62Lxxx 

20.3.1 A/B 

 

Flash SRAM A,B 

A,B 

Flash A 

A 

Flash/SRAM B 

ISP/IAP B 

 

ISP/IAP : SRAM 2K Flash 

 

20.3.2 

/ 

() 

20.3.3 

Table 20-6: A 

 

 

 

B/A/ 

ISP A SWD A 

DMA A 

 

 

 

Flash / B/A/ 

ISP A 

SRAM 

 

SWD A 

A 

 

 

Table 20-7: B 

 

 

 

B 

B A 

B SWD B 

ISP B 

DMA B 

 

 

 

 

 

Flash / B/A/ 

ISP B 

SRAM 

 

B 

B SRAM 

SWD B 

DMA B SRAM 

B 

 

 

 

 

20.4 ISP 

ISP 

XN MCU UART0 . 

• UART 1 

, 8, , 1 

ISP 

: 


XN62Lxxx 

 

(2 0x55AA) 

 

 

( ) CRC16 

(1 ) (1 ) (1 ) (1 ) (2 ) 

: 

( ) CRC16 

Figure 20-4: ISP 

• : , 

: 0x55AA 

• : 

CRC 

• : - ; 1 - . 0 

• : . 

• : 

0, 

0 

• : . 

• / : . 

• CRC: 2 CRC16(:0xFFFF) . 

20.4.1 ISP 

ISP : 

ISP 

4 

4 

• 

#01H 

• #03H 

• #04H 

Table 20-8: ISP 

 

 

#01H #11H 2 8 No 

#02H #12H 2 8 No 

SRAM #04H #14H 2 8 Yes 

SRAM Flash #05H #15H 3 12 No 

#06H #16H 3 12 No 

#07H #17H 2 8 No 

#08H #18H 0 0 No 

 

ID #01H #31H 0 0 No 

Bootloader #02H #32H 0 0 No 

 

 

#02H #42H 0 0 No 

#0AH #4AH 1 16 No 

#0BH #4BH 2 32 No 

B #0CH #4CH 2 20 No 

20.4.2 ISP 

ISP ISP 

 


XN62Lxxx 

: #08H 

: #09H 

: #0AH 

: #0BH 


 

 

#11H #11H 0 0 No 

#12H #12H 0 0 No 

SRAM #14H #14H 0 0 No 

 

SRAM Flash #15H #15H 0 0 No 

#16H #16H 0 0 No 

#17H #17H No 

#18H #18H 0 0 No 

 

ID #31H #31H 3 12 No 

Bootloader #32H #32H 2 8 No 

#42H #42H 0 0 No 

#4AH #4AH 0 0 No 

#4BH #4BH 0 0 No 

B #4CH #4CH 0 0 No 


 

 

#01H #81H 0 0 No 

#02H #82H 0 0 No 

#03H #83H 0 0 No 

CRC #04H #84H 0 0 No 

#01H #91H 0 0 No 

Flash #02H #92H 0 0 No 

Flash #03H #93H 1 4 No 

1 #01H #A1H 0 0 No 

2 #02H #A2H 0 0 No 

3 #03H #A3H 0 0 No 

#01H #B1H 0 0 No 

20.4.3 

: 0x11H 

: 


XN62Lxxx 

 

 

– : 0~ Flash flash 

– : 

 

~ flash 

: 0x11H 

: 

 

20.4.4 

: 0x12H 

: 

 

– : Flash 0 ~ Flash 

– : ~ 

Flash 

: 0x12H 

: 

 

20.4.5 SRAM 

1.: 0x14H 

: 

 

– : SRAM =0x10 000400 

– : 0~1024 

2.MCU : 

0x14H xFF 

3. 

 

4.MCU : 

0x14Hx00 

20.4.6 RAM Flash 

: 0x15H 

: 

Flash (32 ) SRAM (32 ) (32 ) 

– Flash : Flash 

– SRAM : SRAM =0x10000400 

– : Flash 


XN62Lxxx 

: 0x15H 

: 

 

20.4.7 

: 0x16H 

: 

(32 ) (32 ) (32 

) 

– 

– 

– 

: 0x16H 

: 

 

20.4.8 

: 0x17H 

: 

(32 ) (32 

) 

– : 

– : 

: 0x17H 

: 

 

– : MCU 

20.4.9 

: 0x18H 

: 0x18H 

 

20.4.10 ID 

: 0x31H 

: 0x31H 

: 


XN62Lxxx 

ID(32 ) (32 s) (32 

) Flash (32 ) SRAM (32 ) 

– ID: 16 ID + 16 ID 

– : 

– .: 32 

– Flash : 

– SRAM : 

20.4.11 BSL 

: 0x32H 

: 0x32H 

(16 ) (16 ) (32 ) 

: 1~255 

:1~255 

: 

20.4.12 

: 0x42H 

 

– : Flash RAM 

– : 0: Flash; loader 1: Boot 

: 0x42H 

20.4.13 

: 0x4AH 

: 

AB (32 ) (128 ) 

– AB 0: A; 1: B. 

– : 

128 

: 0x4AH 

: 

AB (32 ) 

20.4.14 

: 0x4BH 


XN62Lxxx 

: 

AB (32 ) (128 ) (128 ) 

– AB 0: A; 1: B. 

– : 128 

– : 128 

: 0x4BH 

: 

AB (32 ) 

20.4.15 B 

: 0x4CH 

: 

AB (32 ) 128 Flash (32 ) SRAM (32 ) 

– AB : 1 

– : 

128 

– Flash : 

32 

– SRAM : 

32 

: 0x4CH 

: 

AB (32 ) 

20.4.16 

: 0x4DH 

: 0x4DH 

: 

A (32 ) B (32 ) B Flash (32 ) B SRAM (32 ) 

– A 0: ; 0: 

– B 0: ; 0: 

– Flash : 

32 

– SRAM : 

32 

20.5 IAP 

BSL IAP Thumb 

0x1FFF 1FF0 

r0 

IAP (RAM) 

IAP r1 www.xinnovatech.com 289

XN62Lxxx 

 

r0 r1 

 

IAP COMMAND CODE 

PARAMETER 1 

command 

parameter table 

PARAMETER 2 

ARM REGISTER r0 

ARM REGISTER r1 

PARAMETER n 

STATUS CODE 

RESULT 1 

command 

result table 

RESULT 2 

RESULT n 

Figure 20-5: IAP 

 

C IAP 

IAP 

IAP 0 

Thumb 

 

#define IAP_LOCATION 0x1fff1001 

 

IAP 

IAP : 

unsigned long command[10]; 

unsigned long result[5]; 

 

unsigned long * command; 

unsigned long * result; 

command=(unsigned long *) 0x…… 

result= (unsigned long *) 0x…… 

 

2 

IAP R1 

typedef void (*IAP)(unsigned int [],unsigned int[]); 

IAP iap_entry; 

 

iap_entry=(IAP) IAP_LOCATION; 


XN62Lxxx 

 

IAP 

iap_entry (command, result); 

Table 20-11: IAP 

IAP 

R0 

R1 

 

1 2 3~6 5~9 

 

1 2 3 4 

BSL 0x31 - - - - Major& 

- - 

Minor 

0x11 

- - - - - - - 

0x15 - - - - - - 

0x4A A/B 128 - - - - - 

0x4B A/B 128 128 - - - - 

B 0x4C A/B 128 B Flash SRAM 

- - 

 

 

0x4D 

 

A B B Flash 

B SRAM 

 

 

 

 

IAP : 

1. CMD_SUCC 0x00 

2. INVALID_ADDR 0x01 

3. ERASE_FAILED 0x02 

4. PROG_FAILED 0x03 

5. NOT_BLANK 0x04 

6. INVALID_CMD 0x05 

7. INVALID_PWD 0x06 

8. IRC_NOT_POWERED 0x07 


XN62Lxxx 

21 SWD 

21.1 

XN62L SWD 

ARM Serial Wire Debug mode 

• 

• 

• 4 4 

2 • 2 

21.2 

Table 21-1: SWD 

 

SWCLK (SW 

SWDIO 

/ 

 

/ 

SWDIO ARM Cortex-M0 CPU 

 

21.3 

SWD 

SWD SWD 

SWD A 

SWD 

SWD 

XN62Lxxx 

signals from SWD connector 

SWDIO 

SWCLK 

nSRST 

GND 

Gnd 

SWDIO 

SWCLK 

RESET# 

PIO0_12 

ISP entry 

Figure 21-1: SWD SWD 


XN62Lxxx 

22 

 

1.0 Initial Release. May 2012 

1.1 Revised ADC, ISP/IAP sections. Aug. 2012 

1.2 Document Revision Apr. 2013 

1.3 Revised power down wakeup May 2013

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