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XN62Lxxx QFP64 QFP48 CT32B1_MAT1/ PWM0_5/ PWM1_3/ QSPI_DO PIO0_8/ RXD1/ CT32B1_CAP2/ CT32B1_MAT2/ PWM0_6 PIO0_9/ TXD1/ CT32B1_CAP3/ CT32B1_MAT3/ PWM0_7 PIO0_10/ SCL PIO0_11/ SDA/ CT16B0_CAP0/ CT16B0_MAT0 PIO0_12/ CLKOUT/ CT16B0_CAP1/ CT16B0_MAT1 PWM1_6 RESET/ PIO0_13/ WAKEUP PIO0_14/ SCK/ CLKOUT/ TXD2 PIO0_15/ SSEL/ CT16B1_CAP0/ CT16B1_MAT0/ RXD2 - O - CT32B1_MAT1 —32 1 1 - O - PWM0_5 — PWM 0 , 5 - O - PWM1_3 — PWM 1 , 3 - I/O - QSPI_DO —QSPI IO1 27 23 yes I/O I; PU PIO0_8 — / - I - RXD1 —UART1 - I - CT32B1_CAP2 —32 1 2 - O - CT32B1_MAT2 —32 1 2 - O - PWM0_6 — PWM 0 , 6 28 24 yes I/O I; PU PIO0_9 — / - O - TXD1 —UART1 - I - CT32B1_CAP3 —32 1 3 - O - CT32B1_MAT3 —32 1 3 - O - PWM0_7 — PWM 0 , 7 37 25 yes I/O I; IA PIO0_10 — / - I/O - SCL —TWS / 38 26 yes I/O I; IA PIO0_11 — / - I/O - SDA —TWS / - I - CT16B0_CAP0 —16 0 0 - O - CT16B0_MAT0 —16 0 0 39 27 - I/O I; PU PIO0_12 — / - O - CLKOUT — - I - CT16B0_CAP1 —16 0 1 - O - CT16B0_MAT1 —16 0 1 - O - PWM1_6 — PWM 1 , 6 40 28 - I I; PU RESET — - I/O - PIO0_13 — / - I - WAKEUP — 41 29 - I/O I; PU PIO0_14 — / - I/O - SCK —SPI - O - CLKOUT — - O - TXD2 —UART2 42 30 - I/O I; PU PIO0_15 — / - I/O - SSEL — SPI - I - CT16B1_CAP0 —16 1 0 - O - CT16B1_MAT0 —16 1 0 - I - RXD2 —UART2 PIO0_16/ 43 31 - I/O I; PU PIO0_16 — / 8 www.xinnovatech.com
XN62Lxxx QFP64 QFP48 MISO/ CT16B1_CAP1/ CT16B1_MAT1/ TXD3 PIO0_17/ MOSI/ RXD3 PIO0_18/ SWCLK/ CT32B0_CAP0/ CT32B0_MAT0 PIO0_19/ ACMP0_I0/ CT32B0_CAP1/ CT32B0_MAT1 PIO0_20/ ACMP0_I1/ CT32B0_CAP2/ CT32B0_MAT2 PIO0_21/ ACMP0_I2/ CT32B0_CAP3/ CT32B0_MAT3 PIO0_22/ ACMP0_I3 PIO0_23/ ACMP1_I0/ CT32B1_CAP0/ CT32B1_MAT0 PIO0_24/ ACMP1_I1/ CT32B1_CAP1/ CT32B1_MAT1 SWDIO/ ACMP1_I2/ CT32B1_CAP2/ CT32B1_MAT2/ PIO0_25 - I/O - MISO — SPI - I - CT16B1_CAP1 —16 1 1 - O - CT16B1_MAT1 —16 1 1 - O - TXD3 —UART3 44 32 - I/O I; PU PIO0_17 — / - I/O - MOSI —SPI - I - RXD3 —UART3 45 33 - I/O I; PU PIO0_18 — / - I - SWCLK — SWD - I - CT32B0_CAP0 —32 0 0 - O - CT32B0_MAT0 —32 0 0 4 4 - I/O I; PU PIO0_19 — / - I - ACMP0_I0 — 0 0 - I - CT32B0_CAP1 —32 0 1 - O - CT32B0_MAT1 —32 0 1 5 5 - I/O I; PU PIO0_20 — / - I - ACMP0_I1 — 0 1 - I - CT32B0_CAP2 —32 0 2 - O - CT32B0_MAT2 —32 0 2 6 6 - I/O I; PU PIO0_21 — / - I - ACMP0_I2 — 0 2 - I - CT32B0_CAP3 —32 0 3 - O - CT32B0_MAT3 —32 0 3 7 7 - I/O I; PU PIO0_22 — / - I - ACMP0_I3 — 0 3 8 8 - I/O I; PU PIO0_23 — / - I - ACMP1_I0 — 1 0 - I - CT32B1_CAP0 —32 1 0 - O - CT32B1_MAT0 —32 1 0 9 9 - I/O I; PU PIO0_24 — / - I - ACMP1_I1 — 1 1 - I - CT32B1_CAP1 —32 1 1 - O - CT32B1_MAT1 —32 1 1 10 10 - I/O I; PU SWDIO —SWD - I - ACMP1_I2 — 1 2 - I - CT32B1_CAP2 —32 1 2 - O - CT32B1_MAT2 —32 1 2 - I/O - PIO0_25 — / www.xinnovatech.com 9
Page 1 and 2: XN62Lxxx 32 IC ARM + xDSP , 88K
Page 3 and 4: XN62Lxxx 2 . Flash (bytes) SRAM
Page 5 and 6: XN62Lxxx www.xinnovatech.com 5 3.2
Page 7: XN62Lxxx 3.4 Table 3-1: QFP64 QF
Page 11 and 12: XN62Lxxx QFP64 QFP48 PWM1_5
Page 13 and 14: XN62Lxxx QFP64 QFP48 PIO2_1
Page 15 and 16: XN62Lxxx CT16B1_MAT1 O PIO0_16 PIO1
Page 17 and 18: XN62Lxxx 5 5.1 ARM Cortex-M0 Cort
Page 19 and 20: XN62Lxxx Private peripheral Reserve
Page 21 and 22: XN62Lxxx 0xE000E000 ~ 0xE000E0FF 0x
Page 23 and 24: XN62Lxxx 17:12 VECTPENDING RO : 2
Page 25 and 26: XN62Lxxx Table 5-7: (CCR, 0xE000-ED
Page 27 and 28: XN62Lxxx 0~3 33 17 0x84 SPI (2) T
Page 29 and 30: XN62Lxxx 31:0 SETPEND IRQ0~IRQ31 .
Page 31 and 32: XN62Lxxx 28 PWM1 29 DMA 30 RTC 31 D
Page 33 and 34: XN62Lxxx • • • • Table
Page 35 and 36: XN62Lxxx RESET#Schmitt trigger 15
Page 37 and 38: XN62Lxxx 5 - - 0x0 6 BODINTCLR -
Page 39 and 40: XN62Lxxx 31:9 - - 0x0 5.6.2.4 20
Page 41 and 42: XN62Lxxx 12MHz 50MHz 6 100 01 () 2
Page 43 and 44: XN62Lxxx 7:0 DIV AHB 0 0x01 1: 1.
Page 45 and 46: XN62Lxxx 1 25 ADC2 ADC2 1 0 1 2
Page 47 and 48: XN62Lxxx 0x01 0x03 ~ 0xFF 1 3 ~
Page 49 and 50: XN62Lxxx 5.6.3.3 RTC RTC 32 1 kHz
Page 51 and 52: XN62Lxxx 1 31:16 - - 0 5.6.3.6 P
Page 53 and 54: XN62Lxxx 1. PCON DPDEN 0 2. ARM
Page 55 and 56: XN62Lxxx RTC XN62L • WAKEUP XN
Page 57 and 58: XN62Lxxx 3 ERPIO0_3 PIO0_3 0 0 =
Page 59 and 60:
XN62Lxxx 0 SRPIO0_0 PIO0_0 0 0 = 1
Page 61 and 62:
XN62Lxxx 1 DMA 11 PWM0_RST_N PWM0
Page 63 and 64:
XN62Lxxx 0x3 3 3 15:13 CLK_DIV
Page 65 and 66:
XN62Lxxx PIO0_7 R/W 0x064 PIO0_7/C
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XN62Lxxx 5.7.2.2 PIO0_1 IOCON Tabl
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XN62Lxxx 5.7.2.4 PIO0_3 IOCON Tabl
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XN62Lxxx 0x5 0x6 IOCONFIGCLKDIV5. I
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XN62Lxxx 0x4 0x5 0x6 IOCONFIGCLKDIV
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XN62Lxxx 0x1 0x2 0x3 0x4 0x5 0x6 IO
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XN62Lxxx 2:0 FUNC . 000 0x0 0x1 0x
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XN62Lxxx 6 INV 0 0 . 1 . 7 - . 1
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XN62Lxxx 1 . 5 - . 0 6 INV 0 0 . 1
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XN62Lxxx 0 . 1 . 5 - . 0 6 INV 0 0
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XN62Lxxx 0 . 1 . 5 - . 0 6 INV 0 0
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XN62Lxxx 0x3 0x4 0x5 CT32B0_CAP3.
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XN62Lxxx 2:0 FUNC . 000 0x0 0
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XN62Lxxx 0x6 IOCONFIGCLKDIV6. 31:16
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XN62Lxxx 0x3 3 3 15:13 CLK_DIV
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XN62Lxxx 0x0 0x1 0x2 0x3 1 1 2
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XN62Lxxx 1 12:11 S_MODE 00 0x0 0x
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XN62Lxxx 1 . 10 OD 0 0 1 12:11
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XN62Lxxx 8 - . 0 9 DRV . 0 0 1 .
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XN62Lxxx 1 8 - . 0 9 DRV . 0 0 1
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XN62Lxxx 1 . 7 - . 1 8 - . 0 9 DRV
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XN62Lxxx 5 - . 0 6 INV 0 0 . 1 .
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XN62Lxxx 4 MODE (). 1 0 . 1 . 5 -
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XN62Lxxx 0x5 PWM1_5. 3 - 0 4 MODE
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XN62Lxxx 0x2 0x3 0x4 0x5 0x6 CT32B
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XN62Lxxx 5.7.2.19 PIO2_9 IOCON Tab
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XN62Lxxx 0x3 0x4 0x5 0x6 IOCONFIGCL
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XN62Lxxx 0x1 0x2 0x3 0x4 0x5 0x6 IO
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XN62Lxxx 0x2 0x3 0x4 0x5 0x6 IOCONF
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XN62Lxxx 6 PWM 6.1 XN62L 3 PWM0P
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XN62Lxxx 6.2 PWM Table 6-1: PWM
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XN62Lxxx 6.3.1 PWM Table 6-3 PWM (
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XN62Lxxx 26 CH2OUTEN 2 0 0 1 27
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XN62Lxxx PWM 4 FTACK4 1 FFLAG40
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XN62Lxxx 4 OUT4 PWMn_4 0 0 0 1 1
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XN62Lxxx Table 6-11: PWM (DMAP1) 1
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XN62Lxxx 0 1 12 TOPNEG67 PWMn 6
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XN62Lxxx 1 1 12 FAULTVAL4 PWM FPS
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XN62Lxxx Match 0 PWMn_0 0PWMn_1
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XN62Lxxx 0 CNTR VAL5 1 CNTR VAL
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XN62Lxxx 4 3 2 Up Counter Modulus =
Page 147 and 148:
XN62Lxxx PWM 0 PWM 2 PWM 4 AC Input
Page 149 and 150:
XN62Lxxx Desired Load Voltage Deadt
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XN62Lxxx 4 3 2 Up/Down Counter Modu
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XN62Lxxx Up/Down Counter Reload Cha
Page 155 and 156:
XN62Lxxx LDFQ[3:0] = 0000 = Reload
Page 157 and 158:
XN62Lxxx Table 6-23: PWM PWMn_0 P
Page 159 and 160:
XN62Lxxx 7 GPIO 7.1 XN62L 55 GPIO
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XN62Lxxx 7.3.3 GPIO 0 1 GPIO GP
Page 163 and 164:
XN62Lxxx 1 . 7.3.11 GPIO lE Tab
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XN62Lxxx CAPTURE REGISTER 3 CAPTURE
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XN62Lxxx - - 0x040 - 0x06C - CTCR
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XN62Lxxx 0 5 MR1S MR1 TC TC PC T
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XN62Lxxx 0 10 CAP3FE 1 1 1 0 CR
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XN62Lxxx PCLK CAP CAP PCLK CAP
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XN62Lxxx 8.3.11.3 Primary Second
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XN62Lxxx CAPTURE REGISTER 3 CAPTURE
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XN62Lxxx 2 MR2INT 2 0 3 MR3INT 3
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XN62Lxxx 0 8 MR2S MR2 TC TC PC T
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XN62Lxxx 9.3.9 Table 9-11: (CR0
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XN62Lxxx 2:0 CTM / PCLK 00 (PC) P
Page 187 and 188:
XN62Lxxx 10 (WDT) 10.1 • •
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XN62Lxxx 1 WARNINT WINDOW (WDTC)
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XN62Lxxx 0x1 WDT 0x2 0x3 . . 30:
Page 193 and 194:
XN62Lxxx WDCLK / 4 Watchdog Counter
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XN62Lxxx FILTER_CR R/W 0x280 0x000
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XN62Lxxx 11.2.9 CORDIC X Table 11-
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XN62Lxxx 15:0 FILTER_RESULT . 0 16
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XN62Lxxx 2. CORDIC_X, CORDIC_Y COR
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XN62Lxxx 5. www.xinnovatech.com 20
Page 205 and 206:
XN62Lxxx 12.2 Table 12-1: UART0,1
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XN62Lxxx 1 THR . 3 RBRIE RBR 0
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XN62Lxxx 12.4.2 IrDA UART IRDAEN
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XN62Lxxx CR0 R/W 0x000 0 0x0
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XN62Lxxx 15:0 DATA TNF 1 Tx FIFO
Page 215 and 216:
XN62Lxxx 13.3.9 SPI 1 SPI FIFO
Page 217 and 218:
XN62Lxxx Figure 13-2: SPI CPOL = 0
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XN62Lxxx CLK FS DX/DR MSB LSB 4 to
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XN62Lxxx IMSC R/W 0x014 RIS RO 0x
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XN62Lxxx 14.3.6 4 Table 14-8: (I
Page 225 and 226:
XN62Lxxx CLK CS DI MSB LSB DO Q MSB
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XN62Lxxx www.xinnovatech.com 227
Page 229 and 230:
XN62Lxxx 15.3 Table 15-2: ( 0x400
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XN62Lxxx TWSEN: TWS • TWS EN 1
Page 233 and 234:
XN62Lxxx Table 15-11: TWS (MASK0 -
Page 235 and 236:
XN62Lxxx S SLAVE ADDRESS RW=1 A DAT
Page 237 and 238:
XN62Lxxx reception of the own Slave
Page 239 and 240:
XN62Lxxx 15.4.6 TWS Table 15-14:
Page 241 and 242:
XN62Lxxx STA TXRX STO SI AA 0x4a S
Page 243 and 244:
XN62Lxxx 15.4.7.6 : 0x0b 0x01 AC
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XN62Lxxx 1. CONCLR 0x08 SI 2. 3.
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XN62Lxxx 16 RTC 16.1 1 Hz/1KHz RT
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XN62Lxxx 16.3.7 RTC Table 16-9: RT
Page 251 and 252:
XN62Lxxx 17.2 Table 17-1: ADC
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XN62Lxxx 11:0 RESULT DONE 1 SELNO
Page 255 and 256:
XN62Lxxx 31 DONE A/D 1 0 17.3.6 AD
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XN62Lxxx 9 DACCLR 0 1 0 0 10 DA
Page 259 and 260:
XN62Lxxx Temperature Slope(°C LSB
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XN62Lxxx ACMP0_O 0 ACMP1_O 1
Page 263 and 264:
XN62Lxxx 28 CMP0_RLT - 0 0 29 CMP
Page 265 and 266:
XN62Lxxx - 2 0 • 16 1 (CT16B1)
Page 267 and 268:
XN62Lxxx DMA 816 32 DMA 32 DMA
Page 269 and 270:
XN62Lxxx 19.5.1 DMA DMA Table 19-
Page 271 and 272:
XN62Lxxx [c] = 1 dma_sreq[c] DMA
Page 273 and 274:
XN62Lxxx Table 19-14: (CHNL_PRIORI
Page 275 and 276:
XN62Lxxx ... ... 27 19.7.4 DMA
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XN62Lxxx 19.7.5.3 DMA channel_cfg
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XN62Lxxx 00 = . 01 = . 10 = . 11 =
Page 281 and 282:
XN62Lxxx Flash Control Address Addr
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XN62Lxxx 20.3.1 A/B Flash SRAM A,
Page 285 and 286:
XN62Lxxx : #08H : #09H : #0AH : #0B
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XN62Lxxx : 0x15H : 20.4.7 : 0x16H
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XN62Lxxx : AB (32 ) (128 ) (128 ) -
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XN62Lxxx IAP iap_entry (command, r
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XN62Lxxx 22 1.0 Initial Release
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