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XN62Lxxx M IPR : • IPR , N, N = M DIV 4 • IPR M MOD 4, : – 0 7:0 – 1 15:8 – 2 23:16 – 3 31:24 5.4.7.1 NMI ARM Cortex-M0 (NMI). Table 5-17: NMI (INTNMI, 0x4004 8174) 5:0 NMISRC NMI . - 0 ~ 3 wake -up 0~3 4 PWM 0 5 PWM 1 6 PWM 2 7 PWM2 8 ADC1 9 ADC2 10 UART2 11 UART3 12 TWS 13 CT16B0 14 CT16B1 15 CT32B0 16 CT32B1 17 SPI 18 UART0 19 UART1 20 21 ADC0 22 WDT 23 BOD 24 PWM0 25 PIO0 26 PIO1 27 PIO2 30 www.xinnovatech.com
XN62Lxxx 28 PWM1 29 DMA 30 RTC 31 DAC 32~62 63 NMI 31:6 - - 0x0 5.5 (SysTick) Cortex-M0 10 Cortex-M0 Cortex-M0 • RTOS 100Hz (SysTick) • . • • / COUNTFLAG • 24 • • Table 5-18: ( 0xE000 E000) SYST_CSR R/W 0x010 0x0000 0000 SYST_RVR R/W 0x014 0x0000 0000 SYST_CVR R/W 0x018 0x0000 0000 5.5.1 Cortex-M0 Table 5-18: (SYST_CSR - 0xE000 E010) 0 ENABLE 0 0 1 1 TICKINT 0 0 1 www.xinnovatech.com 31
Page 1 and 2: XN62Lxxx 32 IC ARM + xDSP , 88K
Page 3 and 4: XN62Lxxx 2 . Flash (bytes) SRAM
Page 5 and 6: XN62Lxxx www.xinnovatech.com 5 3.2
Page 7 and 8: XN62Lxxx 3.4 Table 3-1: QFP64 QF
Page 9 and 10: XN62Lxxx QFP64 QFP48 MISO/
Page 11 and 12: XN62Lxxx QFP64 QFP48 PWM1_5
Page 13 and 14: XN62Lxxx QFP64 QFP48 PIO2_1
Page 15 and 16: XN62Lxxx CT16B1_MAT1 O PIO0_16 PIO1
Page 17 and 18: XN62Lxxx 5 5.1 ARM Cortex-M0 Cort
Page 19 and 20: XN62Lxxx Private peripheral Reserve
Page 21 and 22: XN62Lxxx 0xE000E000 ~ 0xE000E0FF 0x
Page 23 and 24: XN62Lxxx 17:12 VECTPENDING RO : 2
Page 25 and 26: XN62Lxxx Table 5-7: (CCR, 0xE000-ED
Page 27 and 28: XN62Lxxx 0~3 33 17 0x84 SPI (2) T
Page 29: XN62Lxxx 31:0 SETPEND IRQ0~IRQ31 .
Page 33 and 34: XN62Lxxx • • • • Table
Page 35 and 36: XN62Lxxx RESET#Schmitt trigger 15
Page 37 and 38: XN62Lxxx 5 - - 0x0 6 BODINTCLR -
Page 39 and 40: XN62Lxxx 31:9 - - 0x0 5.6.2.4 20
Page 41 and 42: XN62Lxxx 12MHz 50MHz 6 100 01 () 2
Page 43 and 44: XN62Lxxx 7:0 DIV AHB 0 0x01 1: 1.
Page 45 and 46: XN62Lxxx 1 25 ADC2 ADC2 1 0 1 2
Page 47 and 48: XN62Lxxx 0x01 0x03 ~ 0xFF 1 3 ~
Page 49 and 50: XN62Lxxx 5.6.3.3 RTC RTC 32 1 kHz
Page 51 and 52: XN62Lxxx 1 31:16 - - 0 5.6.3.6 P
Page 53 and 54: XN62Lxxx 1. PCON DPDEN 0 2. ARM
Page 55 and 56: XN62Lxxx RTC XN62L • WAKEUP XN
Page 57 and 58: XN62Lxxx 3 ERPIO0_3 PIO0_3 0 0 =
Page 59 and 60: XN62Lxxx 0 SRPIO0_0 PIO0_0 0 0 = 1
Page 61 and 62: XN62Lxxx 1 DMA 11 PWM0_RST_N PWM0
Page 63 and 64: XN62Lxxx 0x3 3 3 15:13 CLK_DIV
Page 65 and 66: XN62Lxxx PIO0_7 R/W 0x064 PIO0_7/C
Page 67 and 68: XN62Lxxx 5.7.2.2 PIO0_1 IOCON Tabl
Page 69 and 70: XN62Lxxx 5.7.2.4 PIO0_3 IOCON Tabl
Page 71 and 72: XN62Lxxx 0x5 0x6 IOCONFIGCLKDIV5. I
Page 73 and 74: XN62Lxxx 0x4 0x5 0x6 IOCONFIGCLKDIV
Page 75 and 76: XN62Lxxx 0x1 0x2 0x3 0x4 0x5 0x6 IO
Page 77 and 78: XN62Lxxx 2:0 FUNC . 000 0x0 0x1 0x
Page 79 and 80: XN62Lxxx 6 INV 0 0 . 1 . 7 - . 1
Page 81 and 82:
XN62Lxxx 1 . 5 - . 0 6 INV 0 0 . 1
Page 83 and 84:
XN62Lxxx 0 . 1 . 5 - . 0 6 INV 0 0
Page 85 and 86:
XN62Lxxx 0 . 1 . 5 - . 0 6 INV 0 0
Page 87 and 88:
XN62Lxxx 0x3 0x4 0x5 CT32B0_CAP3.
Page 89 and 90:
XN62Lxxx 2:0 FUNC . 000 0x0 0
Page 91 and 92:
XN62Lxxx 0x6 IOCONFIGCLKDIV6. 31:16
Page 93 and 94:
XN62Lxxx 0x3 3 3 15:13 CLK_DIV
Page 95 and 96:
XN62Lxxx 0x0 0x1 0x2 0x3 1 1 2
Page 97 and 98:
XN62Lxxx 1 12:11 S_MODE 00 0x0 0x
Page 99 and 100:
XN62Lxxx 1 . 10 OD 0 0 1 12:11
Page 101 and 102:
XN62Lxxx 8 - . 0 9 DRV . 0 0 1 .
Page 103 and 104:
XN62Lxxx 1 8 - . 0 9 DRV . 0 0 1
Page 105 and 106:
XN62Lxxx 1 . 7 - . 1 8 - . 0 9 DRV
Page 107 and 108:
XN62Lxxx 5 - . 0 6 INV 0 0 . 1 .
Page 109 and 110:
XN62Lxxx 4 MODE (). 1 0 . 1 . 5 -
Page 111 and 112:
XN62Lxxx 0x5 PWM1_5. 3 - 0 4 MODE
Page 113 and 114:
XN62Lxxx 0x2 0x3 0x4 0x5 0x6 CT32B
Page 115 and 116:
XN62Lxxx 5.7.2.19 PIO2_9 IOCON Tab
Page 117 and 118:
XN62Lxxx 0x3 0x4 0x5 0x6 IOCONFIGCL
Page 119 and 120:
XN62Lxxx 0x1 0x2 0x3 0x4 0x5 0x6 IO
Page 121 and 122:
XN62Lxxx 0x2 0x3 0x4 0x5 0x6 IOCONF
Page 123 and 124:
XN62Lxxx 6 PWM 6.1 XN62L 3 PWM0P
Page 125 and 126:
XN62Lxxx 6.2 PWM Table 6-1: PWM
Page 127 and 128:
XN62Lxxx 6.3.1 PWM Table 6-3 PWM (
Page 129 and 130:
XN62Lxxx 26 CH2OUTEN 2 0 0 1 27
Page 131 and 132:
XN62Lxxx PWM 4 FTACK4 1 FFLAG40
Page 133 and 134:
XN62Lxxx 4 OUT4 PWMn_4 0 0 0 1 1
Page 135 and 136:
XN62Lxxx Table 6-11: PWM (DMAP1) 1
Page 137 and 138:
XN62Lxxx 0 1 12 TOPNEG67 PWMn 6
Page 139 and 140:
XN62Lxxx 1 1 12 FAULTVAL4 PWM FPS
Page 141 and 142:
XN62Lxxx Match 0 PWMn_0 0PWMn_1
Page 143 and 144:
XN62Lxxx 0 CNTR VAL5 1 CNTR VAL
Page 145 and 146:
XN62Lxxx 4 3 2 Up Counter Modulus =
Page 147 and 148:
XN62Lxxx PWM 0 PWM 2 PWM 4 AC Input
Page 149 and 150:
XN62Lxxx Desired Load Voltage Deadt
Page 151 and 152:
XN62Lxxx 4 3 2 Up/Down Counter Modu
Page 153 and 154:
XN62Lxxx Up/Down Counter Reload Cha
Page 155 and 156:
XN62Lxxx LDFQ[3:0] = 0000 = Reload
Page 157 and 158:
XN62Lxxx Table 6-23: PWM PWMn_0 P
Page 159 and 160:
XN62Lxxx 7 GPIO 7.1 XN62L 55 GPIO
Page 161 and 162:
XN62Lxxx 7.3.3 GPIO 0 1 GPIO GP
Page 163 and 164:
XN62Lxxx 1 . 7.3.11 GPIO lE Tab
Page 165 and 166:
XN62Lxxx CAPTURE REGISTER 3 CAPTURE
Page 167 and 168:
XN62Lxxx - - 0x040 - 0x06C - CTCR
Page 169 and 170:
XN62Lxxx 0 5 MR1S MR1 TC TC PC T
Page 171 and 172:
XN62Lxxx 0 10 CAP3FE 1 1 1 0 CR
Page 173 and 174:
XN62Lxxx PCLK CAP CAP PCLK CAP
Page 175 and 176:
XN62Lxxx 8.3.11.3 Primary Second
Page 177 and 178:
XN62Lxxx CAPTURE REGISTER 3 CAPTURE
Page 179 and 180:
XN62Lxxx 2 MR2INT 2 0 3 MR3INT 3
Page 181 and 182:
XN62Lxxx 0 8 MR2S MR2 TC TC PC T
Page 183 and 184:
XN62Lxxx 9.3.9 Table 9-11: (CR0
Page 185 and 186:
XN62Lxxx 2:0 CTM / PCLK 00 (PC) P
Page 187 and 188:
XN62Lxxx 10 (WDT) 10.1 • •
Page 189 and 190:
XN62Lxxx 1 WARNINT WINDOW (WDTC)
Page 191 and 192:
XN62Lxxx 0x1 WDT 0x2 0x3 . . 30:
Page 193 and 194:
XN62Lxxx WDCLK / 4 Watchdog Counter
Page 195 and 196:
XN62Lxxx FILTER_CR R/W 0x280 0x000
Page 197 and 198:
XN62Lxxx 11.2.9 CORDIC X Table 11-
Page 199 and 200:
XN62Lxxx 15:0 FILTER_RESULT . 0 16
Page 201 and 202:
XN62Lxxx 2. CORDIC_X, CORDIC_Y COR
Page 203 and 204:
XN62Lxxx 5. www.xinnovatech.com 20
Page 205 and 206:
XN62Lxxx 12.2 Table 12-1: UART0,1
Page 207 and 208:
XN62Lxxx 1 THR . 3 RBRIE RBR 0
Page 209 and 210:
XN62Lxxx 12.4.2 IrDA UART IRDAEN
Page 211 and 212:
XN62Lxxx CR0 R/W 0x000 0 0x0
Page 213 and 214:
XN62Lxxx 15:0 DATA TNF 1 Tx FIFO
Page 215 and 216:
XN62Lxxx 13.3.9 SPI 1 SPI FIFO
Page 217 and 218:
XN62Lxxx Figure 13-2: SPI CPOL = 0
Page 219 and 220:
XN62Lxxx CLK FS DX/DR MSB LSB 4 to
Page 221 and 222:
XN62Lxxx IMSC R/W 0x014 RIS RO 0x
Page 223 and 224:
XN62Lxxx 14.3.6 4 Table 14-8: (I
Page 225 and 226:
XN62Lxxx CLK CS DI MSB LSB DO Q MSB
Page 227 and 228:
XN62Lxxx www.xinnovatech.com 227
Page 229 and 230:
XN62Lxxx 15.3 Table 15-2: ( 0x400
Page 231 and 232:
XN62Lxxx TWSEN: TWS • TWS EN 1
Page 233 and 234:
XN62Lxxx Table 15-11: TWS (MASK0 -
Page 235 and 236:
XN62Lxxx S SLAVE ADDRESS RW=1 A DAT
Page 237 and 238:
XN62Lxxx reception of the own Slave
Page 239 and 240:
XN62Lxxx 15.4.6 TWS Table 15-14:
Page 241 and 242:
XN62Lxxx STA TXRX STO SI AA 0x4a S
Page 243 and 244:
XN62Lxxx 15.4.7.6 : 0x0b 0x01 AC
Page 245 and 246:
XN62Lxxx 1. CONCLR 0x08 SI 2. 3.
Page 247 and 248:
XN62Lxxx 16 RTC 16.1 1 Hz/1KHz RT
Page 249 and 250:
XN62Lxxx 16.3.7 RTC Table 16-9: RT
Page 251 and 252:
XN62Lxxx 17.2 Table 17-1: ADC
Page 253 and 254:
XN62Lxxx 11:0 RESULT DONE 1 SELNO
Page 255 and 256:
XN62Lxxx 31 DONE A/D 1 0 17.3.6 AD
Page 257 and 258:
XN62Lxxx 9 DACCLR 0 1 0 0 10 DA
Page 259 and 260:
XN62Lxxx Temperature Slope(°C LSB
Page 261 and 262:
XN62Lxxx ACMP0_O 0 ACMP1_O 1
Page 263 and 264:
XN62Lxxx 28 CMP0_RLT - 0 0 29 CMP
Page 265 and 266:
XN62Lxxx - 2 0 • 16 1 (CT16B1)
Page 267 and 268:
XN62Lxxx DMA 816 32 DMA 32 DMA
Page 269 and 270:
XN62Lxxx 19.5.1 DMA DMA Table 19-
Page 271 and 272:
XN62Lxxx [c] = 1 dma_sreq[c] DMA
Page 273 and 274:
XN62Lxxx Table 19-14: (CHNL_PRIORI
Page 275 and 276:
XN62Lxxx ... ... 27 19.7.4 DMA
Page 277 and 278:
XN62Lxxx 19.7.5.3 DMA channel_cfg
Page 279 and 280:
XN62Lxxx 00 = . 01 = . 10 = . 11 =
Page 281 and 282:
XN62Lxxx Flash Control Address Addr
Page 283 and 284:
XN62Lxxx 20.3.1 A/B Flash SRAM A,
Page 285 and 286:
XN62Lxxx : #08H : #09H : #0AH : #0B
Page 287 and 288:
XN62Lxxx : 0x15H : 20.4.7 : 0x16H
Page 289 and 290:
XN62Lxxx : AB (32 ) (128 ) (128 ) -
Page 291 and 292:
XN62Lxxx IAP iap_entry (command, r
Page 293:
XN62Lxxx 22 1.0 Initial Release
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