Compressive Sensing system for recording of ECoG signals in-vivo

August, 31 th , 2012Compressive Sensing systemfor recording of ECoG signalsin-vivo- Master Thesis Project –Mariazel Maqueda Lópezin fulfilment of the thesis requirements for the degree ofMaster in Micro and Nanotechnologiesin a collaboration withIMECsupervised byProf. Alexandre SchmidMahsa ShoaranRefet Firat YaziciogluSrinjoy Mitra

To my mother3

The present project has been submitted to Grenoble INP - Phelma in______________________ at the date of ______________________ by the studentMariazel Maqueda López.Sign of the student:Sign of the Administration:5

AcknowledgmentsI would like to thank Prof. Alexandre Schmid, from EPFL, and Firat Refet Yazicioglu, from IMEC,the great chance they have given to me by accepting my application to carry out the presentmaster thesis in both Microsystems Laboratory (LSM, EPFL) and Ultra Low Power and ExtremeElectronics group (ULPEXEL, IMEC).It has been a challenge to settle in both, university and spin-off environments in such a shortperiod of time. As student I have learnt from some of the best professionals, but the experiencehas extended to much more than the knowledge, because I have been included in twowonderful groups of persons.In the same way, I am immeasurably grateful for the help that Mahsa Shoaran and Srinjoy Mitrahave provided to me. Mahsa, thank you very much for the support and the good ideas. Srinjoy,thank you for the patience and those useful feedbacks.I am not allowed to forget Nikola Katic, Jie Zhang, Narasimha Venkata and Dhurv Chhetri forour enlightening discussions, which have boosted me to evolve along these months of work.Thanks to my family to be able to put up with the distance not only during the thesis period, ifnot along these two long and short years of working hard in the Nanotech Master. Without yourunwavering support, all of these enriching months had not been possible. I specially has tomention Jesús Maqueda Paniza, the new life was bloomed in between our large and lovedfamily, in some years you will understand that my heart was with you in the distance of yourshort first steps.Thanks to all of you, people from Leuven, to make the last episode of this adventure such anincredible farewell.Finally, I would like to particularly recognize the effort that Panagiota Morfouli, Fabrizio Pirri,Suzanne Buffat and many more people have carried out to bring to fruition the seventhgeneration of Nanotech Master students, there are not enough words to extol the wonderfulacademic proposal that you have brought to us.7

AbstractThe project “Compressive Sensing system for recording of ECoG signals in-vivo” has beencarried out as challenging collaboration between the Microelectronic System Laboratoy (LSM)of the École Polytechnique Fédérale de Lausanne (EPFL, Switzerland) and the researchnanotechnology centre IMEC, (Leuven, Belgium). In this way, the context of the thesis has beenboth, academic and industrially oriented. Regarding the latest ranking from Leiden Universityhas just been released at the end of 2011, and EPFL comes in at number twelve in the worldranking and tops the table as the first non-American institution. EPFL and ETHZ, at 12th and18th place respectively, rank as the top two non-American institutions. Considering IMEC, it hasbuilt a research campus is headquartered in Leuven, but additional R&D teams in TheNetherlands, China, Taiwan, and India, and offices in Japan and the USA Belgium. It extendsover 24,400m² of office space, laboratories, training facilities, and technical support rooms,including a 300nm and a 200mm cleanroom.During the period which has taken place in EPFL, the motivation of the present project hasbeen, first of all, a deep study of the state of art of the new revealing methodology of signalcompression called Compressive Sensing. This phase has included mathematical basis toaccomplish compression, applicability scope and a wide range of different kind algorithms forthe signal recovery solution. In this way, models in Matlab and Simulink have been implementedin order to apply an efficient compression and a reliable reconstruction.In the last years, Compressive Sensing has emerged as a revolutionary compression techniquefor sparse biological signals, which are becoming a high-dense source of information inmultielectrodes arrays-based bio-systems. Due to this fact, it has been studied how applying thenovel technique of Compressive Sensing in multichannel-multipath on-chip acquisition systemfor the recording of Electrocorticography (ECoG) and Action Potentials (AP). ECoG and APneural signals have been proved to fit with the Compressive Sensing system requirements.As a conclusion of the period in LSM, the publication “Circuit-Level Implementation ofCompressed Sensing for Multi-Channel Neural Recording” has been submitted as the firstreference about what has been called Spatial Compressive Sensing (SCS), a new method tocompress signals which are distributed over an array of multielectrodes and are sparse in thespatial domain. Compressibility and reconstruction have been proved by differentimplementations in Matlab and Cadence frames. In the same publication, a new, more compactand parallel random generator system based on serial PRBSs has been submitted.During the period in IMEC, a deepest study of the circuitry integration for Compressive Sensingoperation in neural signals has been accomplished. More specifically, a novel circuitryimplementation, for the mixing and integration of the incoming signals, has been proposedaccording to an analog approach for the multipath topology.9

AbstraitLe projet " Compressive Sensing system for recording of ECoG signals in-vivo " a été réaliséavec une collaboration de défi entre le Laboratoire des Systèmes Microélectroniques (LSM) del'Ecole Polytechnique Fédérale de Lausanne (EPFL, Suisse) et le centre de recherche ennanotechnologie IMEC (Louvain, Belgique). Ainsi, la thèse a pu être abordée de manière à la foisacadémique et industrielle. Dans le dernier classement publié à la fin 2011 par l'Université deLeiden, l'EPFL arrive en douzième place et est en tête des universités non américaines. L'EPFL etl'ETHZ, 12ème et 18ème respectivement, se classent comme les deux meilleurs institutions nonaméricaines. IMEC quant à lui est constitué d'un centre de recherche basé à Louvain, mais aussides équipes R&D aux Pays-Bas, en Chine, à Taiwan et en Inde, ainsi que des bureaux au Japon etaux Etats-Unis. Le centre de Louvain s'étend sur 24.400m 2 de bureaux, laboratoires, centres deformation ainsi que de locaux de support technique dont des salles blanches de 300nm et 200mm.Durant la période à l'EPFL, le but de ce projet était avant tout une étude approfondie sur la toutenouvelle méthode de compression de signal appelée Compressive Sensing. Cette partie contenaitdes bases mathématiques pour accomplir la compression, la fenêtre d'applicabilité et un largeéventail d'algorithmes pour la reconstitution du signal. Pour ce faire, des modèles Matlab et Simulinkont été mis en place pour appliquer une compression efficace et une reconstruction fiable.Ces dernières années, le Compressive Sensing a émérgé comme une technique de compressionrévolutionnaire pour les signaux biologiques sparses, qui deviennent des sources importantesd'information dans les bio-systèmes basés sur des rangées de microélectrodes. De ce fait, il a étéétudié comment cette nouvelle technique de Compressive Sensing dans des systèmes d'acquisitionmulti-canal/multi-trajet on-chip pouvait être utilisée pour l'enregistrement d'Electrocorticographie(ECoG) et de potentiels d'action (AP). Il a été montré que les signaux neuraux ECoG et AP étaientcompatibles avec les exigences des systèmes de Compressive Sensing.En guise de conclusion de la période passée au LSM, l'article " Circuit-Level Implementation ofCompressed Sensing for Multi-Channel Neural Recording" a été soumis en tant que premièreréférence sur ce qu'on appelle le Spatial Compressive Sensing (SCS), une nouvelle méthode pourcompresser les signaux qui sont distribués sur une rangée de multiélectrodes et qui sont sparsesdans le domaine temporel. La compressibilité et la reconstruction ont été démontrée dans différentesimplémentations dans Matlab et Cadence. Dans ce même article, un nouveau générateur aléatoire,plus compact et parallèle basé sur des PRBS en série a été développé.Durant la période à IMEC, une étude plus approfondie de l'intégration des circuits de détection pourla compression de signaux neuronaux a été accomplie. Plus précisément, un nouveau circuit pour lemélange et l'intégration des signaux entrants a été proposé selon une approche analogue à latopologie multi-trajet.11

RiassuntoIl progetto “Compressive Sensing system for recording of ECoG signals in-vivo” è statorealizzato attraverso una stimolante collaborazione tra il Microelectronic System Laboratory (LSM)dell'École Polytechnique Fédérale de Lausanne (EPFL, Svizzera) e il centro di ricerca sulla micro enanotecnologia, IMEC, (Leuven, Belgio). In questo modo, il contesto della tesi è stato sia,accademico che industriale. Per quanto riguarda l'ultima classifica dell'Università di Leiden alla finedel 2011, l’EPFL arriva al numero dodici della classifica mondiale e in cima alla tabella come la primaistituzione non americana. EPFL e ETHZ, al 12° e 18° posto, rispettivamente, sono le due primeistituzione non americane. Per quel che riguarda IMEC, si tratta di un campus di ricerca con sede aLovanio, ma ha sedi distaccate nei Paesi Bassi, Cina, Taiwan e India, e uffici in Giappone e negliStati Uniti in Belgio. Si estende su 24.400 m² di spazio per uffici, laboratori, strutture di formazione esale di supporto tecnico, tra cui ci sono due cleanroom di 300 nm e 200mm.Durante il periodo trascorso preso l’EPFL, la motivazione del presente progetto è stata, prima ditutto, uno studio approfondito dello stato dell’arte della nuova metodologia di compressione deisegnali chiamato Compressive Sensing. In questa fase, sono state studiate le base matematiche perrealizzare la compressione, l’applicabilità del metodo e una vasta gamma di algoritmi per lasoluzione del recupero dei segnali. In questo modo, sono stati svilupatti dei modelli in Matlab eSimulink per applicare una compressione efficace e una ricostruzione affidabile.Compressive Sensing è diventata una tecnica di compressione rivoluzionaria per i segnali biologiciclassificati come sparsi, densa fonte di informazioni in biosistemi di multielettrodi. Per tanto, in questoprogetto è stato studiato come applicare la nuova tecnica Compressive Sensing in un sistemamulticanale on-chip orientato all’acquisizione di Electrocorticografia (ECoG) e Potenziali di Azione(AP). I segnali neurali ECOG e AP hanno dimostrato di adattarsi ai requisiti del CompressiveSensing.Come conclusione del periodo di LSM, la pubblicazione “Circuit-Level Implementation ofCompressed Sensing for Multi-Channel Neural Recording” è stata presentata come il primoriferimento dello Spatial Compressive Sensing (SCS), un nuovo metodo per la compressione deisegnali che sono distribuiti su un array di multielettrodi e sono sparsi nel dominio spaziale. Lapossibilita di comprimere e ricostruire questi segnali è stata dimostrata mediante implementazioni inMatlab e Cadence. Nella stessa pubblicazione, un nuovo e più compatto generatore causaleparallelo basato in PRBS seriale è stato presentato.Durante il periodo in IMEC, un più profondo studio della integrazione dei circuiti perl’implemenntazione de un sistema basato in Compressive Sensing per l’applicazione in segnalineurali è stato realizzato. Più in dettaglio, una nueva implementazione dei blocchi necessari pereffettuare il mixing e l'integrazione dei segnali in ingresso è stato proposto secondo un approccioanalogico per la topologia di multipath.13

Gantt’s ChartNotes: Red indications mean interleaved tasks. Green indications mean a finished tasks flow. Yellow indications mean EPFL-IMEC meetings.

IndexAcknowledgments 7Abstract 9Gannt’s Chart 151. Introduction: Framework for Compressive Sensing 252. State of the art 292.1. Neural Signals: EEG, ECoG and AP 292.2. Neural Signal Acquisition Systems On-Chip 302.3. Data Compression Methods 322.4. Compressive Sensing 332.4.1. Compressive sensing in a nutshell 332.4.2. Sparsifying bases 352.5. Reconstruction Methods 353. ECoG and AP Compressive Sensing System Design 373.1. Power Consumption Analysis 373.2. Single and Multi Channel Approach 384. Random Matrix Generation 394.1. Digital Implementation: Pseudo Random Binary Sequence (PRBS) 394.1.1. Basics of PRB: Serial and Parallel Implementation 394.1.2. Flips-Flops: Power and Area Analysis 424.1.3. Serial Implementation with two PRBS 434.1.4. Randomness Checking 455. System Level Design 475.1. Matlab and Simulink Models 475.2. Multi-Channel Implementation of Compressive Sensing 505.3. Reconstruction Method Application 5217

5.3.1. Basis Pursuit Denoising Method (BPDM) 525.3.2. Least Absolute Shrinkage and Selection Operator (LASSO) 536. Analog Path Design 546.1. Design Discussion 546.2. Mixing and Integration 556.2.1. Passive Integration 556.2.2. Ideal Active Inverting Integration 586.2.3. DC-Offset Controlled Active Integration 616.2.4. Switched-Capacitor Integrator with parasitic effects 636.2.5. Non inverting SC Integrator without parasitic effects 666.2.6. SNR Calculations 687. Conclusions 717.1. Remarks 717.2. Next steps 72Appendix 73Appendix A 73Appendix B 75B.1. Digital Implementation 75B.2. Analog Implementation 76B.2.1. Current Mode 76B.2.2. Voltage Mode 77B.2.3. Charge Mode 79Appendix C 81C.1. Analog Implementation 81C.1.1. Direct Amplification of Noise 81C.1.2. High-Frequency Oscillator Sampling 81Appendix D 83Appendix E 84E.1. Amplification 8418

E.2. Signal Digital Conversion 84Glossary 87References 8919

Index of ImagesFigure 1.1. Energy a power costs for a typical biosensor configuration 26Figure 1.2. Integrated Neural Interface (INI) 26Figure 1.3. Characteristic Action Potential signal. 27Figure 2.2.1. Example of wireless neural recording system 31Figure 2.3.1. Transmission and Reception schemes in CS 32Figure 2.4.1.1. Sketch of Compressive Sensing operation 34Figure 2.4.2.1. Tree structure of 3-level decomposed wavelet coefficients 35Figure 2.5.1. l 1 -minimization approaches to l 0 -minimization approach 36Figure 3.4.1. Analog implementation proposal for neural acquisition channel 38Figure 4.1.1.1. LSFR parallel (top) and serial (bottom) architectures 41Figure 4.1.1.2. Galois (top) and Fibonacci (bottom) configurations 41Figure 4.1.2.1. Reset-based Flip-Flop 42Figure 4.1.2.2. TSPC Flip.Flop 42Figure 4.1.3.1.Random Generator 43Figure 4.1.3.2. Serial Implementation with two PRBS (4-FF and 5-FF) 44Figure 4.2.3.3. Random states propagation by columns to the measurement matrix 44Figure 5.1.1. Simulink implementation of a path 48Figure 5.1.2. Details of the CS operation blocks for a path. 48Figure 5.1.3. Compressed signal comparison 49Figure 5.1.4. LASSO method reconstruction comparison 49Figure 5.1.5. BPDN method reconstruction comparison 50Figure 5.2.1. Spatial CS example 51Figure 5.2.2. Original and reconstructed signal by applying SCS 52Figure 6.5.1.1. Mixer and passive integrator circuitry 5320

Figure 6.2.1.2. Input signal Spectra 56Figure 6.2.1.3. Compressed signals comparison 57Figure 6.2.1.4. LASSO reconstruction comparison 58Figure 6.2.1.5. BPDN method reconstruction comparison 58Figure 6.2.2.1. Mixer and ideal active inverting integrator circuitry 59Figure 6.2.2.2. Ideal amplifier 59Figure 6.2.2.3. Compressed signals comparison 60Figure 6.2.2.4. LASSO reconstruction comparison 60Figure 6.2.2.5. BPDN method reconstruction comparison 61Figure 6.2.3.1. Modified active integrator 61Figure 6.2.3.2. Compressed signal comparison 62Figure 6.2.3.3. LASSO method reconstruction comparison 63Figure 6.2.3.4. BPDN method reconstruction comparison 63Figure 6.2.4.1. Switched-Capacitor Integrator with parasitic effect 64Figure 6.2.4.2. Compressed signal comparison 65Figure 6.2.4.3. LASSO method reconstruction comparison 65Figure 6.2.4.4. BPDN method reconstruction comparison 66Figure 6.2.5.1. Switched-Capacitor Integrator without parasitic effects 66Figure 6.2.5.1. Compressed signal comparison 67Figure 6.2.5.2. LASSO method reconstruction comparison 67Figure 6.2.5.3. BPDN method reconstruction comparison 68Figure B.1.1 Block diagram for a digital implementation of one CS channel 75Figure B.1.2. Power consumption versus bandwidth for the digital implementation 76Figure B.2.1.1. Circuit implementation of the proposed CS receiver 77Figure B.2.2.1. Block diagram for an analog implementation 78Figure B.2.2.2. Power consumption versus bandwidth for the analog implementation 7821

Figure B.2.3.1. Switched Capacitor circuit implementation of the CS ADC 79Figure B.2.3.2. Binary-weighted SC MDAC/summer for CS 80Figure C.1.1.1. Random generator based on direct amplification of noise 81Figure C.1.2.1. Basic oscillator-based TRNG 82Figure E.2.1. Several techniques to digitize different kind of neural signals 8522

Index of TablesTable 2.1.1. Summary of main Neural Signals 30Table 5.1. Main parameters of the CS analog design 47Table 6.2.1.1. Main parameters for the simulation of the Passive Integrator-based multipath channel 56Table 6.2.4.1. Main parameters for the simulation of the SC Integrator-based multipath channel 64Table 6.2.6.1. SNR comparison between topologies and reconstruction methods 69Table A.1. Main Reconstruction Methods 73Table B.1.1. CS model specifications 75Table B.2.1.1. CS model specifications 77Table D.1. Selected crosses for 16 outputs through a 4FF-PRBS and a 5FF-PRBS 83Table E.1.1. Main features of a front-end amplifier for neural recording 8423

1. Introduction: Framework for Compressive SensingIn many applications, including imaging systems, high-speed analog to digital converters, homeautomation, environmental and medical monitoring and real-time diagnosis devices, datacompression turns in an indispensable requirement due to the large amount of information thathas to be integrated preferably in a low cost, low power and compact way. The technique calledCompressive Sensing has recently emerged as a compression method which easily enables theintegration on-chip of the compression algorithm, prosecuting a local signal processing in-situ.Nowadays, in the case of biosignal-based systems, the number of sensor nodes rises upaccording to the high dense integration phase of the CMOS technologies, so an increasing ofenergy efficiency is essential to the continued development of the biomedical applications [1].As it is shown in Chapter 2, data reduction firstly means a decreasing in the measurements tobe transmitted, which gives rise to a saving in power and area from the point of view of thenecessary processing devices, and secondly due to the fact that by employing a robustcompression technique the true signal information can eventually be better differentiated fromartifacts during signal recovery.Among all the applications have been mentioned above, in particular, medical monitoring hasrevealed as a challenging field of compression methods application due to the increasingnecessity of more implantable sensor nodes based on wireless technologies to achieve reliablemedical information. That translates into a higher integration of sensors in the same availablearea, which have to consume as little power as possible in order to minimize the numbers oftimes in which the power supplying batteries have to replaced, and so reducing costly surgeriesand improving the quality of life of patients. This kind of sensors is included within the WirelessBody Sensor Network (WBSN) or Body Area Network (BAN) nodes that are intended forpersonal health monitoring and assisted living, but also branch into lifestyle, sports andentertainment applications [2].As it has been introduced above, BAN systems are based on ultra-low power consumptiontendency in order to increase the energy autonomy of the devices. Nonetheless, BANs generatelarge data rates which intrinsically imply an increasing in the power consumption relates to theamplification, conversion, processing and over all, transmission of the information. Therefore,medical monitoring based on BAN devices is an emerging application area which perfectlyexemplifies a scenario to apply integrated data compression.In Fig.1.1, it is shown the energy and power costs for a typical wireless biosensor [3]. It is clearthat the transmitter results in an energy cost of approximately 1nJ/bit, much more than anyother component of the acquisition system, hence a data reduction approach should be takeninto consideration in order to minimize the energy cost of the system and maximize the datathroughput.25

Figure 1.1. Energy a power costs for a typical biosensor configuration [4, 5, 6 7, 8].In applications such an implantable neural recording arrays, as the number of microelectrodewithin the arrays have increased in order to simultaneously understand the dynamics of manyneurons at almost single neuron scale, the data reduction becomes mandatory in order to beable to transmit the recorded data. As a matter of fact, in recent years the advance in thedevelopment of multichannels microprobes, for recording neural activity, has supposed asignificant milestone towards integrated microimplanted wireless devices for clinical applicationsin the study of chronic illness, such as epilepsy.In Fig.1.2 it is depicted an example of an array for neural data acquisition which has beendeveloped by researchers from the University of Utah [9]. It is possible to observe theintegration density of the platinum-tipped silicon microelectrodes over a volume of 4 x 4 x 1.5mm 3 , which have been implemented in a matrix of 10 x 10 microelectrodes. It has to be takeninto consideration that independently from the resolution, when multielectrodes are placed in thebrain it is common for some electrodes to detect spikes from several distinct neurons whileother electrodes may see no resolvable spikes.Figure 1.2. Integrated Neural Interface (INI) developed by University of Utah [9]. The 10 x 10microelectode array has been implemented with an inter-probe distance of 400μm.Neural signals acquisition systems, as ECoG and Action Potentials (AP), play a challenging rolein the biomedical applications development which has been introduced along this chapterbecause of the saving in area and power which have to be mandatorily achieved in order toimplant the chips in human brains.26

The final target is to reliably record as many data as possible, which will define the number ofchannels, by keeping, as far as possible, the time and amplitude features of the signals. Thiswill state the processing and data transmission, so accordingly, data reduction becomes acritical point in the design.As it is shown in Chapter 3, numerous strategies for implementing integrated data compressionbased on filtering have been developed to record neural spike events. However these solutionsinitially exhibit less reliability to the entire feature extraction because information loss can takeplace due to amplitude or time thresholds choices, and hence, there is a strict trade-off to berespected between data reduction, robustness and implementation cost.In order to introduce the kind of signals are going to be further studied on Chapter 2 and itsmain characteristic, in Fig.1.3 an example of Action Potential has been simulated by Matlab. Itcan be observed that AP can be sorted as sparse/compressed signals, because most of theirtime components are zero or can be approximated by zero voltage. Typical amplitudes do notexist because they vary depending on the individual, but they do not usually overcome a rangeof hundreds of microvolts. The bandwidth that can be considered is of the order of 6-10 kHz.Neither a typical transition time between peaks can be settled, but a peak-to-peak period of1ms, as the one as been depicted below, is a typically registered in AP.Figure 1.3. Characteristic Action Potential signal.27

2. State of the art2.1 Neural Signals: EEG, ECoG and AP [10]A neuron is a cell which transmits bioelectrical information by both an electrical and chemicalsignalling. All neurons are connected between each others in a neural network whichcompounds the brain, spinal cord and peripheral ganglia. The electrical information that isproduced in the neurons is object of study in order to better understand neural diseases asAlzheimer’s, Parkinson’s or epilepsy.The different biopotentials that can be registered from the neurons enclose different kind ofinformation. The extracellular Action Potentials (AP) are generated with the depolarisation of themembrane of a neuron, they have a frequency range between 100 Hz and 10 kHz in a durationof few milliseconds and can occur from 10 to 120 times per second. The typical range ofamplitudes goes from 50 μV to 500 μV.The Electroencephalogram (EEG) consists of the electrical activity resulting from ionic currentflows within the neurons. Its frequency varies between 1 mHz to 200 Hz, and its amplitudebetween 1 to 10 mV. Diagnostic applications generally focus on the type of oscillations that canbe observed in EEG signals. In neurology, the main diagnostic application of EEG is in the caseof epilepsy, because epileptic activity can create clear abnormalities on a standard EEG study.EEG is a key clinical diagnosis and monitoring tool that is frequently used in Brain-ComputerInterfaces (BCI).Because the cerebrospinal fluid (CSF) of the brain as well as the skull and scalp cause asmearing of the recorded electrical potential signals, an intracranial EEG is needed to recoverybrain activity [4]. The Electrocorticogram (ECoG) of subdural EEG signals are biopotentialswhich are measured directly from the surface of the brain with a grid of electrodes implantedunder the skull.Although signals measured with EEG and ECoG stem from the same activation in the brain,there are several differences between them, ECoG has higher amplitude, a broader bandwidth,a higher spatial resolution and is less vulnerable to artifacts so it present a better Signal-to-Noise Ratio (SNR). These differences are mainly due to the fact that, in order to reach the scalpelectrodes of an EEG, electrical signals must also be conducted through the skull, wherepotentials rapidly attenuate due to the low conductivity of bone. Due to all of these advantagesover EEG signals, BCI industry is rapidly moving toward this recording alternative.A summary of the most relevant neural biopotentials has been included in Table 2.1.1.29

Signal Amplitude BandwidthAP 50 to 500 μV 100 Hz to 10 kHzLocal FieldPotentials (LFP)0.5 to 5 mV 2 mHz to 200 HzEEG 1 to 10 mV 1 mHz to 200 HzIonic Current 1 to 10nA 1 mHz to 10 kHzRedox Current 100 fA to 10 μA1 mHz to 100 Hz (amperometry)1 mHz to 10 kHz (FSCV)Table 2.1.1. Summary of main Neural Signals.2.2. Neural Signal Acquisition Systems On-Chip [10]Nowadays, there is an intense development in neuroscience research which is aimed at thedevelopment of new biomedical applications. This clinical target has resulted in the necessarydemand for neural interfacing microsystems capable of monitoring the activity of large groups ofneurons. Such devices are mainly composed of multiple neural probes, functionalized tocapture brain signals, which are connected to multiple processing channels able to extract andtransfer the neural data outside of the brain.As it is submitted in Chapter 1, the two main aims of a neural signal acquisition system isaddressed to minimize area and power requirements, as well as to achieve the largest possibleresolution. An important point to be taken into consideration during the neural recording is theexisting interface capacitance which exists in the contact between metal electrode tip and theneural tissue. The capacitance of the interface depends on the electrode area and surfaceroughness, being values between 150 pF and 1.5 nF the common range of variation.These emerging tools can be sorted into two main classifications, the systems which areoriented to the extraction of relevant neural signals in order to establish a direct interactionbetween an individual, who comes under a severe disability, and a computer or prostheses,these applications are called Brain-Computer Interfaces (BCI). The other possible applicationare those based on recording neural signals in order to subsequently be analyzed, in order toshed some light about chronic neural diseases, as epilepsy.During the last sixty years, the Central Nervous System (CNS) has been object of a prolificresearch. In 1952, the experiments of Hodgkin and Huxley [11], gave rise into a precise modelof the generation of action potentials by neurons. Respectively, in 1957 and 1959, Mountcastle[12] and Hubel [13] established a precise understanding of the visual cortex. In 1986,Georgopoulos [14] probed the correlation between neural populations and movement directionswhich led to the experimentation with non-human primates in order to study their motor cortex30

patterns in response to visual targets in a three-dimensional space [15]. Several examples ofapplications based on neuroprosthetic devices are Taylor [16] and Hochberg [17].In the last years, microelectronics and microfabrication techniques have improved theinterfacing between individuals and analysing/actuation tools by defining new embeddedSystems-on-Chip (SoC) implementations. These systems are not any more cable-based butwireless-based implementations, and so they can be implanted individuals, enabling therecording of neural signals which have been locally generated by a group of neurons,whereupon many noise sources have been removed and the resolution of the acquired signalhas been greatly improved.Miniaturization has led a new era in neural recording, but new limiting considerations have to betaken into account in order to implement such neural acquisition SoC systems. In the state ofthe art of neural recording, plenty of electrodes are integrated in the chip and each of them isconnected with a different signal processing channel. Eventually every channel includes Low-Noise Amplifiers (LNA), data converters, wireless transmitters and receivers and another signalprocessing circuitry as is the case of compression data block. All of the blocks have to beintegrated by considering critical constraints in area, power consumption, bandwidth, size,weight and biocompatibility.Figure 2.2.1. Example of wireless neural recording system [33].Fig. 2.2.1 shows a block diagram of a generic wireless neural recording device [18]. In mostneural recording applications, each signal electrode must have its own dedicated LNA, so thisarray of amplifiers can consume relatively large amounts of power and chip area in amultichannel neural recording system. In the same way, depending on the design constraints,31

each channel must have a shared or dedicated module to process, compress and digitalize thesignal and a transmitter module in order to send out of the scalp the registered information.2.3. Data Compression Methods [18]The traditional approach of signal reconstruction is based on the Shannon-Nyquist samplingtheorem which states that the sampling rate must be twice the highest frequency of the signal.Similarly, the fundamental theorem of linear algebra expresses that the number ofmeasurements should be at least as large as its length in order to ensure a correctreconstruction. The aim of compression methods is to come through these limitations byapplying a reversible reduction to the signal to be transmitted. The empirical observation thatmany types of signals of images can be well-approximated by a sparse expansion in terms of asuitable basis, that is, by only a small, number of non-zero coefficients is the key of many lossycompression techniques such a JPEG or MP3. The compression is carried out by storing thelargest basis coefficients and setting the others to zero, and it is a good technique when fullinformation of the signal is available. However, when the sensing procedure is costly, one mightask about the chance about directly obtaining the compressed version by taking a small amountof linear and non-adaptive measurements. CS technique responds to this compressionapproach, which roughly sketched in Fig. 2.3.1 by considering compression is accomplished inthe input signal x, from N samples to K measurements, being N >> K.Figure 2.3.1. Transmission and Reception schemes in CS.In the last ten years, CS applications have become more and more relevant in the area of signalacquisition and imaging compression. In 2008 Boufounos and Baraniuk have proposed 1-Bit CSmeasurements in order to preserve the sign of the recorded signal [19]. In 2009 Duarte andBaraniuk introduced a variation of CS called Kronecker Compressive Sensing (KCS), whichexploits Kronecker matrix to jointly model as sparsifying basis of multidimensional signals [20].In 2010, an imager/compressor based on real-time in-pixel CS has been developed in the ÉcolePolytechnique Fédérale de Lausanne (EPFL) by applying the concept of Random Convolution[21].32

2.4. Compressive Sensing2.4.1. Compressive sensing in a nutshellThe well-known Shannon-Nyquist sampling theorem establishes that the sampling of a signalhas to be done at a rate at least two times faster than its Fourier bandwidth in order not to loseinformation. Nevertheless, in many applications such data rate has revealed as unreachabledue to limitations in the storage, transmission or acquisition systems required by the processedsignal [22]. Compressive Sensing or Compressive Sampling, (CS) provides an alternative toShannon-Nyquist sampling wherein the signal under acquisition is sparse, that is when an N-dimensional signal fits K

In order to have a clear understanding of the Compressive Sensing operation, in Fig.2.4.1.1 itcan be observed how compression takes places. As it is shown, the compression ratio can beachieved is C R = N/M, where N >> M.Figure 2.4.1.1. Sketch of Compressive Sensing operation when a) x is sparse in the identity basis; b) x issparse in the sparsifying bases Ψ.The CS premise is that under specific conditions, x can be efficiently and accuratelyreconstructed from y. In particular, this is possible if the measurement matrix Φ satisfies the K-Restricted Isometry Property (K-RIP), with constant δ K for all x Є Σ K , which is defined by theexpression [24, 25]:(6)The K-RIP ensures that all the submatrices of Φ of size M x K are close to an isometry, andtherefore distance and information preserving. Model-Based CS theory states that it is possibleto decrease M without sacrificing robustness by combining signal sparsity with structuraldependencies between the values and location of the signal coefficients. This model goesbeyond the K-RIP by establishing what has been called Restricted Amplification Property(RAmP) [22]. Summarizing, there are two key features are needed for implementing CS: a)sparsity of the sampled signal and incoherence between the sparsifying basis and b) themeasurement matrix, which ensures maximum information capture by the compression scheme.Random sensing matrices have a high degree of incoherence with sparsifying basis with highprobability [1]. Effective measurement matrix random entries are drawn from a variety ofpossible distribution, such a Bernoulli, Gaussian and Uniform Distribution. In this way, CSmethod leads to a simplification in the on-line signal acquisition phase against an increasingcomplexity in the off-line recovery of the original signal. Thereby, CS is an optimal solution inapplications in which the recording system has to be kept under restrictive limits of area andpower consumption within the chip, while the post-processing can be done out of the chip. Inthe applications in which peak amplitude and spikes location are more relevant than the exactmorphology, time-domain CS has been used after the signal has been dynamically thresholded.Similarly, frequency-domain CS can be achieved by applying a dynamic smoothing can be usedto limit the number of higher frequency components.34

2.4.2. Sparsifying basesSparsifying basis have been used are identity basis for time-domain sparse reconstruction whenthe signals which are recorded are already sparse in time-domain. The inverse Fouriertransform has been used for frequency-domain sparse reconstruction [1, 22]. The Gabor space[27] has been considered as sparsifying basis for EEG signals which are assumed to becomposed by short sinusoidal bursts. In the same way, wavelet-domain basis area good basischoice for EEG and ECoG signals which are considered as windowed, piece-wise smoothpolynomials with additive noise [34, 35, 36].Figure 2.4.2.1. Tree structure of 3-level decomposed wavelet coefficients.More concretely, in the case of wavelet basis, the wavelets use a multi-scale decomposition, i.e.the coefficients of the wavelet transform are generated in a hierarchical manner using scaledependentlow pass, h(n), and high pass, g(n), filter impulse responses. h(n) and g(n) arequadrature mirror filters, (see Fig.2.4.2.1), corresponding to the type of wavelet used [1].In the present work, the sparsifying basis which has been proposed for futures systemimprovements is the one based on Daubechies wavelets. Two important points have to beconsidered in order to create the WL basis: a) The number of samples and measurements arerecommended to be multiple of two, in order to construct a sparsifying basis whose coefficientspropagation (see Fig.2.4.2.1) perfectly fit with these dimensions; b) the number of WLcoefficients has to be selected regarding to the number of samples of the input signal, in anycase the sparsifying basis can be less sparse than the input signal; and c) in the operationshows in Fig.2.4.1.1, the basis has to be the inverse transformation, in order to respect.2.5. Reconstruction MethodsCompressed signals can subsequently be recovered by using a greedy algorithm or a linearprogram that determines the sparsest representation consistent with the acquiredmeasurements. The quality of the reconstruction depends on: a) compressibility of the signal; b)choice of the reconstruction algorithm; and c) incoherence between the measurement matrixand the sparsifying basis.35

Figure 2.5.1. l 1-minimization approaches to l 0-minimization approach.Candès, Tao, Romberg and Donoho have formalized the CS view of the world [26] by statingthat under certain assumptions there is a correspondence between the solution which isobtained from the l 0 -minimizer and the l 1 -minimizer (see Fig.2.5.1). This finding is relevant dueto the fact that a l 1 -minimization is a linear programming problem which can be solved byefficient computer algorithms, unlike the l 0 -minimization which is a NP-hard problem (Nondeterministicpolynomial time). Keeping this point in mind, it can be stated that randommeasurement matrices serve a double purpose: a) providing the easiest set of circumstancesunder which l 1 -minimization is provably equivalent to l 0 -minimization; and b) ensuring that theset of measurements vectors are as dissimilar to the sparsifying basis as possible. When it isgiven a random measurement of a sparse signal, , it generates a subspace of possible signals(green) that could have produced such a measurement. Within that subspace, the vector withsmallest l 1 -norm, is usually equal to [26].The strictest measure of sparsity is the l 0 -norm of the signal defined as the number of non-zerocoefficients of the signal. Unfortunately, the l 0 -norm is combinatorially complex to optimize andso CS enforces sparsity by minimizing the l 1 -norm of the reconstructed signal, which has beenprobed as an equivalent solution. Thereby, the minimization problem is summarized in theexpression:(7)A very important issue is that any real world sensor is subject to at least a small amount ofnoise, so in the cases in which this error margin can be approximated, it is recommendable tomodify the recovery algorithm in order to make the method stable and widely applicable,because small perturbations in the observed data should induce small perturbations in thereconstructed signal. So the expression above can be adapted by including an error ε andmaking consistent the reconstruction with the noise level:(8)36

It is worth mentioning that compressible signals are more realistic to consider than sparsesignals, and under this condition even the l 0 -minimizer does not match the signal exactly, sothere is no hope for the l 1 -minimizer to be correct.Mathematicians have developed new faster algorithms to solve the l 1 -minimization problem. Inthe [30] the main recovery algorithms are available to be downloaded.3. ECoG and AP Compressive Sensing System Design3.1. Power Consumption AnalysisIn Appendix B, two models with an analog and digital approach to be applied over a similarneural acquisition system are included. This comparison has been presented in [3], and it canbe considered the most significant example of power analysis of both, analog and digitalapproach, to the CS problem for neural signals compression in the limited existing literature.Due to this fact, this has been taken as the main reference to study the power consumption of amultichannel acquisition system and figure out which are the blocks susceptible to me improvein terms of power saving. As the bound of this project is to achieve a novelty in the analog pathimplementation for a CS system, the power analysis is focussed in the calculation considered inthe analog implementation shown in Appendix B. These equations has been inferred by takinginto account that as we are integrating over N samples, the instantaneous voltage on theintegrator can be expected to grow by an average factor of √N and cannot be allowed to exceedthe available maximum differential ADC input range. This condition can be summarized in Eq.9:(9)By applying this condition, the resulting power gain becomes NG 2 A instead of G 2 A . However,contrary to what is stated in [3], as sparse signals are integrated, the growth factor of √N is anoverestimation of how the integrated signal can increase, and consequently the total gain canbe approximated depending on the output noise at the output of the integrator and the total ADCquantization noise which can be allowed in the path. That is expressed in Eq. 10:(10)By substituting this condition in the total power consumption estimation for a complete analogpath:(11)37

If calculations in Appendix B (Eq.25) are compared with Eq.11, it is clear that the total powerconsumption for an analog path does not fit anymore with the relation which has been depictedin Fig.B.2.2.2, and hence, it has been probed that a power consumption saving can be carriedout for an analog implementation of the CS based path for neural signals acquisition bymodifying the known architecture of the system and applying the limiting conditions which arespecific for sparse signals.3.2. Single and Multi Channel ApproachBy keeping in mind the analysis has been presented in 3.1, a new block diagram sketch for aCS analog path can be considered to be implemented. The proposed system is shown inFig.3.2.1. In order to reduce the power spending, one front-end LNA can be considered, and sothe input signal is copied in each of the paths of a channel to be mixed and integrated. Similarly,one ADC can be used by previously multiplexing the compressed signal components of each ofthe paths. It has to be considered the data rate in each of the blocks. At the sensor, the inputsignal is sampled at Nyquist rate, so if the acquisition system is focussed in ECoG signals,which have a bandwidth of approximately 10 kHz (see Table 2.1.1), a minimal samplingfrequency, f s , of 20 kHz has to be taken into consideration. After compression, the data rate ineach of the paths becomes f s /N, and it has to be forwarded to the ADC without a data loss,because of which the multiplexer and the ADC have to be designed to work at a rate of M timesf s /N.Figure 3.4.1. Analog implementation proposal for neural acquisition channel.Depending on the number of input samples, N, which are considered in each integration periodand the compression ratio is wanted to be exploit to maintain as high as possible the SNR of thereconstructed signal after the recovery processing, the number of channels, M, is integrated onchip varies. In the same way, area and power constraints are determinant to adjust this relation.In this point, two main milestones have to be established to carry out the circuitry model isincluded in Fig. 3.2.1: a) ultra low power blocks have to be employed in order to keep thesystem under reasonable power spending levels; b) ultra compact blocks have to be designed,38

y specially considering the integration capacitances which are necessary in each of the paths,and which widely increase the total area of a channel, which in composed of M paths.Depending on the capacitances of the integrators, which can be large to correctly implement theintegration at these frequencies, the complete channel could be implemented o n chip in asaving area way. In Chapter 6, it is submitted the new proposal for the mixer-integrator pair ofeach of the paths.4. Random Matrix GenerationAlong the previous chapters, the necessity of a measurement matrix as much incoherent aspossible with respecting to the sparsifying basis has been shown. Different kinds ofimplementations of the random matrix have been considered in [1, 3, 21, 22, 34, 35, 36]. A newrandom matrix implementation has been researched in order to determine which is the lowestpower cost, less area consuming approach and overall the one which leads to the largestnumber of parallelized outputs, which, as it is introduced in 4.2.2.3, is an interesting capability tobe applied in multichannel signal acquisition implementations.Main approaches to the obtaining of random sequences generation are the True RandomNumber Generation, (TRNG), based on analog domain, and the Pseudorandom BinaryGeneration, (PRBS), and mostly based on digital domain. Analog random generation is includedin Appendix C, regarding to digital implementation, it is included below.4.1. Digital Implementation: Pseudo Random Binary SequencePseudorandom Random Binary Sequence circuits (PRBS) perform an alternative architecturewhich sacrifices true randomness generation for simplicity in the implementation, giving rise tomore feasible design which has a known period of randomness, after which the same sequenceis repeated. In any case if the random sequence is long enough not to be repeated during thecircuits operation, this procedure constitutes an optimal solution. Henceforward during thischapter, main properties of PRBS as well as methodologies of functioning are discussed.4.1.1. Basics of PRB: Serial and Parallel ImplementationConventional PRBS are based in Linear Feedback Shift Registers (LFSR), which consist of asequence of DFF which are connected is in series or in parallel by using XOR gates. Theposition of the XOR gates, which are called taps of the LFSR, varies depending of the length ofthe random sequence to be achieved.39

By means of the serial implementation, a random N-bits sequence is developed by getting oneby one the bits at the output each clock cycle. In the case of the parallel configuration, the XORoperation becomes more complex, but each time there are m random bits at the output, where, relying on the chosen parallel architecture. Thereby the choice of the architecture willdepend on the time, area and power constraints of the system, in the case in which areasupposes a critical feature, parallel implementation is discouraged because more DFF areneeded in the block; on the other hand if the system strictly needs k random bits each clockcycle, a parallel LSFR can be implemented. Similarly, in order to face the design of a serial orparallel LSFR, but more necessarily in the latter, an aim of the design will be decreasing thepower consumption as much as possible by using ultra-low power consuming Flip-Flops.Furthermore, the number of DFFs, k, which are needed to implement a detailed length of bitssequence, N, is related in correspondence with the random sequence period shown in Eq.13,this relation is the time-period of the Maximum Length Sequence, (MLS). An important thing tonote is that all XOR tapping configurations do not lead to MLS but to get these MLS of period 2 k– 1, a primitive polynomial h(x) of degree k is required. The algebraic terms occurring in thispolynomial represent the LFSR tapping positions for MLS. A primitive polynomial is anirreducible polynomial of that degree. For example, for the serial LFSR of the Fig.4.2.1.2 theprimitive polynomial is:(12)Changes in the polynomial lead to change in the occurring output sequence. After N bits, thesequence will repeat itself, and so, this must be taken into consideration in order to avoidcorrelations in or between the different signals which are being modified by the randomsequence.(13)In the case of serial implementation, N bits will be achieved at the output of the signal after Nclock periods. For the other hand, in parallel implementation, each clock period, m bits willpropagate across the k outputs each clock period. In Fig. 4.1.1.1 there have been included anexample of a parallel (top) and serial (bottom) LFSR configurations with k = 5, both of thembased on five DFFs. It can be observed that the parallel one is implemented by using five DFFsand four XORs, in addition to the circuitry related with connections, port and clock setting. Theserial architecture is more compact, because it is implemented with five DFFs and one XOR,plus extra circuitry.40

Figure 4.1.1.1. LSFR parallel (top) and serial (bottom) architectures based on five DFFs design.Figure 4.1.1.2. Galois (top) and Fibonacci (bottom) configurations for a k = 16 LFSR.In the case of serial LFSR, here are two types of architectures, Fibonacci and Galois, the latterhas been chosen to implement the PRBS because the concatenation of the gates gives raise toone DFF in the critical path, and so less execution speed is needed. A comparison for k = 16DFFs is included in Fig.4.1.1.2, Galois (top) and Fibonacci (bottom). It can be observed that inthis case taps are in positions 16, 14, 13 and 1. As previously it has been stated, for an k-bitsLFRS, the maximum possible outcome can be – bit-vectors or states because a state withbit-vector containing all ‘0’s will keep repeating itself not allowing any other state to occur (allXOR outputs will always be ‘0’). Measurement matrix generation has to be carry though bywarranting that all its rows are uncorrelated between each others. Thereby, incoherencebetween basis and measurement matrix is insured and the CS recovery can be implemented.On the other hand, in many applications, as the ones based on Random Convolution, (RC) [21],it is a target simultaneously obtaining several random coefficients in order to carry out thecompression. By taking into account these requirements, random generation block becomes acritical design issue, and its study has to be carefully determined in other to realize a compactand efficient compression in CS systems on-chip.41

4.1.2. Flip-Flops: Power and Area AnalysisIn order to implement the less power consuming PRBS, several Flip-Flops implementation havebeen compared taking into consideration few transistors and low power consumption. Flip-Flopsthat have been considered are included in Fig. 4.1.2.1 and Fig.4.1.2.2.The power analysis has been carried out by considering each of the Flip-Flops supplied by 1.2V and at a clock frequency of 50 kHz. The CMOS technology has been used is UMC 0.18μm,by considering the width of PMOS as 2μm and the width of NMOS as 1μm. For the Flip-Flop inFig.4.1.2.1, the power consumption in the conditions specified above has been 7.2 nW, and forthe TSPC FF has been 2.4 pW. Such a difference is caused by the fact the Reset-based FF hasmore than the double of transistors, what, by the other hand also results in more areaconsumption. However, as it is shown in 1, the random generation consumption is negligible incomparison to the analog-digital conversion or the transmission parts for a CS-based system,co although it has to be efficiently designed in terms of power and area, it is not the mostlimiting block of these kind of architectures.Figure 4.1.2.1. Reset-based Flip-Flop.Figure 4.1.2.2 TSPC Flip.Flop.42

4.1.3. Serial Implementation with two PRBSIn [3] the measurement matrix generation has been carried out by using the combination ofPRBS generators, one of them with 50 Flip-Flops and the other one with 15 Flip-Flops. As it canbe observed in Fig.4.1.3.1, the top block generates 50 different outputs, each of them comingput from a Flip-Flop.The bottom block is settled as one output serial PRBS with randomness period of 2 15 – 1. Inorder to achieve 50 outputs in each clock cycle by keeping uncorrelated each of the 50 bitssequences,the bottom PRBS mixes each of the outputs from the top PRBS by XORing itscurrent output value by all their outputs. In this way, it is possible to accomplish 2 15 – 1 randomsequences which maintain no correlation between each others.Figure 4.1.3.1.Random Generator [3].By keeping this idea in mind [3], a new random matrix generator based on two PRBS has beenachieved in order to generate multiple sequences outputs. As it is depicted above, this design ismuch compact than the parallel one, and simultaneous outputs are achieved by cleverlycrossing the states of the two PRBSs by XORing them. A sketch of how is executed theoperation is included in Fig. 4.1.3.2. In this case, a 4FF-PRBS and a 5FF-PRBS have beencombined in order to achieve 16 parallel outputs [31].For the case of a 16 outputs serial Implementation with two PRBS, the crosses have beenconsidered are shown in Appendix D. Each PRBS is created by an LFSR, so the ‘0’ or ‘1’ valuescirculate sequentially from a FF to the next one without changing till a tap is reached. In order toavoid the same state to propagate in successive clock periods, crosses have been chosen inorder to obtain 16 outputs follow the following criteria: a) the first FF of 4FF-PRBS is XORedwith the four last FFs of 5FF-PRBS, (four outputs are achieved); b) the last FF of 4FF-PRBS isXORed with the four last FFs of 5FF-PRBS, (four outputs are achieved); c) The first FF of 5F-PRBS is XORed with the four first FFs of the 4FF-PRBS, (four outputs are achieved); d) look forfour more outputs by taking into consideration outputs which have not been previously mixed43

and interleave these outputs with the others in order to maintain the largest distance betweenthe FFs which are involved, for instance, that means not considered as successive outputs bit 3in 4FF-PRBS and bit 1 in 5FF-PRBS for the output i, and bit 4 in 4FF-PRBS and bit 2 in 5FF-PRBS for the output i + 1, because this choice introduced correlation in that fragment of randomsequence.Figure 4.1.3.2. Serial Implementation with two PRBS (4-FF and 5-FF) to obtain 16 outputs.In 4.1.3 it is studied the randomness of this model, because, as the XORing crossing has beenexploited as much as possible to maximize the number of outputs per pair of PRBScombination, the model shows fragments in some of the states are shifted versions of previousstates. In spite of the partial correlation which exist between successive outputs of the mixedrandom generator, regarding how the random values are provided to the measurement matrixand by considering that each of the outputs of this matrix generator block supplies a column ofthe measurement matrix at each integration period (see Fig. 4.1.3.3), the correlation betweenthe generated sequences in this design does not affect the performance of the reconstructionbecause the similarity periods do not occur simultaneously and they are shifted in time. ThisPRBS has been implemented for different dimensions of the measurement matrix in Cadenceand it is considered in the CS operation along the next chapters.44Figure 4.2.3.3. Random states propagation by columns to the measurement matrix.

4.1.4. Randomness CheckingIn order to ensure that random sequences generation which has been achieved with the newserial-parallel model explain in 4.1.3 is truly random, some simple test have been have beensettled up. The first of them has been to calculate the cross-correlation between the rows of themeasurement matrix in order to evaluate if the outcome is similar to the one which results bychecking the cross-correlation between two random binary sequences create by the availablefunction randint of Matlab.In the same way, if the complete matrix is taken into consideration in an unique sequence, andit is researched by applying a Power Spectra Density (PSD) analysis, if there are binary patternswhich are regularly repeated in the complete sequence.Lastly, the Matlab random benchmark based on the function runstest has been exploited andcompares with the results which are acquired for the case of random sequences created by thepreciously exposed randint function of Matlab. The function runstest performs a runs test on thesequence of observations in the vector x. This is a test of the null hypothesis that the values in xcome in random order, against the alternative that they do not. The test is based on the numberof runs of consecutive values above or below the mean of x. Too few runs indicate a tendencyfor high and low values to cluster. Too many runs indicate a tendency for high and low values toalternate. The test returns the logical value h = 1 if it rejects the null hypothesis at the 5%significance level, and h = 0 if it cannot. The test treats NaN values in x as missing values, andignores them. Thereby if most of h coefficients zero, that state that the vector shows a randomorder.Nonetheless, the three previous common analyses could not to shed light in all cases. Lookingfor randomness is a awkward task because of the fact that as random sequences areconsidered, it is possible that some patterns could be recognised as determinist even when ithas derived from a true random generation, and so the test has to be intended in order to avoidas much as possible fake non-randomness. At this point, the most clarifying test to check if therandom matrix that has been modelled fulfils the required randomness is to introduce it in a CSsystem and observe the reconstruction which is accomplished as it has been done in [31].45

5. System Level DesignCompressive Sensing is a novel compression method, and as it is discussed in the firstchapters, there are just few implementations oriented to wireless on-chip neural acquisition.Regarding to this, the assumptions have to be taken into consideration to develop a completemultichannel system are still in an early phase. As it has been introduced in Chapter 3, one ofthe main purposes of this thesis is to deepen into on the strengths and weaknesses of ananalog implementation in order to clarify if area, power consumption and reliability arecompetitive with the digital implementations, which are a more common approach in biosignalbasedapplications. From this starting point, the main parameters which have been assumed forthe Matlab and Cadence design are summarized in Table 5.1:ParameterSpecificationSamples (N) 128Measurement (M) 64Compression Ratio (C R ) 2Neural signalECoG and/or APBandwidth (BW)10 – 12 kHzMixing Frequency (f s )30 kHzTable 5.1. Main parameters of the CS analog design.The samples and measurement have been chosen regarding the existing literature, by takinginto account that the best reconstruction phase goes beyond the margins of this thesis. Both ofthese parameters are multiple of two in order to easily apply the projection over a sparsifyingbasis without loss of coefficients in the specification of the bank of filters which supports thisdomain. The initial aim of the array of electrodes which is related with the acquisitionmultichannel system of this work is the recovery of ECoG and AP signals from epilepsy patients,in order to specify which is the brain area involved with the characteristic seizures theseindividuals sustain. As it has been presented in Table 2.1.1, ECoG and AP signals have abandwidth about 10 kHz, and so the sampling/mixing frequency has to satisfy the Nyquist-Shannon theorem, so a frequency of 30 kHz fits with the sampling requirements of the interestsignals.5.1. Matlab and Simulink ModelsA CS model has been implemented in Simulink in order to simulate the blocks behaviour of theamplification, mixing and integration of the neural signal as it is shown in Fig.3.4.1. Parameterswhich have been integrated in the model are those contained in Table 2.1.1. Every path has47

een designed independently as it is represented in Fig.5.1.1, it is clearly observed that thematrix multiplication has been implemented by considering a mixer to multiply the interestsignals between each other, and an integrator to carry out the usual addition between theelements that have been just mixed. Each path has two inputs, one is the neural input signal tobe compressed and the other one is the row of the actual path which is multiplied by the inputas it would be calculated in the row-wise column matrix multiplication.Figure 5.1.1. Simulink implementation of a path.The input signal has been created by applying the Matlab function. In the same way,measurement matrices which have been considered and compared are both, the one which hasbeen referred in Chapter 4 as result of the novel PRBSs composition, as well as the one thathas been created by applying the Matlab function randint. The model has been designed tocharge the inputs from mat-files which have to be stored in the current Matlab Workspace.Figure 5.1.2. Details of the CS operation blocks for a path.The integration period which has been considered for each of the samples is the inverse of thesampling frequency, T = 32μs, thus each block of the model has to be synchronized to that timeperiod. The discrete integrator has been included as accumulator by considering the backwardEuler calculation available in the properties of the block. The discrete integrator which has beenused is included in Fig.5.1.2.48

In this way the multipath combination for a channel can be easily integrated according to thenumber of measurements in a scalable way, M. In order to check the correctness of the resultsoffered by the Simulink model, a Matlab ad hoc function has been implemented. Thecomparison between the compressed signals which is obtained by both of the ways is includedin Fig.5.1.3. It has to be clarified that the front-end amplification has been directly applied bymultiplied the input signal by an amplification factor of 10000. In the same way, the multiplexingand AD conversion operation have not been included in the Matlab-Simulink design.Figure 5.1.3. Compressed signal comparison.Figure 5.1.4. LASSO method reconstruction comparison.The difference between the Matlab and the Simulink models is due to a sampling frequencyoffset. In Matlab calculations, the CS operation is accomplished by an exact row-wisemultiplication, however, in Simulink implementation, the operation depends on the sampling49

time, which has been approximated as 33 μs, which is not exactly the inverse of the samplingfrequency. In any case, below reconstruction is shown, and it is probed that both of thecompressed signals give rise a good approximation to the same recovered signal.The reconstruction methods that have been considered are the Basic Pursuit Denoising (BPD)method withand the Least Absolute Shrinkage and Selection Operator (LASSO)method with , provided by SPGL1 [30]. They are well-defined in 5.3. The result of therecovered signal can be observed in Fig.5.1.4 and Fig.5.1.5.Figure 5.1.5. BPDN method reconstruction comparison.5.2. Multi-Channel Implementation of Compressive SensingDuring the study of the CS applications directly related with the initial purpose of the project, thescope of CS systems which are involved with sparse signals in time or frequency has spread toa new applicability which can be defined as Spatial Compressive Sensing, SCS. The resultsderiving from this approach has been submitted as publication in August 2012. Keeping in mindthe huge amount of data which are recorded in neural arrays and the need to compress it, thesmall area and high integration of the electrodes let a high resolution of the brain zone undersignal acquisition, what implies that electrical impulses can be recorded in almost a singleneuron.Due to the sparse nature of the spikes which are registered, when a group of neurons is active,the surrounding groups will be inactive till the stimulus propagates with certain latency. Thisusual scenery gives rise to some electrodes which are catching spikes and many others whichare inactive, so, it is clear to see, that it does exist a spatial sparsity, because at sampling50

frequency when all the electrodes are scanned, solely a few of them will detect a spike. If atsampling frequency it is created a vector containing what each of the electrodes captures in thatclock cycle, that vector most probably will be sparse as well, and so it can be compressed byapplying CS. By repeating this operation during all the acquisition time (N samples), N vectorswill be composed, each of them with M measurements. In Fig.5.2.1 it is sketched the SCSconception for the first clock time multielectrode acquisition, which leads to a spatially collectedsparse signal. When acquisition time is completed, original signals can be reconstructed byreversing the operation during the off-line signal processing.Figure 5.2.1. Spatial CS example. The composition of the first sample of all of the electrodes gives rise toa sparse signal.If spatial sparsity is guaranteed, several benefits arise from SCS, without applying thresholdingor signal-dependent pre-processing neural signals can be recovered by achieving a largerCompression Ratio, because signals of length N can be recovered by M measurements, thelatter one depending on the number of electrodes of the array. Similarly, the new compactrandom generator which is included in Chapter 4 can be used without eventual drawbacks ofcorrelation between paths, because each of the samples of a signal is involved in a different CSspatial operation.As in 5.1., the reconstruction methods which have been considered in order to test this new CSapproach have been the ones based on SPGL1 [30], (see 5.3). In Fig.5.2.2 it can be observedthe original and reconstructed signals in 10 ms for two sample channels using MATLAB andcircuit simulations, which has been included in [31].51

Figure 5.2.2. Original and reconstructed signal by applying SCS.5.3. Reconstruction Method ApplicationAs it is included in 2.4, nowadays there is an intense research in achieving the fastest and moreefficient algorithms to solve the undetermined systems of equations which derive from CSoperations. The study and comparison of this large literature has slightly been under the scopeof this project, and as it has been presented previously, two of these methods have beenchosen to carry out the recovery: a) BPDM and LASSO [30]. They are described in 5.3.1.5.3.1. Basis Pursuit Denoising Method (BPDM)The Matlab code developed in [30] was designed to solve the convergence problem myminimizing the Eq.14.(14)Where A is the M x N measurements matrix, y is the compressed vector and σ is a nonnegativescalar which represents the noise margin. If σ is zero, then the Basis Pursuit Method(BPM) is solved, being the only constraint Ax = y.52

5.3.2. Least Absolute Shrinkage and Selection Operator (LASSO)The Matlab code [30] solves the convergence problem my minimizing the Eq.15.(15)Where A is the M x N measurements matrix, y is the compressed vector and τ is a non-negativescalar which represents the input signal margins.53

6. Analog Path Design6.1. Design DiscussionThe multipath neural acquisition system for a channel that is shown in Fig.3.4.1 has beenchosen as the implementation to be developed. It is included again below as reference duringthe design discussion. Having a look of the complete design it is clear that the complexity ofimplementing all of the blocks overcomes the scope of a final master thesis, and so, in order tointroduce design improvements, the design has had to be limited to some blocks, putting off thetotal implementation for future steps in the CS field.As it is commented in the Chapter 1 and 2, the main constraints of the system are: a) area, dueto the act that the chip to be placed over individuals brain has to be as smaller as possible, andso less invasive; and b) power consumption, because of the fact that a large battery cannot beincluded in the system, and overall safety issues, because low power consumption means lowheat dissipation and so the chip will be permitted as bioapplication. By the other hand, thesystem is not conditioned by time constraints, so any extra effort is employed in order to make ahigh-speed design. That is since real neural signals have a low bandwidth, and so there is noreason into exploit high-speed features which will be not used.By considering the main blocks of the system, and the design problems with which each of themis related, it is stated that the LNA, the ADC and the multiplexer boil over the time limitations,and so, previous designs are considered. By the other hand, a good design of howimplementing the mixing and integration blocks have not been already done in the state of theart, and so, it has been considered as the best feasible design to be completed under thescenario of this project. The main goal for being considered in the improvement is area savingin order to achieve an architecture in which the miniaturization of the integration capacitances,which regarding the literature are too large components of the integrator circuitry, could be carryout. Along the next points the different blocks of the multipath analog approach are analyzed indetails.A discussion about the amplification and conversion operations has been included in AppendixE. In order to address the mixer-integrator design, the same parameters which have beenconsidered during the Matlab and Simulink models are taken for the circuitry design inCadence. They are referred in Table 5.1. The same synthetic input signal that has been usedfor Matlab-Simulink simulations has been introduced into Cadence model. Similarly, the randommatrices which have been considered are those based on the new random generator presentedin Chapter 4 and the one which can be generated by randint in Matlab.54

6.2. Mixing and IntegrationFirst of all, the purposes of the re-design of the mixing and integration blocks are: a) reducingarea and b) implementing together the mixer and the integrator, and not integrating as differentblocks. In order to study which are the limitations in performance and the eventual problemsthat have to be faced in the mixer-integrator design, several known models have beenimplemented and checked within a multipath channel in Cadence, by taking into considerationdifferent configurations for the integrator: passive, active and switched capacitors-based one.These topologies are introduced below by using the technology TSMC018.6.2.1. Passive IntegrationA passive integrator is a simple four-terminal network consisting of two passive elements, aresistor and a capacitor as it is included in Fig.6.2.1.2. For each of the paths, integration iscarried out and the final integration value is obtained with a scale factor which depends on RCand the integration time. Thereby, the final output result accumulated in the integrator of eachpath is obtained as:(16)Where is the integration interval, which corresponds to the inverse of the samplingfrequency, and so it is . The circuit in Fig.6.2.1.1 acts as a Low Pass Filter (LPF) forfrequencies which are under the pole frequency, f p , which defined as (see Eq.17).Figure 6.5.1.1. Mixer and passive integrator circuitry.The circuit performs as integrator for input signals whose frequency is over f p because of thefact that the constant of time of the integrator has to be larger than the period of the signal.According to this, the integrator has to be designed in order to fix the pole frequency below thefrequencies of interest that have to be integrated.(17)55

The spectra of the input signal have been depicted in Cadence, (see Fig. 6.2.1.2) and it can beobserved that most of the information in frequency is approximately in the range between 300Hz and 12 kHz. In this way, the values for R and C has to verify Eq.17 for a frequency polewhich has been chosen f p = 100 Hz. The main parameters of the simulation are shown in Table6.2.1.1:ParameterPole frequency (f p )Sampling frequency (f s )Integration period (Δt)Signal BandwidthRCSpecification100 Hz33 kHz32μs12 kHz1.59 GΩ1 pFTable 6.2.1.1. Main parameters for the simulation of the Passive Integrator-based multipath channel.Figure 6.2.1.2. Input signal Spectra.As it has been commented previously, the mixing has to be included within the integrator,hence, it can be implemented by considering a switch which in controlled by the random binarysequence which comes from the random generator. In this way, when the actual value of therandom sequence is ‘1’, the switch is close and so the value which is being registered in theelectrode passes across the resistor and accumulates in the integrator capacitor. The56

considered switch is almost ideal, that is, the close circuit resistance is 1 Ω and the open circuitresistance is 1 TΩ. The control voltages have been chosen as underfor closingthe switch, and overto close it. In this way the uncertain range of control voltageis minimize, but anyway the random binary sequence does not distort. The mixer-integrator hasbeen sketched in Fig.6.2.1.1. A complete multipath acquisition array has been implemented inCadence by considering N = 128 and M = 64. The resulting compressed signal has beencompared in Fig.6.2.1.3 with the one which has resulted in Matlab implementation.As the reconstructed signal is robust in both of the models, the differences regarding thesamples of the compressed signal have to be caused by non-idealities during the sampling andintegrating phases. The compressed signal coming from Cadence is slightly different to the onewhich has been calculated in Matlab, so the reconstruction signal for both of the models iscompared in Fig.6.2.1.4 for LASSO reconstruction method and in Fig.6.2.1.5 for BPDM. InLASSO-based reconstruction (see Eq.15) and in BPDN-based reconstruction(see Eq.14). Both of the values have been chosen as those which have led a better SNRbetween the original signal and the reconstructed one. Hereafter reconstructed signals areincluded for each topology, a comparison between all of them is introduced at 6.2.5 and SNRcomparison is included in 6.2.6.Figure 6.2.1.3. Compressed signals comparison.It is clear that this topology cannot be used for CS purposes on-chip, because in order toincrease the signal swing it is necessary to increase the RC ratio, and so, it becomes a noimplementable design due to area constraints.57

Figure 6.2.1.4. LASSO reconstruction comparison.Figure 6.2.1.5. BPDN method reconstruction comparison.6.2.2. Ideal Active Inverting IntegrationThe next topology which has been faced in the step by step approximation to the bestimplementation of the mixer-integrator is the one based on the ideal active inverting integratorwhich is shown in Fig.6.2.2.1. As it is depicted, it has been considered the same mixing byswitching than in 6.2.1.58

Figure 6.2.2.1. Mixer and ideal active inverting integrator circuitry.The integration operation is shown in Eq.18:(18)In this way, the final integration value has to be multiplied by a scale which depends once againon RC and the integration time Δt, in this case in inverting configuration (see Eq. 16). On theother hand, the final integration value depends as well on the gain on the ideal amplifier hasbeen used, which is included in Fig.6.2.2.2. In order to evaluate which is the gain furnished bythis configuration by considering that the system works within integration frequency range, anaveraged gain has been calculated by comparing the Matlab output achieved and the Cadenceoutput has been obtained for each of the cases based on an amplifier. The other simulationparameters have been included in Table 6.2.1.1.Figure 6.2.2.2. Ideal amplifier.A complete multipath acquisition array has been implemented in Cadence by considering N =128 and M = 64. The resulting compressed signal has been compared in Fig.6.2.2.3 with theones presented in 6.2.1.59

Figure 6.2.2.3. Compressed signals comparison.In the same way, in Fig.6.2.2.4 and Fig.6.2.2.5 LASSO-based ( ) and BPDN-based( ) signal recovery have been respectively sketched and compared for 6.2.1 and 6.2.2cases.Figure 6.2.2.4. LASSO reconstruction comparison.60

Figure 6.2.2.5. BPDN method reconstruction comparison.6.2.3. DC-Offset Controlled Active IntegrationAt zero frequency, the capacitor in Fig.6.2.2.1 is an open circuit and the amplifier in theintegrator loses feedback. For non-ideal amplifiers this can cause undesirable DC offset at theoutput. To provide a DC feedback at DC, a resistor can be used in parallel with C as shown inFig.6.2.3.1.Figure 6.2.3.1. Modified active integrator.At low frequencies, where C is an open circuit, the magnitude of the voltage gain is limited bythe value, and so the transfer function for the voltage gain of the integrator is given by:(19)61

In this way, the pole frequency is at and the frequency at 0dB-gain is .By taking into consideration that the bandwidth of the input signal is about 12 kHz, the pole hasbeen accounted at 100 Hz, as in 6.2.2, and the 0-dB frequency has been considered at 20 kHz,far enough from the bandwidth limit in order not to filter out any frequency component ofinterest. The other simulation parameters have been included in Table 6.2.1.1 and inFig.6.2.2.2. In order to estimate the scale factor which is applied over the final integration valuesimilarly as it is introduced in Eq.16, Eq.19 can be expressed in time domain as:(20)Figure 6.2.3.2. Compressed signal comparison.In this way, the scale has to be considered in each integration time, depends on –R 2 C and thegain which is applied in the integration frequency range, which has been calculated as in 6.2.1.A complete multipath acquisition array has been implemented in Cadence by considering N =128 and M = 64. The resulting compressed signal has been compared in Fig.6.2.3.2 with theones presented in 6.2.1. In Fig. 6.2.3.3 and Fig.6.2.3.4, reconstructions which have beenaccomplished are shown for all the compared topologies seen above for and .62

Figure 6.2.3.3. LASSO method reconstruction comparison.Figure 6.2.3.4. BPDN method reconstruction comparison.6.2.4. Switched-Capacitor Integrator with parasitic effectsIn order to reduce the area derived of the resistor, this is replaced by a Switched-Capacitorresistor as the one which is delighted in Fig.6.2.4.1. The capacitor, C, which has been includedin parallel after the mixing switch, has been considered during the simulations in order to avoidthat node63

A can be floating when the mixing switch and the Φ 1 -controlled switch are closed. Its value canbe chosen really small by considering the relation below:(20)Figure 6.2.4.1. Switched-Capacitor Integrator with parasitic effect.By considering Eq.22, the integration operation is modified as shown in Eq.21:(21)Similarly, the fundamental frequency relation is modified to:(22)By taking into consideration Eq.20 and Eq.22, C 1 and C 2 can be defined as is shown in Table6.2.4.1.ParameterSampling frequency (f s )Switching frequency (f switch )Integration period (Δt)Signal BandwidthC 1C 2CRSpecification33 kHz200 kHz32μs12 kHz1 pF960 fF1 fF5 MΩTable 6.2.4.1. Main parameters for the simulation of the SC Integrator-based multipath channel.In practice, the SC inverting amplifier of Fig.6.2.4.1 is influenced by the parasitic capacitors dueto the bottom and top plate of the desired capacitor. The bottom plate is shorted out but the topplate parasitic adds directly to the value of C 1 . The parasitic of C 2 does not affect it, this isbecause one of the capacitors (i.e. the bottom plate) is in shunt with the amplifier input, which is64

a virtual ground. The top plate capacitor is in shunt with the output of the amplifier and onlyserves as a capacitive load for it. In 6.2.5 it is introduced SC circuits which have beendeveloped to be insensitive to the capacitor parasitic. A complete multipath acquisition arrayhas been implemented in Cadence by considering N = 128 and M = 64. The resultingcompressed signal has been compared in Fig.6.2.4.2. In Fig.6.2.4.3 and Fig.6.2.4.4 theresulting LASSO and BPDN reconstructions are respectively included. In this case the scalefactor has been considered as in 6.2.2, but taking into account the equivalent resistor shown inEq.20.Figure 6.2.4.2. Compressed signal comparison.Figure 6.2.4.3. LASSO method reconstruction comparison.65

Figure 6.2.4.4. BPDN method reconstruction comparison.6.2.5. Non inverting Switched-Capacitor Integrator without parasitic effects [32]At it is described in 6.2.4, in the circuit shown in Fig.6.2.4.1 parasitic effects are present due tonon-idealities in the capacitors due to the top and bottom plates which add additional capacitorsto the system. One way to avoid these non-idealities is to consider the topology shown inFig.6.2.5.1.Figure 6.2.5.1. Switched-Capacitor Integrator without parasitic effects.The parameters choice has been done by taking into consideration the same relations whichhave been introduce in Table 6.2.4.1.The results concerning compressed signal and inputreconstruction are shown below for and . In this case the scale factor hasbeen considered as in 6.2.2, but taking into account the equivalent resistor shown in Eq.20 anda non-inverting architecture.66

Figure 6.2.5.1. Compressed signal comparison.Figure 6.2.5.2. LASSO method reconstruction comparison.67

Figure 6.2.5.3. BPDN method reconstruction comparison.In Fig.6.2.5.2 and Fig.6.2.5.3 input reconstruction is shown for all the ideal cases have beentested. It is clearly observable that the best recovery for the full energy range has beenachieved by the non-inverting SC Integrator without parasitic effects (in yellow), closely followedby the SC Integrator with parasitic effects. The continuous time configurations, in passive oractive topologies have demonstrated to carry out a worst charge and discharge of the capacitorduring the integration phases, and so the final accumulated values for each of the compressedsamples in each of the paths of the channels move away from the theoretical solution calculatedin Matlab, whereupon the reconstructed signal is more noisy than in discrete time-basedintegrators. This discussion is summarized in 6.2.6 with the SNR analysis.6.2.6. SNR Calculations [32]Signal to Noise Ratio has been calculated by considering Eq. 23:(23)Where is the original input signal and is the reconstructed one. In Table 6.2.6.1 SNRcalculations for each of the ideal topologies which have been presented in 6.5 are summarizedfor both of the recovery methods have been considered, LASSO-based and BPDN-based one.According to the results obtained below, the best topology to be improved is the one presentedin 6.2.5, based on switched capacitors and enhanced not to be sensitive to the parasitic whichare introduced by C 1 . Henceforward, a mixing-integration real topology based on switchedcapacitors is considered.68

Topology LASSO (dB) BPDN (dB)Matlab Code 36.3 36.9Passive Integrator (6.5.1) 9.8 10.4Active Integrator (6.5.2) 7.8 5.6Modified Active Int. (6.5.3) 8.2 3.6SC Int. Parasitic Sensitive (6.5.4) 12.7 14.7SC Int. Parasitic Insensitive(6.5.5)14.1 14.9Table 6.2.6.1. SNR comparison between topologies and reconstruction methods.The primary advantages of SC circuits include: a) compatibility with CMOS technology; b) goodaccuracy of time constants; c) good voltage linearity; d) good temperature characteristics; ande) less area needs. By the other hand, the main disadvantages are a) clock feedthrough; b) therequirement of nonoverlapping clock; and c) the necessity of the bandwidth of the signal beingless than the clock frequency. Beneath, these considerations are taken into account.69

7. Conclusions7.1. RemarksAs it is shown along the previous chapters, this project has been arranged as collaborationbetween LSM-EPFL and IMEC. During the three months in LSM, it has been carried out a deepstudy about Compressive Sensing oriented to the implementation of a system on-chip tocompress neural signals and send it by saving power consumption and heat dissipation in thetransmitter.Due to the fact that Compressive Sensing technique applied to real implementations is in anearly phase, an extensive state of the art has been accomplished in order to be able to specifythe known limitations of the designs based on Compressive Sensing. This study encompassesall the actual trends of design, both in digital and analog domain, and so it is considered a goodstarting point for future related projects. It has been scheduled the circuit implementation of ananalog-liked multi-path/multi-channel compression system, in order to deepen into the feasibilityof this configuration instead of the digital implementation, which is the most used one evenwhen the available power consumption comparison between digital and analog approacheshave revealed not to be enough conclusive to dismiss the latter one.For this purpose, foremost, a complete multichannel implementation has been developed bothin Matlab and Simulink. In order to carry through this task, a neural signal, (AP) has beenconsidered as sparse input. The reconstruction has been accomplished by applying BPDN andLASSO reconstruction methods, for which the mathematical bases of Compressive Sensinghave been studied.In order to implement a parallel and more compact random generator block to implement themeasurements matrix, a new design has been settled up in Cadence 5, by using the technologyUMC 0.18μm, for a variable number of multiple outputs.Under the scope of the regular operation of Compressive Sensing, a new approach to thismethod has been developed by realizing that sparsity conditions are fulfilled in an array ofmultielectrodes. That it, if all the sensors are simultaneously sampled, according to the usualspikes propagation among neurons, just few of these electrodes receive a peak, what results ina spatial sparse signal which can be compressed by Compressive Sensing. This approach hasbeen implemented in Matlab and Cadence, and results have been submitted in the paper [31].During the period in IMEC, in order to implement the mixer and the integrator blocks which areneed in each of the paths (rows) of a channel, a combined design has been implemented inCadence 6, by using the technology TSMC018.In order to achieve a feasible analog implementation, different integrators have been tested.Integrators in continues time domain have been proved not to be an optimal solution due to the71

fact that in order to integrated the neural input signals in a range of frequencies till 10 kHz, thearea needed to implement the resistor and the capacitors is too large to be a design whichcould spread out all over all the paths are needed in all the channels of the chip array. Due tothis, switched capacitor architecture has been deployed. By considering an implementation thatmakes depend the magnitude of the components on a clock frequency, area constraints arerelaxed, so that has revealed as a practicable design to implement an analog design of the CSlikedacquisition system.7.2. Next stepsDuring the accomplishment of this project, Compressive Sensing-based systems has revealedas a promising compression method to be applied in biological signals which satisfy sparsityconditions.As it is shown along the previous chapters, Compressive Sensing systems are becoming moreand more relevant in order to efficiently implement high information rate acquisition circuits.However, it is a new methodology, and many design parameters have not been settled yet, sothe project has turned into the first approximation to an entire CS-platform based on analogimplementation for EPFL and IMEC.After the work which is circumscribed to the scope of the master thesis, a real SC-based mixingand integration path will be implemented in IMEC based on real components. In the same way,LNA and ADC will be integrated along with the mixer, integrator and random generator whichhave been individually designed in order to attain a complete analog path for futuremultichannel implementations.For the other hand, in order to be able to apply this array-based neural acquisition system torecord as many different neural signals as possible, it is recommended to study the bestsparsifying basis for each of the characteristic neural signals. Therefore, neural sciences couldbenefit of clearer recordings in order to better understand the illness which are related with thebrain. Similarly, other reconstruction methods, as [37], could be applied and compare with theones have been used in this work, in order to verify which one gives the best results.Finally, the new CS-application which has been presented [31] has to be deeper studied inorder to specify its better applicability in neural recording.72

AppendixAppendix AConvexOptimizationIterative GreedyAlgorithmsOthersBasis Pursuit (BP)Basis Pursuit De-Noising (BPDN)Conjugate Gradients Pursuit (CGP)Preconditioned Conjugate Gradient Pursuit (PCGP)Matching Pursuit (MP)Orthogonal Matching Pursuit (OMP)Regularised Orthogonal Matching Pursuit (ROMP)Compressive Sampling Matching Pursuit (CoSaMP)Iterative Hard Thresholding (IHT)Iterative Shrinkage/Thresholding (IST)Stagewise Orthogonal Matching Pursuit (StOMP)Stagewise Weak Orthogonal Matching Pursuit (SWOMP)Stagewise Conjugate Gradient Pursuit (StCGP)Weak Conjugate Gradient Pursuit (SWCGP)Stagewise and Reduced Conjugate Gradient (RCG)Subspace Pursuit (SP)Iterative Reweighted l 1 -norm Minimization Algorithm(IRWL1) + Hidden Markov Tree (HMT) modelGradient Projection (GP)Gradient Projection for Sparse Reconstruction (GPSR)Least-Angle Regression (LARS)Least Squares Quadratic Regression (LSQR)Least Absolute Shrinkage and Selection Operator(LASSO)Bound Constrained Quadratic Programming (BCQP)Interior Point (IP)Table A.1. Main Reconstruction Methods.73

Appendix BB.1. Digital ImplementationAn implementation of a hardware-efficient CS architecture in wireless sensors has beenrecently proposed by Chen and Chandrakasan [3]. The CS channel that has been implementedis shown below. As it can be observed, the main issue in this design is that the compressionoperation takes place in the digital domain. The signal is acquired, amplified and forwarded tothe analog-to-digital converter (ADC), after thus, each of the M rows of the random matrix isrow-wise multiplied by the input bits in M different paths, being at the end of each path onecompressed coefficient.Figure B.1.1 Block diagram for a digital implementation of one CS channel.In order to implement the multiplication, a digital mixing and accumulation is carried out alongthe N samples of length of the registered signal. All the operation takes place at Nyquist rate butthe final accumulation of the M compressed values of the signal. The cost of this design hasbeen calculated by taking into consideration the following specifications, (see Table B.1.1):ParameterSpecificationTechnology90 nm CMOSMeasurements (M) 50Samples (N) 500ADC bits (B f ) 8CS signal bits (B y ) 10Bandwidth (BW f )200 HzTotal gain (G A ) >100Table B.1.1. CS model specifications.75

The total power cost for the digital implementation of a multipath CS encoder, without taking intoconsideration the random generation, has been calculated in [3] as:(24)The digital CS channel, including matrix generation and clock consumption, consumes 1.9 μWat 0.6 V for sampling frequencies below 20kS/s. In Fig. B.1.2 is included the power consumptionanalysis regarding to the bandwidth of the input signal as it has been presented in [3]. Byconsidering the power consumption estimation of Eq.24, it is clear that the largest contributionto the power spending is the result of the ADC and the amplifier.Figure B.1.2. Power consumption versus bandwidth for the digital implementation of a CS path.Specifications from Table 3.1.1 have been taken into consideration.B.2. Analog ImplementationB.2.1. Current ModeIn [27], it is presented a current-mode circuit implementation of CS architecture to be used in amultichannel receiver system which is used to digitize at 1.5 GHz the signals of each channel,which are sparse in frequency domain, and spread it over the entire bandwidth. In Fig. B.2.1.1 itis observed the circuit proposal to this application. In the approach of [27], an OperationalTransconductance Amplifier (OTA) and an ADC are considered for each of the paths. It is worthmentioning, that the integrators consist of two time-interleaved branches which provide76

successive integration windows in order to develop a Parallel Segmented CS (PSCS)architecture, which achieves a decreasing in the necessary number of implemented paths perchannel.Figure B.2.1.1. Circuit implementation of the proposed CS receiver.By exploiting signal sparsity, the system accomplishes 44 dB overall SNRD, with a powerconsumption of 120.8 mW. Others critical specifications about the design have been included inTable B.2.1.1.ParameterSpecificationTechnology90 nm CMOSParallel paths 8Chip area (8 paths)1000 μm x 1400 μmBandwidth (BW f )10 MHz - 1.5 GHzTable B.2.1.1. CS model specifications.B.2.2. Voltage ModeIn [3], Chen and Chandrakasan have proposed a voltage mode-based architecture for ananalog channel for a wireless neural CS implementation which has been depicted in Fig.B.2.2.1.The registered signal is amplified by an operational transconductance ampliflier (OTA) in eachof the M paths of the CS operation, and afterwards, the N samples are multiplied by Ncoefficients of the random matrix and accumulated in each of the rows before being sent atcompressed rate to the dedicated ADC which has been included in each of the paths. At theoutput of each of the ADC the final digitized compressed value is acquired. The exploit of oneamplifier per channel widely increase the power consumption as it is shown in the Eq.24. In theChapter 3.3 the necessity of one OTA and ADC per path are deeply discussed in order to clarifythe feasibility of an analog implementation for a neural channel.77

Figure B.2.2.1. Block diagram for an analog implementation of a CS channel for neuralacquisition.The total power cost for the analog implementation of a multipath CS encoder, without takinginto consideration the random generation and the mixers cost, has been calculated in [3] as:(25)Figure B.2.2.2. Power consumption versus bandwidth for the analog implementation of a CSpath. Specifications from Table 3.1.1 have been taken into consideration.Tthe power consumption has been introduced versus the bandwidth of the input signal, (seeFig. B.2.2.2). In this case, regarding to the calculations have been presented above, the largestcontribution to the power consumption is the one due to each of the amplifiers which have beenconsidered as necessary for each of the paths of the matrix multiplication. In 3.1 this78

approximation is discussed by taking into consideration a different block diagram, which hasbeen considered as a better approximation to the analog implementation of a CS path in termsof power saving. In the same way, Chapter 6 a new path design has been considered byexploiting an area saving on chip.B.2.3. Charge ModeAn incremental Sigma-Delta ADC (ΣΔ-ADC), for CS applications has been submitted in [28]. Thenovelty of this implementation is the simultaneity of the acquisition and quantization of CSmeasurements, due to the fact that a Switched Capacitor (SC) integrator of has beenincorporated in the close loop of the converter. The converter occupies a small area of 0.047mm 2 on a target 0.5 μm CMOS process, and it can be suitable for CS applications. A sketch ofthe complete implementation has been depicted in Fig. B.2.3.1.Figure B.2.3.1. Switched Capacitor circuit implementation of the CS ADC.In [1] it has been proposed a binary-weighted SC Multiplying Digital-to-Analog Converter(MDAC) for the processing of ECG and EMG signals. The architecture that is included inFig.B.2.3.2. implements a multiplication between the actual random coefficient and the inputsignal sample during Φ 1 and the accumulation of this value during Φ 2, these two are settled innon-overlapping. For instead, the first random coefficient which corresponds to element row oneand column one from the random matrix, Φ 11 , and the first signal sample X 1 , are multiplied whenΦ 1 is closed. When Φ 2 is closed, the result is accumulated in the integration capacitance. Onceagain, when Φ 1 is closed, Φ 12 and X 2 are multiplied, and during the next high level Φ 2 , the resultof this operation is added to the previous value has been accumulated, and so on. The MostSignificant Bit (MSB) is used as sign bit.79

80Figure B.2.3.2. Binary-weighted SC MDAC/summer for CS.

Appendix CC.1. Analog ImplementationThere is a large range of applications in which random generation is necessary in order to beused in signal processing blocks. Radiofrequency communications signal mixing, test systemsand more recently biosignal compression based on CS are the most relevant ones. By means ofan analog implementation of such randomness, a true random generation is achieved at theexpense of a larger circuit complexity of the integration of more exotic circuitry. The maintechniques have been developed are: direct amplification of noise, high-frequency oscillatorsampling and randomness generation based on chaotic systems, and they are described below.C.1.1. Direct Amplification of NoiseThis method uses a device noise to make a decision of a bit 1 or 0 depending if the signal isgreater than certain threshold or vice versa. This can be done by amplifying the white noise of aresistor and then using a comparator to obtain a random bit. These schemes need a high-gainbandwidthlow-offset amplifier due to the fact that if a low-bandwidth amplifier is used, theoutput noise spectrum can be concentrated around DC and so, noise samples are correlated.Thus, they are not suitable for Radio Frequency Identification, RFID, systems. Animplementation has been presented in [29], and the main architecture is shown in Fig.C.1.1.1.This approach is not feasible to an on-chip application, due to area constraints.Figure C.1.1.1. Random generator based on direct amplification of noise [29].C.1.2. High-Frequency Oscillator Sampling [29]A TRNG can be implemented by combining a low-frequency jitter clock and using it to sample ahigh-frequency oscillator. The timing jitter is a stochastic phenomenon caused y thermal noisepresent in the transistors of a ring oscillator. The drawback of this procedure is that themegahertz generation is power hungry, so it is not an option for an on-chip CS design.81

The main model is shown in Fig.C.1.2.1, it can be observed as the final random bit stream is theresult of the subsampling of a high-frequency source of oscillations and storing thecorresponding values in a D Flip-Flop, (DFF).Figure C.1.2.1. Basic oscillator-based TRNG.82

Appendix DOutput 4FF-PRBS Output 5FF-PFBS Output1 3 32 1 23 1 34 1 45 1 56 4 27 4 38 4 49 4 510 1 111 2 112 3 113 4 114 2 515 2 316 3 5Table D.1. Selected crosses for 16 outputs through a 4FF-PRBS and a 5FF-PRBS.83

Appendix EE.1. AmplificationThe small amplitude of neural signals and the high impedance of the electrode-tissue interfaceforce to use a front-end amplifier before processing of digitizing the input signal [33]. The mainfeatures are required in the LNA to be used are shorted in Table E.1.1.FeatureNeural Signal AmplificationInput referred noiseLow to revolve spikes of 30 μVDynamic range± 1-10 mV to convey EEG peaksInput impedanceHigher than the electrode-tissue interfaceDC input currentNegligibleFrequency band Depending on signals of interest (see Table 2.1.1)Power ConsumptionLow to avoid neural tissue heatingCommon Mode Rejection High in order to minimize interference from power lineRatio (CMRR)noise and close proximity between electrode andPower Supply Rejection amplifier to minimize capacitive and inductive coupledRatio (PSRR)interferometersTable E.1.1. Main features of a front-end amplifier for neural recording.Besides the characteristics listed behind, the LNA has to block DC offset present at theelectrode-tissue interface to prevent saturation of the amplifier and it has to consume littlesilicon area and use few or no off-chip components to minimize the dimensions. An example ofOTA-based neural amplifier was presented in 2003 by Harrison and Charles.E.2. Signal Digital ConversionIn order to achieve a robust transmission of the signals which have been registered, theamplified and eventually compressed information has to be digitized. There is an extensivevariety of techniques for performing analog-to-digital conversion which are included in Fig.E.2.1.Choice of one specific technique depends on the signal of interest, as well as the area andpower constraints which have to be faced by the designer. As it is depicted below, a data rate of15 kS/s is enough in most of clinical applications, but it requires a data stream of 15Mb/s for 100electrodes, which is impossible to transmit across the skull and the scalp. RF links are limited bythe tissue electromagnetic absorption, which follows an f 2 ratio.84

Figure E.2.1. Several techniques to digitize different kind of neural signals.85

GlossaryADC: Analog-to-Digital ConverterAP: Action potentialBAN: Body Area NetworkBCI: Brain-Computer InterfaceBCQP: Bound Constrained Quadratic ProgrammingBP: Basis PursuitBPDN : Basis Pursuit De-NoisingBW : BandwithdCGP : Conjugate Gradients PursuitCS : Compressive Sensing or Compressive SamplingCoSaMP: Compressive Sampling Matching PursuitECG: ElectrocardiogramECoG: ElectrocorticogramEEG: EectroencefalogramGP: Gradient ProjectionGPSR: Gradient Projection for Sparse Reconstruction (GPSR)HMT: Hidden Markov TreeIHT: Iterative Hard ThresholdingIP: Interior PointIRWL1: Iterative Reweighted l 1-norm Minimization AlgorithmIST: Iterative Shrinkage/ThresholdingLARS: Least-Angle RegressionLASSO: Least Absolute Shrinkage and Selection OperatorLFSR: Linear Feedback Shift RegisterLNA: Low Noise AmplifierLPF: Low Pass Filter87

LSQR: Least Squares Quadratic RegressionMDAC: Multiplying Digital-to-Analog ConverterMP: Matching Pursuit MPMSB: More Significant BitOMP: Orthogonal Matching PursuitOTA: Operational Transconductance AmplifierPCGP: Preconditioned Conjugate Gradient PursuitPRBS : Pseudorandom Binary SequencePSD: Power Spectra DensityRAmP: Restricted Amplification PropertyRC: Random ConvolutionRFID: Radio Frequency IdentificationRIP: RestrictedRDG: Reduced Conjugate GradientROMP: Regularised Orthogonal Matching PursuitSC: Switched CapacitorSCS: Spatial Compressive SensingSNR: Signal-to-Noise RatioStCGP: Stagewise Conjugate Gradient PursuitStOMP: Stagewise Orthogonal Matching PursuitSP: Subspace PursuitSWOMP: Stagewise Weak Orthogonal Matching PursuitTRNG: True Random Number GenerationWCGP: Weak Conjugate Gradient Pursuit88

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