Compressive Sensing system for recording of ECoG signals in-vivo

If calculations in Appendix B (Eq.25) are compared with Eq.11, it is clear that the total powerconsumption for an analog path does not fit anymore with the relation which has been depictedin Fig.B.2.2.2, and hence, it has been probed that a power consumption saving can be carriedout for an analog implementation of the CS based path for neural signals acquisition bymodifying the known architecture of the system and applying the limiting conditions which arespecific for sparse signals.3.2. Single and Multi Channel ApproachBy keeping in mind the analysis has been presented in 3.1, a new block diagram sketch for aCS analog path can be considered to be implemented. The proposed system is shown inFig.3.2.1. In order to reduce the power spending, one front-end LNA can be considered, and sothe input signal is copied in each of the paths of a channel to be mixed and integrated. Similarly,one ADC can be used by previously multiplexing the compressed signal components of each ofthe paths. It has to be considered the data rate in each of the blocks. At the sensor, the inputsignal is sampled at Nyquist rate, so if the acquisition system is focussed in ECoG signals,which have a bandwidth of approximately 10 kHz (see Table 2.1.1), a minimal samplingfrequency, f s , of 20 kHz has to be taken into consideration. After compression, the data rate ineach of the paths becomes f s /N, and it has to be forwarded to the ADC without a data loss,because of which the multiplexer and the ADC have to be designed to work at a rate of M timesf s /N.Figure 3.4.1. Analog implementation proposal for neural acquisition channel.Depending on the number of input samples, N, which are considered in each integration periodand the compression ratio is wanted to be exploit to maintain as high as possible the SNR of thereconstructed signal after the recovery processing, the number of channels, M, is integrated onchip varies. In the same way, area and power constraints are determinant to adjust this relation.In this point, two main milestones have to be established to carry out the circuitry model isincluded in Fig. 3.2.1: a) ultra low power blocks have to be employed in order to keep thesystem under reasonable power spending levels; b) ultra compact blocks have to be designed,38