Compressive Sensing system for recording of ECoG signals in-vivo

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If calculations in Appendix B (Eq.25) are compared with Eq.11, it is clear that the total powerconsumption for an analog path does not fit anymore with the relation which has been depictedin Fig.B.2.2.2, and hence, it has been probed that a power consumption saving can be carriedout for an analog implementation of the CS based path for neural signals acquisition bymodifying the known architecture of the system and applying the limiting conditions which arespecific for sparse signals.3.2. Single and Multi Channel ApproachBy keeping in mind the analysis has been presented in 3.1, a new block diagram sketch for aCS analog path can be considered to be implemented. The proposed system is shown inFig.3.2.1. In order to reduce the power spending, one front-end LNA can be considered, and sothe input signal is copied in each of the paths of a channel to be mixed and integrated. Similarly,one ADC can be used by previously multiplexing the compressed signal components of each ofthe paths. It has to be considered the data rate in each of the blocks. At the sensor, the inputsignal is sampled at Nyquist rate, so if the acquisition system is focussed in ECoG signals,which have a bandwidth of approximately 10 kHz (see Table 2.1.1), a minimal samplingfrequency, f s , of 20 kHz has to be taken into consideration. After compression, the data rate ineach of the paths becomes f s /N, and it has to be forwarded to the ADC without a data loss,because of which the multiplexer and the ADC have to be designed to work at a rate of M timesf s /N.Figure 3.4.1. Analog implementation proposal for neural acquisition channel.Depending on the number of input samples, N, which are considered in each integration periodand the compression ratio is wanted to be exploit to maintain as high as possible the SNR of thereconstructed signal after the recovery processing, the number of channels, M, is integrated onchip varies. In the same way, area and power constraints are determinant to adjust this relation.In this point, two main milestones have to be established to carry out the circuitry model isincluded in Fig. 3.2.1: a) ultra low power blocks have to be employed in order to keep thesystem under reasonable power spending levels; b) ultra compact blocks have to be designed,38
y specially considering the integration capacitances which are necessary in each of the paths,and which widely increase the total area of a channel, which in composed of M paths.Depending on the capacitances of the integrators, which can be large to correctly implement theintegration at these frequencies, the complete channel could be implemented o n chip in asaving area way. In Chapter 6, it is submitted the new proposal for the mixer-integrator pair ofeach of the paths.4. Random Matrix GenerationAlong the previous chapters, the necessity of a measurement matrix as much incoherent aspossible with respecting to the sparsifying basis has been shown. Different kinds ofimplementations of the random matrix have been considered in [1, 3, 21, 22, 34, 35, 36]. A newrandom matrix implementation has been researched in order to determine which is the lowestpower cost, less area consuming approach and overall the one which leads to the largestnumber of parallelized outputs, which, as it is introduced in 4.2.2.3, is an interesting capability tobe applied in multichannel signal acquisition implementations.Main approaches to the obtaining of random sequences generation are the True RandomNumber Generation, (TRNG), based on analog domain, and the Pseudorandom BinaryGeneration, (PRBS), and mostly based on digital domain. Analog random generation is includedin Appendix C, regarding to digital implementation, it is included below.4.1. Digital Implementation: Pseudo Random Binary SequencePseudorandom Random Binary Sequence circuits (PRBS) perform an alternative architecturewhich sacrifices true randomness generation for simplicity in the implementation, giving rise tomore feasible design which has a known period of randomness, after which the same sequenceis repeated. In any case if the random sequence is long enough not to be repeated during thecircuits operation, this procedure constitutes an optimal solution. Henceforward during thischapter, main properties of PRBS as well as methodologies of functioning are discussed.4.1.1. Basics of PRB: Serial and Parallel ImplementationConventional PRBS are based in Linear Feedback Shift Registers (LFSR), which consist of asequence of DFF which are connected is in series or in parallel by using XOR gates. Theposition of the XOR gates, which are called taps of the LFSR, varies depending of the length ofthe random sequence to be achieved.39
Page 1: August, 31 th , 2012Compressive Sen
Page 5: The present project has been submit
Page 9: AbstractThe project “Compressive
Page 13: RiassuntoIl progetto “Compressive
Page 17 and 18: IndexAcknowledgments 7Abstract 9Gan
Page 19 and 20: E.2. Signal Digital Conversion 84Gl
Page 21 and 22: Figure 6.2.1.2. Input signal Spectr
Page 23: Index of TablesTable 2.1.1. Summary
Page 26 and 27: Figure 1.1. Energy a power costs fo
Page 29 and 30: 2. State of the art2.1 Neural Signa
Page 31 and 32: patterns in response to visual targ
Page 33 and 34: 2.4. Compressive Sensing2.4.1. Comp
Page 35 and 36: 2.4.2. Sparsifying basesSparsifying
Page 37: It is worth mentioning that compres
Page 41 and 42: Figure 4.1.1.1. LSFR parallel (top)
Page 43 and 44: 4.1.3. Serial Implementation with t
Page 45: 4.1.4. Randomness CheckingIn order
Page 48 and 49: een designed independently as it is
Page 50 and 51: time, which has been approximated a
Page 52 and 53: Figure 5.2.2. Original and reconstr
Page 54 and 55: 6. Analog Path Design6.1. Design Di
Page 56 and 57: The spectra of the input signal hav
Page 58 and 59: Figure 6.2.1.4. LASSO reconstructio
Page 60 and 61: Figure 6.2.2.3. Compressed signals
Page 62 and 63: In this way, the pole frequency is
Page 64 and 65: A can be floating when the mixing s
Page 66 and 67: Figure 6.2.4.4. BPDN method reconst
Page 68 and 69: Figure 6.2.5.3. BPDN method reconst
Page 71 and 72: 7. Conclusions7.1. RemarksAs it is
Page 73: AppendixAppendix AConvexOptimizatio
Page 76 and 77: The total power cost for the digita
Page 78 and 79: Figure B.2.2.1. Block diagram for a
Page 80 and 81: 80Figure B.2.3.2. Binary-weighted S
Page 82 and 83: The main model is shown in Fig.C.1.
Page 84 and 85: Appendix EE.1. AmplificationThe sma
Page 87 and 88: GlossaryADC: Analog-to-Digital Conv
Page 89 and 90:
References[1] D. Gangopadhyay et al
Page 91:
[35] M.F. Duarte et. al., Recovery
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Compressive Sensing system for recording of ECoG signals in-vivo

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