Compressive Sensing system for recording of ECoG signals in-vivo

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The total power cost for the digital implementation of a multipath CS encoder, without taking intoconsideration the random generation, has been calculated in [3] as:(24)The digital CS channel, including matrix generation and clock consumption, consumes 1.9 μWat 0.6 V for sampling frequencies below 20kS/s. In Fig. B.1.2 is included the power consumptionanalysis regarding to the bandwidth of the input signal as it has been presented in [3]. Byconsidering the power consumption estimation of Eq.24, it is clear that the largest contributionto the power spending is the result of the ADC and the amplifier.Figure B.1.2. Power consumption versus bandwidth for the digital implementation of a CS path.Specifications from Table 3.1.1 have been taken into consideration.B.2. Analog ImplementationB.2.1. Current ModeIn [27], it is presented a current-mode circuit implementation of CS architecture to be used in amultichannel receiver system which is used to digitize at 1.5 GHz the signals of each channel,which are sparse in frequency domain, and spread it over the entire bandwidth. In Fig. B.2.1.1 itis observed the circuit proposal to this application. In the approach of [27], an OperationalTransconductance Amplifier (OTA) and an ADC are considered for each of the paths. It is worthmentioning, that the integrators consist of two time-interleaved branches which provide76
successive integration windows in order to develop a Parallel Segmented CS (PSCS)architecture, which achieves a decreasing in the necessary number of implemented paths perchannel.Figure B.2.1.1. Circuit implementation of the proposed CS receiver.By exploiting signal sparsity, the system accomplishes 44 dB overall SNRD, with a powerconsumption of 120.8 mW. Others critical specifications about the design have been included inTable B.2.1.1.ParameterSpecificationTechnology90 nm CMOSParallel paths 8Chip area (8 paths)1000 μm x 1400 μmBandwidth (BW f )10 MHz - 1.5 GHzTable B.2.1.1. CS model specifications.B.2.2. Voltage ModeIn [3], Chen and Chandrakasan have proposed a voltage mode-based architecture for ananalog channel for a wireless neural CS implementation which has been depicted in Fig.B.2.2.1.The registered signal is amplified by an operational transconductance ampliflier (OTA) in eachof the M paths of the CS operation, and afterwards, the N samples are multiplied by Ncoefficients of the random matrix and accumulated in each of the rows before being sent atcompressed rate to the dedicated ADC which has been included in each of the paths. At theoutput of each of the ADC the final digitized compressed value is acquired. The exploit of oneamplifier per channel widely increase the power consumption as it is shown in the Eq.24. In theChapter 3.3 the necessity of one OTA and ADC per path are deeply discussed in order to clarifythe feasibility of an analog implementation for a neural channel.77
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August, 31 th , 2012Compressive Sen
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The present project has been submit
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AbstractThe project “Compressive
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RiassuntoIl progetto “Compressive
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IndexAcknowledgments 7Abstract 9Gan
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E.2. Signal Digital Conversion 84Gl
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Figure 6.2.1.2. Input signal Spectr
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Index of TablesTable 2.1.1. Summary
Page 26 and 27: Figure 1.1. Energy a power costs fo
Page 29 and 30: 2. State of the art2.1 Neural Signa
Page 31 and 32: patterns in response to visual targ
Page 33 and 34: 2.4. Compressive Sensing2.4.1. Comp
Page 35 and 36: 2.4.2. Sparsifying basesSparsifying
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Page 39 and 40: y specially considering the integra
Page 41 and 42: Figure 4.1.1.1. LSFR parallel (top)
Page 43 and 44: 4.1.3. Serial Implementation with t
Page 45: 4.1.4. Randomness CheckingIn order
Page 48 and 49: een designed independently as it is
Page 50 and 51: time, which has been approximated a
Page 52 and 53: Figure 5.2.2. Original and reconstr
Page 54 and 55: 6. Analog Path Design6.1. Design Di
Page 56 and 57: The spectra of the input signal hav
Page 58 and 59: Figure 6.2.1.4. LASSO reconstructio
Page 60 and 61: Figure 6.2.2.3. Compressed signals
Page 62 and 63: In this way, the pole frequency is
Page 64 and 65: A can be floating when the mixing s
Page 66 and 67: Figure 6.2.4.4. BPDN method reconst
Page 68 and 69: Figure 6.2.5.3. BPDN method reconst
Page 71 and 72: 7. Conclusions7.1. RemarksAs it is
Page 73: AppendixAppendix AConvexOptimizatio
Page 78 and 79: Figure B.2.2.1. Block diagram for a
Page 80 and 81: 80Figure B.2.3.2. Binary-weighted S
Page 82 and 83: The main model is shown in Fig.C.1.
Page 84 and 85: Appendix EE.1. AmplificationThe sma
Page 87 and 88: GlossaryADC: Analog-to-Digital Conv
Page 89 and 90: References[1] D. Gangopadhyay et al
Page 91: [35] M.F. Duarte et. al., Recovery
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