Compressive Sensing system for recording of ECoG signals in-vivo

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6. Analog Path Design6.1. Design DiscussionThe multipath neural acquisition system for a channel that is shown in Fig.3.4.1 has beenchosen as the implementation to be developed. It is included again below as reference duringthe design discussion. Having a look of the complete design it is clear that the complexity ofimplementing all of the blocks overcomes the scope of a final master thesis, and so, in order tointroduce design improvements, the design has had to be limited to some blocks, putting off thetotal implementation for future steps in the CS field.As it is commented in the Chapter 1 and 2, the main constraints of the system are: a) area, dueto the act that the chip to be placed over individuals brain has to be as smaller as possible, andso less invasive; and b) power consumption, because of the fact that a large battery cannot beincluded in the system, and overall safety issues, because low power consumption means lowheat dissipation and so the chip will be permitted as bioapplication. By the other hand, thesystem is not conditioned by time constraints, so any extra effort is employed in order to make ahigh-speed design. That is since real neural signals have a low bandwidth, and so there is noreason into exploit high-speed features which will be not used.By considering the main blocks of the system, and the design problems with which each of themis related, it is stated that the LNA, the ADC and the multiplexer boil over the time limitations,and so, previous designs are considered. By the other hand, a good design of howimplementing the mixing and integration blocks have not been already done in the state of theart, and so, it has been considered as the best feasible design to be completed under thescenario of this project. The main goal for being considered in the improvement is area savingin order to achieve an architecture in which the miniaturization of the integration capacitances,which regarding the literature are too large components of the integrator circuitry, could be carryout. Along the next points the different blocks of the multipath analog approach are analyzed indetails.A discussion about the amplification and conversion operations has been included in AppendixE. In order to address the mixer-integrator design, the same parameters which have beenconsidered during the Matlab and Simulink models are taken for the circuitry design inCadence. They are referred in Table 5.1. The same synthetic input signal that has been usedfor Matlab-Simulink simulations has been introduced into Cadence model. Similarly, the randommatrices which have been considered are those based on the new random generator presentedin Chapter 4 and the one which can be generated by randint in Matlab.54
6.2. Mixing and IntegrationFirst of all, the purposes of the re-design of the mixing and integration blocks are: a) reducingarea and b) implementing together the mixer and the integrator, and not integrating as differentblocks. In order to study which are the limitations in performance and the eventual problemsthat have to be faced in the mixer-integrator design, several known models have beenimplemented and checked within a multipath channel in Cadence, by taking into considerationdifferent configurations for the integrator: passive, active and switched capacitors-based one.These topologies are introduced below by using the technology TSMC018.6.2.1. Passive IntegrationA passive integrator is a simple four-terminal network consisting of two passive elements, aresistor and a capacitor as it is included in Fig.6.2.1.2. For each of the paths, integration iscarried out and the final integration value is obtained with a scale factor which depends on RCand the integration time. Thereby, the final output result accumulated in the integrator of eachpath is obtained as:(16)Where is the integration interval, which corresponds to the inverse of the samplingfrequency, and so it is . The circuit in Fig.6.2.1.1 acts as a Low Pass Filter (LPF) forfrequencies which are under the pole frequency, f p , which defined as (see Eq.17).Figure 6.5.1.1. Mixer and passive integrator circuitry.The circuit performs as integrator for input signals whose frequency is over f p because of thefact that the constant of time of the integrator has to be larger than the period of the signal.According to this, the integrator has to be designed in order to fix the pole frequency below thefrequencies of interest that have to be integrated.(17)55
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August, 31 th , 2012Compressive Sen
Page 5: The present project has been submit
Page 9: AbstractThe project “Compressive
Page 13: RiassuntoIl progetto “Compressive
Page 17 and 18: IndexAcknowledgments 7Abstract 9Gan
Page 19 and 20: E.2. Signal Digital Conversion 84Gl
Page 21 and 22: Figure 6.2.1.2. Input signal Spectr
Page 23: Index of TablesTable 2.1.1. Summary
Page 26 and 27: Figure 1.1. Energy a power costs fo
Page 29 and 30: 2. State of the art2.1 Neural Signa
Page 31 and 32: patterns in response to visual targ
Page 33 and 34: 2.4. Compressive Sensing2.4.1. Comp
Page 35 and 36: 2.4.2. Sparsifying basesSparsifying
Page 37 and 38: It is worth mentioning that compres
Page 39 and 40: y specially considering the integra
Page 41 and 42: Figure 4.1.1.1. LSFR parallel (top)
Page 43 and 44: 4.1.3. Serial Implementation with t
Page 45: 4.1.4. Randomness CheckingIn order
Page 48 and 49: een designed independently as it is
Page 50 and 51: time, which has been approximated a
Page 52 and 53: Figure 5.2.2. Original and reconstr
Page 56 and 57: The spectra of the input signal hav
Page 58 and 59: Figure 6.2.1.4. LASSO reconstructio
Page 60 and 61: Figure 6.2.2.3. Compressed signals
Page 62 and 63: In this way, the pole frequency is
Page 64 and 65: A can be floating when the mixing s
Page 66 and 67: Figure 6.2.4.4. BPDN method reconst
Page 68 and 69: Figure 6.2.5.3. BPDN method reconst
Page 71 and 72: 7. Conclusions7.1. RemarksAs it is
Page 73: AppendixAppendix AConvexOptimizatio
Page 76 and 77: The total power cost for the digita
Page 78 and 79: Figure B.2.2.1. Block diagram for a
Page 80 and 81: 80Figure B.2.3.2. Binary-weighted S
Page 82 and 83: The main model is shown in Fig.C.1.
Page 84 and 85: Appendix EE.1. AmplificationThe sma
Page 87 and 88: GlossaryADC: Analog-to-Digital Conv
Page 89 and 90: References[1] D. Gangopadhyay et al
Page 91: [35] M.F. Duarte et. al., Recovery
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Compressive Sensing system for recording of ECoG signals in-vivo

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