Compressive Sensing system for recording of ECoG signals in-vivo

approximation is discussed by taking into consideration a different block diagram, which hasbeen considered as a better approximation to the analog implementation of a CS path in termsof power saving. In the same way, Chapter 6 a new path design has been considered byexploiting an area saving on chip.B.2.3. Charge ModeAn incremental Sigma-Delta ADC (ΣΔ-ADC), for CS applications has been submitted in [28]. Thenovelty of this implementation is the simultaneity of the acquisition and quantization of CSmeasurements, due to the fact that a Switched Capacitor (SC) integrator of has beenincorporated in the close loop of the converter. The converter occupies a small area of 0.047mm 2 on a target 0.5 μm CMOS process, and it can be suitable for CS applications. A sketch ofthe complete implementation has been depicted in Fig. B.2.3.1.Figure B.2.3.1. Switched Capacitor circuit implementation of the CS ADC.In [1] it has been proposed a binary-weighted SC Multiplying Digital-to-Analog Converter(MDAC) for the processing of ECG and EMG signals. The architecture that is included inFig.B.2.3.2. implements a multiplication between the actual random coefficient and the inputsignal sample during Φ 1 and the accumulation of this value during Φ 2, these two are settled innon-overlapping. For instead, the first random coefficient which corresponds to element row oneand column one from the random matrix, Φ 11 , and the first signal sample X 1 , are multiplied whenΦ 1 is closed. When Φ 2 is closed, the result is accumulated in the integration capacitance. Onceagain, when Φ 1 is closed, Φ 12 and X 2 are multiplied, and during the next high level Φ 2 , the resultof this operation is added to the previous value has been accumulated, and so on. The MostSignificant Bit (MSB) is used as sign bit.79