Compressive Sensing system for recording of ECoG signals in-vivo

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By means of the serial implementation, a random N-bits sequence is developed by getting oneby one the bits at the output each clock cycle. In the case of the parallel configuration, the XORoperation becomes more complex, but each time there are m random bits at the output, where, relying on the chosen parallel architecture. Thereby the choice of the architecture willdepend on the time, area and power constraints of the system, in the case in which areasupposes a critical feature, parallel implementation is discouraged because more DFF areneeded in the block; on the other hand if the system strictly needs k random bits each clockcycle, a parallel LSFR can be implemented. Similarly, in order to face the design of a serial orparallel LSFR, but more necessarily in the latter, an aim of the design will be decreasing thepower consumption as much as possible by using ultra-low power consuming Flip-Flops.Furthermore, the number of DFFs, k, which are needed to implement a detailed length of bitssequence, N, is related in correspondence with the random sequence period shown in Eq.13,this relation is the time-period of the Maximum Length Sequence, (MLS). An important thing tonote is that all XOR tapping configurations do not lead to MLS but to get these MLS of period 2 k– 1, a primitive polynomial h(x) of degree k is required. The algebraic terms occurring in thispolynomial represent the LFSR tapping positions for MLS. A primitive polynomial is anirreducible polynomial of that degree. For example, for the serial LFSR of the Fig.4.2.1.2 theprimitive polynomial is:(12)Changes in the polynomial lead to change in the occurring output sequence. After N bits, thesequence will repeat itself, and so, this must be taken into consideration in order to avoidcorrelations in or between the different signals which are being modified by the randomsequence.(13)In the case of serial implementation, N bits will be achieved at the output of the signal after Nclock periods. For the other hand, in parallel implementation, each clock period, m bits willpropagate across the k outputs each clock period. In Fig. 4.1.1.1 there have been included anexample of a parallel (top) and serial (bottom) LFSR configurations with k = 5, both of thembased on five DFFs. It can be observed that the parallel one is implemented by using five DFFsand four XORs, in addition to the circuitry related with connections, port and clock setting. Theserial architecture is more compact, because it is implemented with five DFFs and one XOR,plus extra circuitry.40
Figure 4.1.1.1. LSFR parallel (top) and serial (bottom) architectures based on five DFFs design.Figure 4.1.1.2. Galois (top) and Fibonacci (bottom) configurations for a k = 16 LFSR.In the case of serial LFSR, here are two types of architectures, Fibonacci and Galois, the latterhas been chosen to implement the PRBS because the concatenation of the gates gives raise toone DFF in the critical path, and so less execution speed is needed. A comparison for k = 16DFFs is included in Fig.4.1.1.2, Galois (top) and Fibonacci (bottom). It can be observed that inthis case taps are in positions 16, 14, 13 and 1. As previously it has been stated, for an k-bitsLFRS, the maximum possible outcome can be – bit-vectors or states because a state withbit-vector containing all ‘0’s will keep repeating itself not allowing any other state to occur (allXOR outputs will always be ‘0’). Measurement matrix generation has to be carry though bywarranting that all its rows are uncorrelated between each others. Thereby, incoherencebetween basis and measurement matrix is insured and the CS recovery can be implemented.On the other hand, in many applications, as the ones based on Random Convolution, (RC) [21],it is a target simultaneously obtaining several random coefficients in order to carry out thecompression. By taking into account these requirements, random generation block becomes acritical design issue, and its study has to be carefully determined in other to realize a compactand efficient compression in CS systems on-chip.41
Page 1: August, 31 th , 2012Compressive Sen
Page 5: The present project has been submit
Page 9: AbstractThe project “Compressive
Page 13: RiassuntoIl progetto “Compressive
Page 17 and 18: IndexAcknowledgments 7Abstract 9Gan
Page 19 and 20: E.2. Signal Digital Conversion 84Gl
Page 21 and 22: Figure 6.2.1.2. Input signal Spectr
Page 23: Index of TablesTable 2.1.1. Summary
Page 26 and 27: Figure 1.1. Energy a power costs fo
Page 29 and 30: 2. State of the art2.1 Neural Signa
Page 31 and 32: patterns in response to visual targ
Page 33 and 34: 2.4. Compressive Sensing2.4.1. Comp
Page 35 and 36: 2.4.2. Sparsifying basesSparsifying
Page 37 and 38: It is worth mentioning that compres
Page 39: y specially considering the integra
Page 43 and 44: 4.1.3. Serial Implementation with t
Page 45: 4.1.4. Randomness CheckingIn order
Page 48 and 49: een designed independently as it is
Page 50 and 51: time, which has been approximated a
Page 52 and 53: Figure 5.2.2. Original and reconstr
Page 54 and 55: 6. Analog Path Design6.1. Design Di
Page 56 and 57: The spectra of the input signal hav
Page 58 and 59: Figure 6.2.1.4. LASSO reconstructio
Page 60 and 61: Figure 6.2.2.3. Compressed signals
Page 62 and 63: In this way, the pole frequency is
Page 64 and 65: A can be floating when the mixing s
Page 66 and 67: Figure 6.2.4.4. BPDN method reconst
Page 68 and 69: Figure 6.2.5.3. BPDN method reconst
Page 71 and 72: 7. Conclusions7.1. RemarksAs it is
Page 73: AppendixAppendix AConvexOptimizatio
Page 76 and 77: The total power cost for the digita
Page 78 and 79: Figure B.2.2.1. Block diagram for a
Page 80 and 81: 80Figure B.2.3.2. Binary-weighted S
Page 82 and 83: The main model is shown in Fig.C.1.
Page 84 and 85: Appendix EE.1. AmplificationThe sma
Page 87 and 88: GlossaryADC: Analog-to-Digital Conv
Page 89 and 90: References[1] D. Gangopadhyay et al
Page 91:
[35] M.F. Duarte et. al., Recovery
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Compressive Sensing system for recording of ECoG signals in-vivo

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